478 lines
17 KiB
Python
Executable File
478 lines
17 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import pcie
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import pcie_usp
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import dma_ram
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import axis_ep
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module = 'dma_if_pcie_us_wr'
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testbench = 'test_%s_512' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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AXIS_PCIE_DATA_WIDTH = 512
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AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32)
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AXIS_PCIE_RQ_USER_WIDTH = 137
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RQ_SEQ_NUM_WIDTH = 4 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 6
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RQ_SEQ_NUM_ENABLE = 1
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SEG_COUNT = max(2, int(AXIS_PCIE_DATA_WIDTH*2/128))
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SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT
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SEG_ADDR_WIDTH = 12
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SEG_BE_WIDTH = int(SEG_DATA_WIDTH/8)
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RAM_SEL_WIDTH = 2
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RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+(SEG_COUNT-1).bit_length()+(SEG_BE_WIDTH-1).bit_length()
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PCIE_ADDR_WIDTH = 64
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LEN_WIDTH = 16
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TAG_WIDTH = 8
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OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1)
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TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1)
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TX_FC_ENABLE = 1
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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s_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
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s_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
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s_axis_rq_tvalid = Signal(bool(0))
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s_axis_rq_tlast = Signal(bool(0))
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s_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
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m_axis_rq_tready = Signal(bool(0))
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s_axis_rq_seq_num_0 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
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s_axis_rq_seq_num_valid_0 = Signal(bool(0))
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s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
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s_axis_rq_seq_num_valid_1 = Signal(bool(0))
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pcie_tx_fc_ph_av = Signal(intbv(0)[8:])
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pcie_tx_fc_pd_av = Signal(intbv(0)[12:])
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s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:])
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s_axis_write_desc_ram_sel = Signal(intbv(0)[RAM_SEL_WIDTH:])
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s_axis_write_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:])
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s_axis_write_desc_len = Signal(intbv(0)[LEN_WIDTH:])
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s_axis_write_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
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s_axis_write_desc_valid = Signal(bool(0))
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ram_rd_cmd_ready = Signal(intbv(0)[SEG_COUNT:])
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ram_rd_resp_data = Signal(intbv(0)[SEG_COUNT*SEG_DATA_WIDTH:])
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ram_rd_resp_valid = Signal(intbv(0)[SEG_COUNT:])
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enable = Signal(bool(0))
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requester_id = Signal(intbv(0)[16:])
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requester_id_enable = Signal(bool(0))
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max_payload_size = Signal(intbv(0)[3:])
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# Outputs
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s_axis_rq_tready = Signal(bool(0))
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m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
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m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
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m_axis_rq_tvalid = Signal(bool(0))
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m_axis_rq_tlast = Signal(bool(0))
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m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
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m_axis_rq_seq_num_0 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
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m_axis_rq_seq_num_valid_0 = Signal(bool(0))
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m_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
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m_axis_rq_seq_num_valid_1 = Signal(bool(0))
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s_axis_write_desc_ready = Signal(bool(0))
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m_axis_write_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
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m_axis_write_desc_status_valid = Signal(bool(0))
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ram_rd_cmd_sel = Signal(intbv(0)[SEG_COUNT*RAM_SEL_WIDTH:])
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ram_rd_cmd_addr = Signal(intbv(0)[SEG_COUNT*SEG_ADDR_WIDTH:])
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ram_rd_cmd_valid = Signal(intbv(0)[SEG_COUNT:])
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ram_rd_resp_ready = Signal(intbv(0)[SEG_COUNT:])
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# Clock and Reset Interface
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user_clk=Signal(bool(0))
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user_reset=Signal(bool(0))
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sys_clk=Signal(bool(0))
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sys_reset=Signal(bool(0))
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# PCIe DMA RAM
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dma_ram_inst = dma_ram.PSDPRam(2**16)
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dma_ram_pause = Signal(bool(0))
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dma_ram_port0 = dma_ram_inst.create_read_ports(
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user_clk,
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ram_rd_cmd_addr=ram_rd_cmd_addr,
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ram_rd_cmd_valid=ram_rd_cmd_valid,
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ram_rd_cmd_ready=ram_rd_cmd_ready,
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ram_rd_resp_data=ram_rd_resp_data,
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ram_rd_resp_valid=ram_rd_resp_valid,
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ram_rd_resp_ready=ram_rd_resp_ready,
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pause=dma_ram_pause,
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name='port0'
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)
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# sources and sinks
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write_desc_source = axis_ep.AXIStreamSource()
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write_desc_source_logic = write_desc_source.create_logic(
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user_clk,
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user_reset,
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tdata=(s_axis_write_desc_pcie_addr, s_axis_write_desc_ram_sel, s_axis_write_desc_ram_addr, s_axis_write_desc_len, s_axis_write_desc_tag),
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tvalid=s_axis_write_desc_valid,
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tready=s_axis_write_desc_ready,
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name='write_desc_source'
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)
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write_desc_status_sink = axis_ep.AXIStreamSink()
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write_desc_status_sink_logic = write_desc_status_sink.create_logic(
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user_clk,
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user_reset,
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tdata=(m_axis_write_desc_status_tag,),
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tvalid=m_axis_write_desc_status_valid,
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name='write_desc_status_sink'
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)
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# PCIe devices
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rc = pcie.RootComplex()
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mem_base, mem_data = rc.alloc_region(16*1024*1024)
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dev = pcie_usp.UltrascalePlusPCIe()
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dev.pcie_generation = 3
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dev.pcie_link_width = 16
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dev.user_clock_frequency = 256e6
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rc.make_port().connect(dev)
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cq_pause = Signal(bool(0))
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cc_pause = Signal(bool(0))
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rq_pause = Signal(bool(0))
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rc_pause = Signal(bool(0))
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pcie_logic = dev.create_logic(
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# Completer reQuest Interface
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m_axis_cq_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
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m_axis_cq_tuser=Signal(intbv(0)[183:]),
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m_axis_cq_tlast=Signal(bool(0)),
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m_axis_cq_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
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m_axis_cq_tvalid=Signal(bool(0)),
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m_axis_cq_tready=Signal(bool(1)),
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pcie_cq_np_req=Signal(intbv(3)[2:]),
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pcie_cq_np_req_count=Signal(intbv(0)[6:]),
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# Completer Completion Interface
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s_axis_cc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
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s_axis_cc_tuser=Signal(intbv(0)[81:]),
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s_axis_cc_tlast=Signal(bool(0)),
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s_axis_cc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
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s_axis_cc_tvalid=Signal(bool(0)),
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s_axis_cc_tready=Signal(bool(0)),
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# Requester reQuest Interface
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s_axis_rq_tdata=m_axis_rq_tdata,
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s_axis_rq_tuser=m_axis_rq_tuser,
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s_axis_rq_tlast=m_axis_rq_tlast,
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s_axis_rq_tkeep=m_axis_rq_tkeep,
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s_axis_rq_tvalid=m_axis_rq_tvalid,
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s_axis_rq_tready=m_axis_rq_tready,
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pcie_rq_seq_num0=s_axis_rq_seq_num_0,
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pcie_rq_seq_num_vld0=s_axis_rq_seq_num_valid_0,
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pcie_rq_seq_num1=s_axis_rq_seq_num_1,
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pcie_rq_seq_num_vld1=s_axis_rq_seq_num_valid_1,
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# pcie_rq_tag0=pcie_rq_tag0,
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# pcie_rq_tag1=pcie_rq_tag1,
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# pcie_rq_tag_av=pcie_rq_tag_av,
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# pcie_rq_tag_vld0=pcie_rq_tag_vld0,
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# pcie_rq_tag_vld1=pcie_rq_tag_vld1,
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# Requester Completion Interface
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m_axis_rc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
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m_axis_rc_tuser=Signal(intbv(0)[161:]),
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m_axis_rc_tlast=Signal(bool(0)),
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m_axis_rc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
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m_axis_rc_tvalid=Signal(bool(0)),
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m_axis_rc_tready=Signal(bool(0)),
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# Transmit Flow Control Interface
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# pcie_tfc_nph_av=pcie_tfc_nph_av,
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# pcie_tfc_npd_av=pcie_tfc_npd_av,
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# Configuration Flow Control Interface
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cfg_fc_ph=pcie_tx_fc_ph_av,
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cfg_fc_pd=pcie_tx_fc_pd_av,
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#cfg_fc_nph=cfg_fc_nph,
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#cfg_fc_npd=cfg_fc_npd,
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#cfg_fc_cplh=cfg_fc_cplh,
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#cfg_fc_cpld=cfg_fc_cpld,
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cfg_fc_sel=Signal(intbv(0b100)[3:]),
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# Configuration Control Interface
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# cfg_hot_reset_in=cfg_hot_reset_in,
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# cfg_hot_reset_out=cfg_hot_reset_out,
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# cfg_config_space_enable=cfg_config_space_enable,
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# cfg_dsn=cfg_dsn,
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# cfg_ds_port_number=cfg_ds_port_number,
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# cfg_ds_bus_number=cfg_ds_bus_number,
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# cfg_ds_device_number=cfg_ds_device_number,
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# cfg_ds_function_number=cfg_ds_function_number,
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# cfg_power_state_change_ack=cfg_power_state_change_ack,
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# cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
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# cfg_err_cor_in=cfg_err_cor_in,
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# cfg_err_uncor_in=cfg_err_uncor_in,
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# cfg_flr_done=cfg_flr_done,
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# cfg_vf_flr_done=cfg_vf_flr_done,
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# cfg_flr_in_process=cfg_flr_in_process,
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# cfg_vf_flr_in_process=cfg_vf_flr_in_process,
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# cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
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# cfg_link_training_enable=cfg_link_training_enable,
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# Clock and Reset Interface
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user_clk=user_clk,
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user_reset=user_reset,
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#user_lnk_up=user_lnk_up,
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sys_clk=sys_clk,
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sys_clk_gt=sys_clk,
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sys_reset=sys_reset,
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cq_pause=cq_pause,
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cc_pause=cc_pause,
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rq_pause=rq_pause,
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rc_pause=rc_pause
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=user_clk,
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rst=user_reset,
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current_test=current_test,
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s_axis_rq_tdata=s_axis_rq_tdata,
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s_axis_rq_tkeep=s_axis_rq_tkeep,
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s_axis_rq_tvalid=s_axis_rq_tvalid,
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s_axis_rq_tready=s_axis_rq_tready,
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s_axis_rq_tlast=s_axis_rq_tlast,
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s_axis_rq_tuser=s_axis_rq_tuser,
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m_axis_rq_tdata=m_axis_rq_tdata,
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m_axis_rq_tkeep=m_axis_rq_tkeep,
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m_axis_rq_tvalid=m_axis_rq_tvalid,
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m_axis_rq_tready=m_axis_rq_tready,
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m_axis_rq_tlast=m_axis_rq_tlast,
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m_axis_rq_tuser=m_axis_rq_tuser,
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s_axis_rq_seq_num_0=s_axis_rq_seq_num_0,
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s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0,
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s_axis_rq_seq_num_1=s_axis_rq_seq_num_1,
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s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1,
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m_axis_rq_seq_num_0=m_axis_rq_seq_num_0,
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m_axis_rq_seq_num_valid_0=m_axis_rq_seq_num_valid_0,
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m_axis_rq_seq_num_1=m_axis_rq_seq_num_1,
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m_axis_rq_seq_num_valid_1=m_axis_rq_seq_num_valid_1,
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pcie_tx_fc_ph_av=pcie_tx_fc_ph_av,
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pcie_tx_fc_pd_av=pcie_tx_fc_pd_av,
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s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr,
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s_axis_write_desc_ram_sel=s_axis_write_desc_ram_sel,
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s_axis_write_desc_ram_addr=s_axis_write_desc_ram_addr,
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s_axis_write_desc_len=s_axis_write_desc_len,
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s_axis_write_desc_tag=s_axis_write_desc_tag,
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s_axis_write_desc_valid=s_axis_write_desc_valid,
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s_axis_write_desc_ready=s_axis_write_desc_ready,
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m_axis_write_desc_status_tag=m_axis_write_desc_status_tag,
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m_axis_write_desc_status_valid=m_axis_write_desc_status_valid,
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ram_rd_cmd_sel=ram_rd_cmd_sel,
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ram_rd_cmd_addr=ram_rd_cmd_addr,
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ram_rd_cmd_valid=ram_rd_cmd_valid,
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ram_rd_cmd_ready=ram_rd_cmd_ready,
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ram_rd_resp_data=ram_rd_resp_data,
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ram_rd_resp_valid=ram_rd_resp_valid,
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ram_rd_resp_ready=ram_rd_resp_ready,
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enable=enable,
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requester_id=requester_id,
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requester_id_enable=requester_id_enable,
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max_payload_size=max_payload_size
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@always_comb
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def clk_logic():
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sys_clk.next = clk
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sys_reset.next = not rst
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cq_pause_toggle = Signal(bool(0))
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cc_pause_toggle = Signal(bool(0))
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rq_pause_toggle = Signal(bool(0))
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rc_pause_toggle = Signal(bool(0))
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@instance
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def pause_toggle():
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while True:
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if (cq_pause_toggle or cc_pause_toggle or rq_pause_toggle or rc_pause_toggle):
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cq_pause.next = cq_pause_toggle
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cc_pause.next = cc_pause_toggle
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rq_pause.next = rq_pause_toggle
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rc_pause.next = rc_pause_toggle
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yield user_clk.posedge
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yield user_clk.posedge
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yield user_clk.posedge
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cq_pause.next = 0
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cc_pause.next = 0
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rq_pause.next = 0
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rc_pause.next = 0
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yield user_clk.posedge
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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# testbench stimulus
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cur_tag = 1
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max_payload_size.next = 0
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enable.next = 1
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yield user_clk.posedge
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print("test 1: enumeration")
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current_test.next = 1
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yield rc.enumerate(enable_bus_mastering=True)
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yield delay(100)
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yield user_clk.posedge
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print("test 2: PCIe write")
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current_test.next = 2
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pcie_addr = 0x00000000
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ram_addr = 0x00000000
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test_data = b'\x11\x22\x33\x44'
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dma_ram_inst.write_mem(ram_addr, test_data)
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data = dma_ram_inst.read_mem(ram_addr, 32)
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for i in range(0, len(data), 16):
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print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
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write_desc_source.send([(mem_base+pcie_addr, 0, ram_addr, len(test_data), cur_tag)])
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yield write_desc_status_sink.wait(1000)
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yield delay(50)
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status = write_desc_status_sink.recv()
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print(status)
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assert status.data[0][0] == cur_tag
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data = mem_data[pcie_addr:pcie_addr+32]
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for i in range(0, len(data), 16):
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print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
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assert mem_data[pcie_addr:pcie_addr+len(test_data)] == test_data
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cur_tag = (cur_tag + 1) % 256
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|
|
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yield delay(100)
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|
|
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yield user_clk.posedge
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print("test 3: various writes")
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current_test.next = 3
|
|
|
|
for length in list(range(1,67))+list(range(128-4,128+4))+[1024]:
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for pcie_offset in list(range(8,13))+list(range(4096-4,4096+4)):
|
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for ram_offset in list(range(8,137))+list(range(4096-128,4096)):
|
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for pause in [False, True]:
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print("length %d, pcie_offset %d, ram_offset %d"% (length, pcie_offset, ram_offset))
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|
#pcie_addr = length * 0x100000000 + pcie_offset * 0x10000 + offset
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|
pcie_addr = pcie_offset
|
|
ram_addr = ram_offset
|
|
test_data = bytearray([x%256 for x in range(length)])
|
|
|
|
dma_ram_inst.write_mem(ram_addr & 0xffff80, b'\x55'*(len(test_data)+256))
|
|
mem_data[(pcie_addr-1) & 0xffff80:((pcie_addr-1) & 0xffff80)+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
|
|
dma_ram_inst.write_mem(ram_addr, test_data)
|
|
|
|
data = dma_ram_inst.read_mem(ram_addr&0xfffff0, 64)
|
|
for i in range(0, len(data), 16):
|
|
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
|
|
|
|
rq_pause_toggle.next = pause
|
|
|
|
write_desc_source.send([(mem_base+pcie_addr, 0, ram_addr, len(test_data), cur_tag)])
|
|
|
|
yield write_desc_status_sink.wait(4000)
|
|
yield delay(50)
|
|
|
|
rq_pause_toggle.next = 0
|
|
|
|
status = write_desc_status_sink.recv()
|
|
|
|
print(status)
|
|
|
|
assert status.data[0][0] == cur_tag
|
|
|
|
data = mem_data[pcie_addr&0xfffff0:(pcie_addr&0xfffff0)+64]
|
|
for i in range(0, len(data), 16):
|
|
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
|
|
|
|
print(mem_data[pcie_addr-1:pcie_addr+len(test_data)+1])
|
|
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
|
|
|
|
cur_tag = (cur_tag + 1) % 256
|
|
|
|
yield delay(100)
|
|
|
|
raise StopSimulation
|
|
|
|
return instances()
|
|
|
|
def test_bench():
|
|
sim = Simulation(bench())
|
|
sim.run()
|
|
|
|
if __name__ == '__main__':
|
|
print("Running test...")
|
|
test_bench()
|