187 lines
6.1 KiB
Verilog
187 lines
6.1 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for dma_if_pcie_us_wr
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*/
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module test_dma_if_pcie_us_wr_256;
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// Parameters
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parameter AXIS_PCIE_DATA_WIDTH = 256;
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parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
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parameter AXIS_PCIE_RQ_USER_WIDTH = 60;
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parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2;
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parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT;
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parameter SEG_ADDR_WIDTH = 12;
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parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8;
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parameter RAM_SEL_WIDTH = 2;
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parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH);
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parameter PCIE_ADDR_WIDTH = 64;
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parameter LEN_WIDTH = 16;
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parameter TAG_WIDTH = 8;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rq_tdata = 0;
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reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rq_tkeep = 0;
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reg s_axis_rq_tvalid = 0;
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reg s_axis_rq_tlast = 0;
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reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] s_axis_rq_tuser = 0;
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reg m_axis_rq_tready = 0;
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reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0;
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reg [RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel = 0;
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reg [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr = 0;
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reg [LEN_WIDTH-1:0] s_axis_write_desc_len = 0;
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reg [TAG_WIDTH-1:0] s_axis_write_desc_tag = 0;
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reg s_axis_write_desc_valid = 0;
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reg [SEG_COUNT-1:0] ram_rd_cmd_ready = 0;
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] ram_rd_resp_data = 0;
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reg [SEG_COUNT-1:0] ram_rd_resp_valid = 0;
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reg enable = 0;
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reg [15:0] requester_id = 0;
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reg requester_id_enable = 0;
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reg [2:0] max_payload_size = 0;
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// Outputs
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wire s_axis_rq_tready;
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wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata;
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wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep;
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wire m_axis_rq_tvalid;
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wire m_axis_rq_tlast;
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wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser;
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wire s_axis_write_desc_ready;
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wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag;
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wire m_axis_write_desc_status_valid;
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wire [SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_rd_cmd_sel;
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wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr;
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wire [SEG_COUNT-1:0] ram_rd_cmd_valid;
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wire [SEG_COUNT-1:0] ram_rd_resp_ready;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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s_axis_rq_tdata,
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s_axis_rq_tkeep,
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s_axis_rq_tvalid,
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s_axis_rq_tlast,
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s_axis_rq_tuser,
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m_axis_rq_tready,
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s_axis_write_desc_pcie_addr,
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s_axis_write_desc_ram_sel,
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s_axis_write_desc_ram_addr,
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s_axis_write_desc_len,
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s_axis_write_desc_tag,
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s_axis_write_desc_valid,
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ram_rd_cmd_ready,
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ram_rd_resp_data,
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ram_rd_resp_valid,
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enable,
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requester_id,
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requester_id_enable,
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max_payload_size
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);
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$to_myhdl(
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s_axis_rq_tready,
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m_axis_rq_tdata,
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m_axis_rq_tkeep,
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m_axis_rq_tvalid,
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m_axis_rq_tlast,
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m_axis_rq_tuser,
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s_axis_write_desc_ready,
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m_axis_write_desc_status_tag,
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m_axis_write_desc_status_valid,
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ram_rd_cmd_sel,
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ram_rd_cmd_addr,
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ram_rd_cmd_valid,
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ram_rd_resp_ready
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);
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// dump file
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$dumpfile("test_dma_if_pcie_us_wr_256.lxt");
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$dumpvars(0, test_dma_if_pcie_us_wr_256);
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end
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dma_if_pcie_us_wr #(
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.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
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.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
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.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
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.SEG_COUNT(SEG_COUNT),
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.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
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.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
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.SEG_BE_WIDTH(SEG_BE_WIDTH),
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.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
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.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
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.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
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.LEN_WIDTH(LEN_WIDTH),
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.TAG_WIDTH(TAG_WIDTH)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.s_axis_rq_tdata(s_axis_rq_tdata),
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.s_axis_rq_tkeep(s_axis_rq_tkeep),
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.s_axis_rq_tvalid(s_axis_rq_tvalid),
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.s_axis_rq_tready(s_axis_rq_tready),
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.s_axis_rq_tlast(s_axis_rq_tlast),
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.s_axis_rq_tuser(s_axis_rq_tuser),
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.m_axis_rq_tdata(m_axis_rq_tdata),
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.m_axis_rq_tkeep(m_axis_rq_tkeep),
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.m_axis_rq_tvalid(m_axis_rq_tvalid),
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.m_axis_rq_tready(m_axis_rq_tready),
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.m_axis_rq_tlast(m_axis_rq_tlast),
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.m_axis_rq_tuser(m_axis_rq_tuser),
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.s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr),
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.s_axis_write_desc_ram_sel(s_axis_write_desc_ram_sel),
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.s_axis_write_desc_ram_addr(s_axis_write_desc_ram_addr),
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.s_axis_write_desc_len(s_axis_write_desc_len),
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.s_axis_write_desc_tag(s_axis_write_desc_tag),
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.s_axis_write_desc_valid(s_axis_write_desc_valid),
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.s_axis_write_desc_ready(s_axis_write_desc_ready),
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.m_axis_write_desc_status_tag(m_axis_write_desc_status_tag),
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.m_axis_write_desc_status_valid(m_axis_write_desc_status_valid),
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.ram_rd_cmd_sel(ram_rd_cmd_sel),
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.ram_rd_cmd_addr(ram_rd_cmd_addr),
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.ram_rd_cmd_valid(ram_rd_cmd_valid),
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.ram_rd_cmd_ready(ram_rd_cmd_ready),
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.ram_rd_resp_data(ram_rd_resp_data),
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.ram_rd_resp_valid(ram_rd_resp_valid),
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.ram_rd_resp_ready(ram_rd_resp_ready),
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.enable(enable),
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.requester_id(requester_id),
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.requester_id_enable(requester_id_enable),
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.max_payload_size(max_payload_size)
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);
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endmodule
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