443 lines
14 KiB
Python
Executable File
443 lines
14 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import pcie
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import pcie_us
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import axi
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module = 'pcie_us_axi_master_rd'
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testbench = 'test_%s_128' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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AXIS_PCIE_DATA_WIDTH = 128
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AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32)
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AXIS_PCIE_CQ_USER_WIDTH = 85
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AXIS_PCIE_CC_USER_WIDTH = 33
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AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH
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AXI_ADDR_WIDTH = 64
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AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8)
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AXI_ID_WIDTH = 8
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AXI_MAX_BURST_LEN = 256
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
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s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
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s_axis_cq_tvalid = Signal(bool(0))
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s_axis_cq_tlast = Signal(bool(0))
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s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:])
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m_axis_cc_tready = Signal(bool(0))
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m_axi_arready = Signal(bool(0))
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m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:])
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m_axi_rdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
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m_axi_rresp = Signal(intbv(0)[2:])
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m_axi_rlast = Signal(bool(0))
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m_axi_rvalid = Signal(bool(0))
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completer_id = Signal(intbv(0)[16:])
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completer_id_enable = Signal(bool(0))
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max_payload_size = Signal(intbv(0)[3:])
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# Outputs
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s_axis_cq_tready = Signal(bool(0))
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m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
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m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
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m_axis_cc_tvalid = Signal(bool(0))
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m_axis_cc_tlast = Signal(bool(0))
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m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:])
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m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:])
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m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
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m_axi_arlen = Signal(intbv(0)[8:])
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m_axi_arsize = Signal(intbv(4)[3:])
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m_axi_arburst = Signal(intbv(1)[2:])
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m_axi_arlock = Signal(bool(0))
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m_axi_arcache = Signal(intbv(3)[4:])
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m_axi_arprot = Signal(intbv(2)[3:])
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m_axi_arvalid = Signal(bool(0))
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m_axi_rready = Signal(bool(0))
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status_error_cor = Signal(bool(0))
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status_error_uncor = Signal(bool(0))
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# Clock and Reset Interface
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user_clk=Signal(bool(0))
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user_reset=Signal(bool(0))
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sys_clk=Signal(bool(0))
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sys_reset=Signal(bool(0))
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# AXI4 RAM model
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axi_ram_inst = axi.AXIRam(2**16)
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axi_ram_port0 = axi_ram_inst.create_port(
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user_clk,
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s_axi_arid=m_axi_arid,
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s_axi_araddr=m_axi_araddr,
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s_axi_arlen=m_axi_arlen,
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s_axi_arsize=m_axi_arsize,
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s_axi_arburst=m_axi_arburst,
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s_axi_arlock=m_axi_arlock,
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s_axi_arcache=m_axi_arcache,
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s_axi_arprot=m_axi_arprot,
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s_axi_arvalid=m_axi_arvalid,
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s_axi_arready=m_axi_arready,
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s_axi_rid=m_axi_rid,
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s_axi_rdata=m_axi_rdata,
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s_axi_rresp=m_axi_rresp,
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s_axi_rlast=m_axi_rlast,
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s_axi_rvalid=m_axi_rvalid,
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s_axi_rready=m_axi_rready,
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name='port0'
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)
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# PCIe devices
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rc = pcie.RootComplex()
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dev = pcie_us.UltrascalePCIe()
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dev.pcie_generation = 3
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dev.pcie_link_width = 4
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dev.user_clock_frequency = 250e6
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dev.functions[0].configure_bar(0, 16*1024*1024)
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dev.functions[0].configure_bar(1, 32, io=True)
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rc.make_port().connect(dev)
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cq_pause = Signal(bool(0))
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cc_pause = Signal(bool(0))
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rq_pause = Signal(bool(0))
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rc_pause = Signal(bool(0))
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pcie_logic = dev.create_logic(
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# Completer reQuest Interface
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m_axis_cq_tdata=s_axis_cq_tdata,
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m_axis_cq_tuser=s_axis_cq_tuser,
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m_axis_cq_tlast=s_axis_cq_tlast,
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m_axis_cq_tkeep=s_axis_cq_tkeep,
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m_axis_cq_tvalid=s_axis_cq_tvalid,
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m_axis_cq_tready=s_axis_cq_tready,
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#pcie_cq_np_req=pcie_cq_np_req,
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#pcie_cq_np_req_count=pcie_cq_np_req_count,
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# Completer Completion Interface
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s_axis_cc_tdata=m_axis_cc_tdata,
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s_axis_cc_tuser=m_axis_cc_tuser,
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s_axis_cc_tlast=m_axis_cc_tlast,
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s_axis_cc_tkeep=m_axis_cc_tkeep,
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s_axis_cc_tvalid=m_axis_cc_tvalid,
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s_axis_cc_tready=m_axis_cc_tready,
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# Requester reQuest Interface
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s_axis_rq_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
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s_axis_rq_tuser=Signal(intbv(0)[60:]),
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s_axis_rq_tlast=Signal(bool(0)),
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s_axis_rq_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
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s_axis_rq_tvalid=Signal(bool(0)),
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s_axis_rq_tready=Signal(bool(1)),
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# pcie_rq_seq_num=pcie_rq_seq_num,
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# pcie_rq_seq_num_vld=pcie_rq_seq_num_vld,
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# pcie_rq_tag=pcie_rq_tag,
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# pcie_rq_tag_av=pcie_rq_tag_av,
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# pcie_rq_tag_vld=pcie_rq_tag_vld,
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# Requester Completion Interface
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m_axis_rc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
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m_axis_rc_tuser=Signal(intbv(0)[75:]),
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m_axis_rc_tlast=Signal(bool(0)),
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m_axis_rc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
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m_axis_rc_tvalid=Signal(bool(0)),
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m_axis_rc_tready=Signal(bool(0)),
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# Transmit Flow Control Interface
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# pcie_tfc_nph_av=pcie_tfc_nph_av,
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# pcie_tfc_npd_av=pcie_tfc_npd_av,
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# Configuration Control Interface
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# cfg_hot_reset_in=cfg_hot_reset_in,
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# cfg_hot_reset_out=cfg_hot_reset_out,
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# cfg_config_space_enable=cfg_config_space_enable,
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# cfg_per_function_update_done=cfg_per_function_update_done,
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# cfg_per_function_number=cfg_per_function_number,
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# cfg_per_function_output_request=cfg_per_function_output_request,
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# cfg_dsn=cfg_dsn,
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# cfg_ds_bus_number=cfg_ds_bus_number,
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# cfg_ds_device_number=cfg_ds_device_number,
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# cfg_ds_function_number=cfg_ds_function_number,
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# cfg_power_state_change_ack=cfg_power_state_change_ack,
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# cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
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# cfg_err_cor_in=cfg_err_cor_in,
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# cfg_err_uncor_in=cfg_err_uncor_in,
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# cfg_flr_done=cfg_flr_done,
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# cfg_vf_flr_done=cfg_vf_flr_done,
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# cfg_flr_in_process=cfg_flr_in_process,
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# cfg_vf_flr_in_process=cfg_vf_flr_in_process,
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# cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
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# cfg_link_training_enable=cfg_link_training_enable,
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# Clock and Reset Interface
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user_clk=user_clk,
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user_reset=user_reset,
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#user_lnk_up=user_lnk_up,
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sys_clk=sys_clk,
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sys_clk_gt=sys_clk,
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sys_reset=sys_reset,
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cq_pause=cq_pause,
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cc_pause=cc_pause,
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rq_pause=rq_pause,
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rc_pause=rc_pause
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=user_clk,
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rst=user_reset,
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current_test=current_test,
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s_axis_cq_tdata=s_axis_cq_tdata,
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s_axis_cq_tkeep=s_axis_cq_tkeep,
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s_axis_cq_tvalid=s_axis_cq_tvalid,
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s_axis_cq_tready=s_axis_cq_tready,
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s_axis_cq_tlast=s_axis_cq_tlast,
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s_axis_cq_tuser=s_axis_cq_tuser,
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m_axis_cc_tdata=m_axis_cc_tdata,
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m_axis_cc_tkeep=m_axis_cc_tkeep,
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m_axis_cc_tvalid=m_axis_cc_tvalid,
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m_axis_cc_tready=m_axis_cc_tready,
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m_axis_cc_tlast=m_axis_cc_tlast,
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m_axis_cc_tuser=m_axis_cc_tuser,
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m_axi_arid=m_axi_arid,
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m_axi_araddr=m_axi_araddr,
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m_axi_arlen=m_axi_arlen,
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m_axi_arsize=m_axi_arsize,
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m_axi_arburst=m_axi_arburst,
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m_axi_arlock=m_axi_arlock,
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m_axi_arcache=m_axi_arcache,
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m_axi_arprot=m_axi_arprot,
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m_axi_arvalid=m_axi_arvalid,
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m_axi_arready=m_axi_arready,
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m_axi_rid=m_axi_rid,
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m_axi_rdata=m_axi_rdata,
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m_axi_rresp=m_axi_rresp,
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m_axi_rlast=m_axi_rlast,
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m_axi_rvalid=m_axi_rvalid,
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m_axi_rready=m_axi_rready,
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completer_id=completer_id,
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completer_id_enable=completer_id_enable,
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max_payload_size=max_payload_size,
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status_error_cor=status_error_cor,
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status_error_uncor=status_error_uncor
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@always_comb
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def clk_logic():
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sys_clk.next = clk
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sys_reset.next = not rst
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status_error_cor_asserted = Signal(bool(0))
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status_error_uncor_asserted = Signal(bool(0))
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@always(user_clk.posedge)
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def monitor():
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if (status_error_cor):
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status_error_cor_asserted.next = 1
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if (status_error_uncor):
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status_error_uncor_asserted.next = 1
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cq_pause_toggle = Signal(bool(0))
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cc_pause_toggle = Signal(bool(0))
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rq_pause_toggle = Signal(bool(0))
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rc_pause_toggle = Signal(bool(0))
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@instance
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def pause_toggle():
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while True:
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if (cq_pause_toggle or cc_pause_toggle or rq_pause_toggle or rc_pause_toggle):
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cq_pause.next = cq_pause_toggle
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cc_pause.next = cc_pause_toggle
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rq_pause.next = rq_pause_toggle
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rc_pause.next = rc_pause_toggle
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yield user_clk.posedge
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yield user_clk.posedge
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yield user_clk.posedge
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cq_pause.next = 0
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cc_pause.next = 0
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rq_pause.next = 0
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rc_pause.next = 0
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yield user_clk.posedge
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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# testbench stimulus
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max_payload_size.next = 0
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yield user_clk.posedge
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print("test 1: enumeration")
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current_test.next = 1
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yield rc.enumerate()
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dev_bar0 = rc.tree[0][0].bar[0]
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dev_bar1 = rc.tree[0][0].bar[1]
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yield delay(100)
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yield clk.posedge
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print("test 2: memory read")
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current_test.next = 2
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pcie_addr = 0x00000000
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test_data = b'\x11\x22\x33\x44'
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axi_ram_inst.write_mem(pcie_addr, test_data)
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data = axi_ram_inst.read_mem(0, 32)
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for i in range(0, len(data), 16):
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print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
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val = yield from rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000)
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print(val)
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assert val == test_data
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assert not status_error_cor_asserted
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assert not status_error_uncor_asserted
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yield delay(100)
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yield user_clk.posedge
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print("test 3: various reads")
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current_test.next = 3
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for length in list(range(1,34))+[1024]:
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for pcie_offset in list(range(8,25))+list(range(4096-16,4096)):
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for pause in [False, True]:
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print("length %d, pcie_offset %d"% (length, pcie_offset))
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#pcie_addr = length * 0x100000000 + pcie_offset * 0x10000 + offset
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pcie_addr = pcie_offset
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test_data = bytearray([x%256 for x in range(length)])
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axi_ram_inst.write_mem(pcie_addr & 0xffff80, b'\x55'*(len(test_data)+256))
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axi_ram_inst.write_mem(pcie_addr, test_data)
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data = axi_ram_inst.read_mem(pcie_addr&0xfffff0, 64)
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for i in range(0, len(data), 16):
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print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
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cq_pause_toggle.next = pause
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cc_pause_toggle.next = pause
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val = yield from rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000)
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cq_pause_toggle.next = 0
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cc_pause_toggle.next = 0
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print(val)
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assert val == test_data
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assert not status_error_cor_asserted
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assert not status_error_uncor_asserted
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yield delay(100)
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yield clk.posedge
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print("test 4: bad requests")
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current_test.next = 4
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yield from rc.mem_write(dev_bar0, b'\x11\x22\x33\x44')
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yield delay(100)
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assert not status_error_cor_asserted
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assert status_error_uncor_asserted
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status_error_cor_asserted.next = False
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status_error_uncor_asserted.next = False
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try:
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yield from rc.io_write(dev_bar1, b'\x11\x22\x33\x44')
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except:
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print("Caught unsuccessful completion exception")
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pass
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else:
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assert False
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assert status_error_cor_asserted
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assert not status_error_uncor_asserted
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status_error_cor_asserted.next = False
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status_error_uncor_asserted.next = False
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yield delay(100)
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raise StopSimulation
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return instances()
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def test_bench():
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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