161 lines
4.4 KiB
Verilog
161 lines
4.4 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for pcie_us_axi_master_wr
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*/
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module test_pcie_us_axi_master_wr_64;
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// Parameters
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parameter AXIS_PCIE_DATA_WIDTH = 64;
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parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
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parameter AXIS_PCIE_CQ_USER_WIDTH = 85;
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parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
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parameter AXI_ADDR_WIDTH = 64;
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parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
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parameter AXI_ID_WIDTH = 8;
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parameter AXI_MAX_BURST_LEN = 256;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0;
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reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0;
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reg s_axis_cq_tvalid = 0;
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reg s_axis_cq_tlast = 0;
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reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0;
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reg m_axi_awready = 0;
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reg m_axi_wready = 0;
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reg [AXI_ID_WIDTH-1:0] m_axi_bid = 0;
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reg [1:0] m_axi_bresp = 0;
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reg m_axi_bvalid = 0;
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// Outputs
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wire s_axis_cq_tready;
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wire [AXI_ID_WIDTH-1:0] m_axi_awid;
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wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr;
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wire [7:0] m_axi_awlen;
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wire [2:0] m_axi_awsize;
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wire [1:0] m_axi_awburst;
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wire m_axi_awlock;
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wire [3:0] m_axi_awcache;
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wire [2:0] m_axi_awprot;
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wire m_axi_awvalid;
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wire [AXI_DATA_WIDTH-1:0] m_axi_wdata;
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wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb;
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wire m_axi_wlast;
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wire m_axi_wvalid;
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wire m_axi_bready;
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wire status_error_uncor;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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s_axis_cq_tdata,
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s_axis_cq_tkeep,
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s_axis_cq_tvalid,
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s_axis_cq_tlast,
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s_axis_cq_tuser,
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m_axi_awready,
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m_axi_wready,
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m_axi_bid,
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m_axi_bresp,
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m_axi_bvalid
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);
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$to_myhdl(
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s_axis_cq_tready,
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m_axi_awid,
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m_axi_awaddr,
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m_axi_awlen,
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m_axi_awsize,
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m_axi_awburst,
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m_axi_awlock,
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m_axi_awcache,
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m_axi_awprot,
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m_axi_awvalid,
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m_axi_wdata,
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m_axi_wstrb,
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m_axi_wlast,
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m_axi_wvalid,
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m_axi_bready,
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status_error_uncor
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);
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// dump file
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$dumpfile("test_pcie_us_axi_master_wr_64.lxt");
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$dumpvars(0, test_pcie_us_axi_master_wr_64);
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end
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pcie_us_axi_master_wr #(
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.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
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.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
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.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
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.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
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.AXI_ID_WIDTH(AXI_ID_WIDTH),
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.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.s_axis_cq_tdata(s_axis_cq_tdata),
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.s_axis_cq_tkeep(s_axis_cq_tkeep),
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.s_axis_cq_tvalid(s_axis_cq_tvalid),
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.s_axis_cq_tready(s_axis_cq_tready),
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.s_axis_cq_tlast(s_axis_cq_tlast),
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.s_axis_cq_tuser(s_axis_cq_tuser),
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.m_axi_awid(m_axi_awid),
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.m_axi_awaddr(m_axi_awaddr),
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.m_axi_awlen(m_axi_awlen),
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.m_axi_awsize(m_axi_awsize),
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.m_axi_awburst(m_axi_awburst),
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.m_axi_awlock(m_axi_awlock),
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.m_axi_awcache(m_axi_awcache),
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.m_axi_awprot(m_axi_awprot),
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.m_axi_awvalid(m_axi_awvalid),
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.m_axi_awready(m_axi_awready),
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.m_axi_wdata(m_axi_wdata),
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.m_axi_wstrb(m_axi_wstrb),
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.m_axi_wlast(m_axi_wlast),
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.m_axi_wvalid(m_axi_wvalid),
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.m_axi_wready(m_axi_wready),
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.m_axi_bid(m_axi_bid),
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.m_axi_bresp(m_axi_bresp),
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.m_axi_bvalid(m_axi_bvalid),
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.m_axi_bready(m_axi_bready),
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.status_error_uncor(status_error_uncor)
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);
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endmodule
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