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Change CONFIG_* parameter to CFG_*

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Shortens the parameter name without reducing the readability.
This commit is contained in:
Berin Martini 2018-06-03 14:49:01 -07:00
parent 1de6b65223
commit 05e0b292f2
12 changed files with 144 additions and 144 deletions
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36
hdl/axis/axis.v
View File

@ -21,12 +21,12 @@ module axis #(
parameter
BUF_AWIDTH = 9,
CONFIG_ID_WR = 1,
CONFIG_ID_RD = 2,
CONFIG_ADDR = 23,
CONFIG_DATA = 24,
CONFIG_AWIDTH = 5,
CONFIG_DWIDTH = 32,
CFG_ID_WR = 1,
CFG_ID_RD = 2,
CFG_ADDR = 23,
CFG_DATA = 24,
CFG_AWIDTH = 5,
CFG_DWIDTH = 32,
STREAM_WIDTH = 32,
@ -38,8 +38,8 @@ module axis #(
input rst,
// configuation
input [CONFIG_AWIDTH-1:0] cfg_addr,
input [CONFIG_DWIDTH-1:0] cfg_data,
input [CFG_AWIDTH-1:0] cfg_addr,
input [CFG_DWIDTH-1:0] cfg_data,
input cfg_valid,
// stream interface
@ -148,11 +148,11 @@ module axis #(
axis_write #(
.BUF_AWIDTH (BUF_AWIDTH),
.CONFIG_ID (CONFIG_ID_WR),
.CONFIG_ADDR (CONFIG_ADDR),
.CONFIG_DATA (CONFIG_DATA),
.CONFIG_AWIDTH (CONFIG_AWIDTH),
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_ID (CFG_ID_WR),
.CFG_ADDR (CFG_ADDR),
.CFG_DATA (CFG_DATA),
.CFG_AWIDTH (CFG_AWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
@ -185,11 +185,11 @@ module axis #(
axis_read #(
.BUF_AWIDTH (BUF_AWIDTH),
.CONFIG_ID (CONFIG_ID_RD),
.CONFIG_ADDR (CONFIG_ADDR),
.CONFIG_DATA (CONFIG_DATA),
.CONFIG_AWIDTH (CONFIG_AWIDTH),
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_ID (CFG_ID_RD),
.CFG_ADDR (CFG_ADDR),
.CFG_DATA (CFG_DATA),
.CFG_AWIDTH (CFG_AWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),

12
hdl/axis/axis_addr.v
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@ -19,7 +19,7 @@
module axis_addr
#(parameter
CONFIG_DWIDTH = 32,
CFG_DWIDTH = 32,
WIDTH_RATIO = 16,
CONVERT_SHIFT = 3,
AXI_LEN_WIDTH = 8,
@ -28,8 +28,8 @@ module axis_addr
(input clk,
input rst,
input [CONFIG_DWIDTH-1:0] cfg_address,
input [CONFIG_DWIDTH-1:0] cfg_length,
input [CFG_DWIDTH-1:0] cfg_address,
input [CFG_DWIDTH-1:0] cfg_length,
input cfg_valid,
output cfg_ready,
@ -43,7 +43,7 @@ module axis_addr
* Local parameters
*/
localparam BURST_NB_WIDTH = CONFIG_DWIDTH-AXI_LEN_WIDTH;
localparam BURST_NB_WIDTH = CFG_DWIDTH-AXI_LEN_WIDTH;
localparam BURST_LENGTH = 1<<AXI_LEN_WIDTH;
localparam
@ -76,11 +76,11 @@ module axis_addr
reg [BURST_NB_WIDTH-1:0] burst_cnt;
wire burst_done;
reg [CONFIG_DWIDTH-1:0] cfg_length_r;
reg [CFG_DWIDTH-1:0] cfg_length_r;
reg cfg_valid_r;
reg cfg_done;
reg [CONFIG_DWIDTH-1:0] axi_address;
reg [CFG_DWIDTH-1:0] axi_address;
/**

8
hdl/axis/axis_addr_tb.v
View File

@ -50,7 +50,7 @@ module axis_addr_tb;
* Local parameters
*/
localparam CONFIG_DWIDTH = 32;
localparam CFG_DWIDTH = 32;
localparam WIDTH_RATIO = 16;
localparam AXI_LEN_WIDTH = 8;
localparam AXI_ADDR_WIDTH = 32;
@ -67,8 +67,8 @@ module axis_addr_tb;
reg rst;
reg [CONFIG_DWIDTH-1:0] cfg_address;
reg [CONFIG_DWIDTH-1:0] cfg_length;
reg [CFG_DWIDTH-1:0] cfg_address;
reg [CFG_DWIDTH-1:0] cfg_length;
reg cfg_valid;
wire cfg_ready;
@ -83,7 +83,7 @@ module axis_addr_tb;
*/
axis_addr #(
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.WIDTH_RATIO (WIDTH_RATIO),
.CONVERT_SHIFT ($clog2(WIDTH_RATIO)),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),

48
hdl/axis/axis_read.v
View File

@ -25,11 +25,11 @@ module axis_read
#(parameter
BUF_AWIDTH = 9,
CONFIG_ID = 1,
CONFIG_ADDR = 23,
CONFIG_DATA = 24,
CONFIG_AWIDTH = 5,
CONFIG_DWIDTH = 32,
CFG_ID = 1,
CFG_ADDR = 23,
CFG_DATA = 24,
CFG_AWIDTH = 5,
CFG_DWIDTH = 32,
AXI_LEN_WIDTH = 8,
AXI_ADDR_WIDTH = 32,
@ -38,8 +38,8 @@ module axis_read
(input clk,
input rst,
input [CONFIG_AWIDTH-1:0] cfg_addr,
input [CONFIG_DWIDTH-1:0] cfg_data,
input [CFG_AWIDTH-1:0] cfg_addr,
input [CFG_DWIDTH-1:0] cfg_data,
input cfg_valid,
input axi_arready,
@ -61,8 +61,8 @@ module axis_read
*/
localparam WIDTH_RATIO = AXI_DATA_WIDTH/DATA_WIDTH;
localparam CONFIG_NB = 2;
localparam STORE_WIDTH = CONFIG_DWIDTH*CONFIG_NB;
localparam CFG_NB = 2;
localparam STORE_WIDTH = CFG_DWIDTH*CFG_NB;
localparam
C_IDLE = 0,
@ -87,17 +87,17 @@ module axis_read
wire cfg_addr_ready;
wire cfg_data_ready;
reg [CONFIG_AWIDTH-1:0] cfg_addr_r;
reg [CONFIG_DWIDTH-1:0] cfg_data_r;
reg [CFG_AWIDTH-1:0] cfg_addr_r;
reg [CFG_DWIDTH-1:0] cfg_data_r;
reg cfg_valid_r;
wire [STORE_WIDTH+CONFIG_DWIDTH-1:0] cfg_store_i;
wire [STORE_WIDTH+CFG_DWIDTH-1:0] cfg_store_i;
reg [STORE_WIDTH-1:0] cfg_store;
reg [7:0] cfg_cnt;
wire [CONFIG_DWIDTH-1:0] start_addr;
reg [CONFIG_DWIDTH-1:0] cfg_address;
wire [CONFIG_DWIDTH-1:0] str_length;
reg [CONFIG_DWIDTH-1:0] cfg_length;
wire [CFG_DWIDTH-1:0] start_addr;
reg [CFG_DWIDTH-1:0] cfg_address;
wire [CFG_DWIDTH-1:0] str_length;
reg [CFG_DWIDTH-1:0] cfg_length;
reg cfg_enable;
wire id_valid;
wire addressed;
@ -110,15 +110,15 @@ module axis_read
assign cfg_store_i = {cfg_store, cfg_data_r};
assign start_addr = cfg_store[CONFIG_DWIDTH +: CONFIG_DWIDTH];
assign start_addr = cfg_store[CFG_DWIDTH +: CFG_DWIDTH];
assign str_length = cfg_store[0 +: CONFIG_DWIDTH];
assign str_length = cfg_store[0 +: CFG_DWIDTH];
assign id_valid = (CONFIG_ID == cfg_data_r);
assign id_valid = (CFG_ID == cfg_data_r);
assign addressed = (CONFIG_ADDR == cfg_addr_r) & cfg_valid_r;
assign addressed = (CFG_ADDR == cfg_addr_r) & cfg_valid_r;
assign axis_data = (CONFIG_DATA == cfg_addr_r) & cfg_valid_r;
assign axis_data = (CFG_DATA == cfg_addr_r) & cfg_valid_r;
// register for improved timing
@ -181,7 +181,7 @@ module axis_read
else c_state_nx[C_IDLE] = 1'b1;
end
c_state[C_CONFIG] : begin
if (axis_data & ((CONFIG_NB-1) <= cfg_cnt)) begin
if (axis_data & ((CFG_NB-1) <= cfg_cnt)) begin
c_state_nx[C_WAIT] = 1'b1;
end
else c_state_nx[C_CONFIG] = 1'b1;
@ -203,7 +203,7 @@ module axis_read
axis_addr #(
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.WIDTH_RATIO (WIDTH_RATIO),
.CONVERT_SHIFT ($clog2(WIDTH_RATIO)),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),
@ -227,7 +227,7 @@ module axis_read
axis_read_data #(
.BUF_AWIDTH (BUF_AWIDTH),
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.WIDTH_RATIO (WIDTH_RATIO),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.DATA_WIDTH (DATA_WIDTH))

8
hdl/axis/axis_read_data.v
View File

@ -23,7 +23,7 @@
module axis_read_data
#(parameter
BUF_AWIDTH = 9,
CONFIG_DWIDTH = 32,
CFG_DWIDTH = 32,
WIDTH_RATIO = 2,
AXI_DATA_WIDTH = 64,
@ -31,7 +31,7 @@ module axis_read_data
(input clk,
input rst,
input [CONFIG_DWIDTH-1:0] cfg_length,
input [CFG_DWIDTH-1:0] cfg_length,
input cfg_valid,
output cfg_ready,
@ -67,8 +67,8 @@ module axis_read_data
reg [3:0] state;
reg [3:0] state_nx;
reg [CONFIG_DWIDTH-1:0] str_cnt;
reg [CONFIG_DWIDTH-1:0] str_length;
reg [CFG_DWIDTH-1:0] str_cnt;
reg [CFG_DWIDTH-1:0] str_length;
wire buf_pop;
wire buf_full;

6
hdl/axis/axis_read_data_tb.v
View File

@ -53,7 +53,7 @@ module axis_read_data_tb;
localparam STREAM_LENGTH = (256*8*2)-4;
localparam BUF_AWIDTH = 4;
localparam CONFIG_DWIDTH = 32;
localparam CFG_DWIDTH = 32;
localparam WIDTH_RATIO = 8;
localparam AXI_DATA_WIDTH = 256;
localparam DATA_WIDTH = 32;
@ -70,7 +70,7 @@ module axis_read_data_tb;
reg rst;
reg [CONFIG_DWIDTH-1:0] cfg_length;
reg [CFG_DWIDTH-1:0] cfg_length;
reg cfg_valid;
wire cfg_ready;
@ -89,7 +89,7 @@ module axis_read_data_tb;
axis_read_data #(
.BUF_AWIDTH (BUF_AWIDTH),
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.WIDTH_RATIO (WIDTH_RATIO),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),

48
hdl/axis/axis_read_tb.v
View File

@ -54,11 +54,11 @@ module axis_read_tb;
localparam BUF_AWIDTH = 4;
localparam CONFIG_ID = 1;
localparam CONFIG_ADDR = 23;
localparam CONFIG_DATA = 24;
localparam CONFIG_AWIDTH = 5;
localparam CONFIG_DWIDTH = 32;
localparam CFG_ID = 1;
localparam CFG_ADDR = 23;
localparam CFG_DATA = 24;
localparam CFG_AWIDTH = 5;
localparam CFG_DWIDTH = 32;
localparam AXI_ADDR_WIDTH = 32;
localparam AXI_DATA_WIDTH = 256;
@ -76,8 +76,8 @@ module axis_read_tb;
reg rst;
reg [CONFIG_AWIDTH-1:0] cfg_addr;
reg [CONFIG_DWIDTH-1:0] cfg_data;
reg [CFG_AWIDTH-1:0] cfg_addr;
reg [CFG_DWIDTH-1:0] cfg_data;
reg cfg_valid;
reg axi_arready;
@ -101,11 +101,11 @@ module axis_read_tb;
axis_read #(
.BUF_AWIDTH (BUF_AWIDTH),
.CONFIG_ID (CONFIG_ID),
.CONFIG_ADDR (CONFIG_ADDR),
.CONFIG_DATA (CONFIG_DATA),
.CONFIG_AWIDTH (CONFIG_AWIDTH),
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_ID (CFG_ID),
.CFG_ADDR (CFG_ADDR),
.CFG_DATA (CFG_DATA),
.CFG_AWIDTH (CFG_AWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
@ -235,8 +235,8 @@ module axis_read_tb;
`endif
repeat(5) @(negedge clk);
cfg_addr <= CONFIG_ADDR;
cfg_data <= CONFIG_ID;
cfg_addr <= CFG_ADDR;
cfg_data <= CFG_ID;
cfg_valid <= 1'b1;
@(negedge clk)
@ -246,7 +246,7 @@ module axis_read_tb;
repeat(5) @(negedge clk);
// memory address
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= 4;
cfg_valid <= 1'b1;
@(negedge clk)
@ -257,7 +257,7 @@ module axis_read_tb;
repeat(5) @(negedge clk);
// length of flow stream
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= 8;
cfg_valid <= 1'b1;
@(negedge clk)
@ -302,17 +302,17 @@ module axis_read_tb;
`endif
repeat(5) @(negedge clk);
cfg_addr <= CONFIG_ADDR;
cfg_data <= CONFIG_ID;
cfg_addr <= CFG_ADDR;
cfg_data <= CFG_ID;
cfg_valid <= 1'b1;
@(negedge clk)
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= 4;
cfg_valid <= 1'b1;
@(negedge clk)
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= 20;
cfg_valid <= 1'b1;
@(negedge clk)
@ -370,17 +370,17 @@ module axis_read_tb;
`endif
repeat(5) @(negedge clk);
cfg_addr <= CONFIG_ADDR;
cfg_data <= CONFIG_ID;
cfg_addr <= CFG_ADDR;
cfg_data <= CFG_ID;
cfg_valid <= 1'b1;
@(negedge clk)
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= 255;
cfg_valid <= 1'b1;
@(negedge clk)
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= STREAM_LENGTH;
cfg_valid <= 1'b1;
@(negedge clk)

48
hdl/axis/axis_write.v
View File

@ -25,11 +25,11 @@ module axis_write
#(parameter
BUF_AWIDTH = 9,
CONFIG_ID = 1,
CONFIG_ADDR = 23,
CONFIG_DATA = 24,
CONFIG_AWIDTH = 5,
CONFIG_DWIDTH = 32,
CFG_ID = 1,
CFG_ADDR = 23,
CFG_DATA = 24,
CFG_AWIDTH = 5,
CFG_DWIDTH = 32,
AXI_LEN_WIDTH = 8,
AXI_ADDR_WIDTH = 32,
@ -38,8 +38,8 @@ module axis_write
(input clk,
input rst,
input [CONFIG_AWIDTH-1:0] cfg_addr,
input [CONFIG_DWIDTH-1:0] cfg_data,
input [CFG_AWIDTH-1:0] cfg_addr,
input [CFG_DWIDTH-1:0] cfg_data,
input cfg_valid,
input axi_awready,
@ -62,8 +62,8 @@ module axis_write
*/
localparam WIDTH_RATIO = AXI_DATA_WIDTH/DATA_WIDTH;
localparam CONFIG_NB = 2;
localparam STORE_WIDTH = CONFIG_DWIDTH*CONFIG_NB;
localparam CFG_NB = 2;
localparam STORE_WIDTH = CFG_DWIDTH*CFG_NB;
localparam
C_IDLE = 0,
@ -88,17 +88,17 @@ module axis_write
wire cfg_addr_ready;
wire cfg_data_ready;
reg [CONFIG_AWIDTH-1:0] cfg_addr_r;
reg [CONFIG_DWIDTH-1:0] cfg_data_r;
reg [CFG_AWIDTH-1:0] cfg_addr_r;
reg [CFG_DWIDTH-1:0] cfg_data_r;
reg cfg_valid_r;
wire [STORE_WIDTH+CONFIG_DWIDTH-1:0] cfg_store_i;
wire [STORE_WIDTH+CFG_DWIDTH-1:0] cfg_store_i;
reg [STORE_WIDTH-1:0] cfg_store;
reg [7:0] cfg_cnt;
wire [CONFIG_DWIDTH-1:0] start_addr;
reg [CONFIG_DWIDTH-1:0] cfg_address;
wire [CONFIG_DWIDTH-1:0] str_length;
reg [CONFIG_DWIDTH-1:0] cfg_length;
wire [CFG_DWIDTH-1:0] start_addr;
reg [CFG_DWIDTH-1:0] cfg_address;
wire [CFG_DWIDTH-1:0] str_length;
reg [CFG_DWIDTH-1:0] cfg_length;
reg cfg_enable;
wire id_valid;
wire addressed;
@ -111,15 +111,15 @@ module axis_write
assign cfg_store_i = {cfg_store, cfg_data_r};
assign start_addr = cfg_store[CONFIG_DWIDTH +: CONFIG_DWIDTH];
assign start_addr = cfg_store[CFG_DWIDTH +: CFG_DWIDTH];
assign str_length = cfg_store[0 +: CONFIG_DWIDTH];
assign str_length = cfg_store[0 +: CFG_DWIDTH];
assign id_valid = (CONFIG_ID == cfg_data_r);
assign id_valid = (CFG_ID == cfg_data_r);
assign addressed = (CONFIG_ADDR == cfg_addr_r) & cfg_valid_r;
assign addressed = (CFG_ADDR == cfg_addr_r) & cfg_valid_r;
assign axis_data = (CONFIG_DATA == cfg_addr_r) & cfg_valid_r;
assign axis_data = (CFG_DATA == cfg_addr_r) & cfg_valid_r;
// register for improved timing
@ -182,7 +182,7 @@ module axis_write
else c_state_nx[C_IDLE] = 1'b1;
end
c_state[C_CONFIG] : begin
if (axis_data & ((CONFIG_NB-1) <= cfg_cnt)) begin
if (axis_data & ((CFG_NB-1) <= cfg_cnt)) begin
c_state_nx[C_WAIT] = 1'b1;
end
else c_state_nx[C_CONFIG] = 1'b1;
@ -204,7 +204,7 @@ module axis_write
axis_addr #(
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.WIDTH_RATIO (WIDTH_RATIO),
.CONVERT_SHIFT ($clog2(WIDTH_RATIO)),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),
@ -228,7 +228,7 @@ module axis_write
axis_write_data #(
.BUF_AWIDTH (BUF_AWIDTH),
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.WIDTH_RATIO (WIDTH_RATIO),
.CONVERT_SHIFT ($clog2(WIDTH_RATIO)),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),

8
hdl/axis/axis_write_data.v
View File

@ -23,7 +23,7 @@
module axis_write_data
#(parameter
BUF_AWIDTH = 9,
CONFIG_DWIDTH = 32,
CFG_DWIDTH = 32,
WIDTH_RATIO = 2,
CONVERT_SHIFT = 3,
@ -33,7 +33,7 @@ module axis_write_data
(input clk,
input rst,
input [CONFIG_DWIDTH-1:0] cfg_length,
input [CFG_DWIDTH-1:0] cfg_length,
input cfg_valid,
output cfg_ready,
@ -73,8 +73,8 @@ module axis_write_data
reg [3:0] state;
reg [3:0] state_nx;
reg [CONFIG_DWIDTH-1:0] str_cnt;
reg [CONFIG_DWIDTH-1:0] str_length;
reg [CFG_DWIDTH-1:0] str_cnt;
reg [CFG_DWIDTH-1:0] str_length;
wire [BUF_AWIDTH:0] buf_count;
wire buf_pop;

6
hdl/axis/axis_write_data_tb.v
View File

@ -53,7 +53,7 @@ module axis_write_data_tb;
localparam STREAM_LENGTH = (256*8*2)-4;
localparam BUF_AWIDTH = 4;
localparam CONFIG_DWIDTH = 32;
localparam CFG_DWIDTH = 32;
localparam AXI_LEN_WIDTH = 4;
localparam AXI_DATA_WIDTH = 64;
@ -75,7 +75,7 @@ module axis_write_data_tb;
wire done;
reg [CONFIG_DWIDTH-1:0] cfg_length;
reg [CFG_DWIDTH-1:0] cfg_length;
reg cfg_valid;
wire cfg_ready;
@ -95,7 +95,7 @@ module axis_write_data_tb;
axis_write_data #(
.BUF_AWIDTH (BUF_AWIDTH),
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.WIDTH_RATIO (WIDTH_RATIO),
.CONVERT_SHIFT ($clog2(WIDTH_RATIO)),

48
hdl/axis/axis_write_tb.v
View File

@ -54,11 +54,11 @@ module axis_write_tb;
localparam BUF_AWIDTH = 4;
localparam CONFIG_ID = 1;
localparam CONFIG_ADDR = 23;
localparam CONFIG_DATA = 24;
localparam CONFIG_AWIDTH = 5;
localparam CONFIG_DWIDTH = 32;
localparam CFG_ID = 1;
localparam CFG_ADDR = 23;
localparam CFG_DATA = 24;
localparam CFG_AWIDTH = 5;
localparam CFG_DWIDTH = 32;
localparam AXI_LEN_WIDTH = 2;
localparam AXI_ADDR_WIDTH = 32;
@ -77,8 +77,8 @@ module axis_write_tb;
reg rst;
reg [CONFIG_AWIDTH-1:0] cfg_addr;
reg [CONFIG_DWIDTH-1:0] cfg_data;
reg [CFG_AWIDTH-1:0] cfg_addr;
reg [CFG_DWIDTH-1:0] cfg_data;
reg cfg_valid;
reg axi_awready;
@ -103,11 +103,11 @@ module axis_write_tb;
axis_write #(
.BUF_AWIDTH (BUF_AWIDTH),
.CONFIG_ID (CONFIG_ID),
.CONFIG_ADDR (CONFIG_ADDR),
.CONFIG_DATA (CONFIG_DATA),
.CONFIG_AWIDTH (CONFIG_AWIDTH),
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.CFG_ID (CFG_ID),
.CFG_ADDR (CFG_ADDR),
.CFG_DATA (CFG_DATA),
.CFG_AWIDTH (CFG_AWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
@ -240,8 +240,8 @@ module axis_write_tb;
`endif
repeat(5) @(negedge clk);
cfg_addr <= CONFIG_ADDR;
cfg_data <= CONFIG_ID;
cfg_addr <= CFG_ADDR;
cfg_data <= CFG_ID;
cfg_valid <= 1'b1;
@(negedge clk)
@ -250,7 +250,7 @@ module axis_write_tb;
cfg_valid <= 1'b0;
repeat(5) @(negedge clk);
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= 4;
cfg_valid <= 1'b1;
@(negedge clk)
@ -260,7 +260,7 @@ module axis_write_tb;
cfg_valid <= 1'b0;
repeat(5) @(negedge clk);
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= 8;
cfg_valid <= 1'b1;
@(negedge clk)
@ -320,17 +320,17 @@ module axis_write_tb;
`endif
repeat(5) @(negedge clk);
cfg_addr <= CONFIG_ADDR;
cfg_data <= CONFIG_ID;
cfg_addr <= CFG_ADDR;
cfg_data <= CFG_ID;
cfg_valid <= 1'b1;
@(negedge clk)
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= 4;
cfg_valid <= 1'b1;
@(negedge clk)
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= 8;
cfg_valid <= 1'b1;
@(negedge clk)
@ -375,17 +375,17 @@ module axis_write_tb;
`endif
repeat(5) @(negedge clk);
cfg_addr <= CONFIG_ADDR;
cfg_data <= CONFIG_ID;
cfg_addr <= CFG_ADDR;
cfg_data <= CFG_ID;
cfg_valid <= 1'b1;
@(negedge clk)
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= 255;
cfg_valid <= 1'b1;
@(negedge clk)
cfg_addr <= CONFIG_DATA;
cfg_addr <= CFG_DATA;
cfg_data <= STREAM_LENGTH;
cfg_valid <= 1'b1;
@(negedge clk)

12
hdl/top/axis_loopback.v
View File

@ -210,12 +210,12 @@ module axis_loopback #(
axis #(
.BUF_AWIDTH (9),
.CONFIG_ID_RD (1),
.CONFIG_ID_WR (2),
.CONFIG_ADDR (CFG_AXIS_ADDR),
.CONFIG_DATA (CFG_AXIS_DATA),
.CONFIG_AWIDTH (CFG_AWIDTH),
.CONFIG_DWIDTH (CFG_DWIDTH),
.CFG_ID_RD (1),
.CFG_ID_WR (2),
.CFG_ADDR (CFG_AXIS_ADDR),
.CFG_DATA (CFG_AXIS_DATA),
.CFG_AWIDTH (CFG_AWIDTH),
.CFG_DWIDTH (CFG_DWIDTH),
.STREAM_WIDTH (SYS_DWIDTH),
.AXI_ID_WIDTH (C_M00_AXI_ID_WIDTH),
.AXI_LEN_WIDTH (C_M00_AXI_BURST_LEN),