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Ensure correct width during bus assignment

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This commit is contained in:
Berin Martini 2016-05-30 20:08:39 -07:00
parent aae41b52d1
commit 0c3c7599fb
1 changed files with 6 additions and 2 deletions
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8
hdl/axis/axis_read.v
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@ -62,6 +62,7 @@ module axis_read
localparam WIDTH_RATIO = AXI_DATA_WIDTH/DATA_WIDTH;
localparam CONFIG_NB = 2;
localparam STORE_WIDTH = CONFIG_DWIDTH*CONFIG_NB;
localparam
C_IDLE = 0,
@ -89,7 +90,8 @@ module axis_read
reg [CONFIG_AWIDTH-1:0] cfg_addr_r;
reg [CONFIG_DWIDTH-1:0] cfg_data_r;
reg cfg_valid_r;
reg [CONFIG_DWIDTH*CONFIG_NB-1:0] cfg_store;
wire [STORE_WIDTH+CONFIG_DWIDTH-1:0] cfg_store_i;
reg [STORE_WIDTH-1:0] cfg_store;
reg [7:0] cfg_cnt;
wire [CONFIG_DWIDTH-1:0] start_addr;
@ -106,6 +108,8 @@ module axis_read
* Implementation
*/
assign cfg_store_i = {cfg_store, cfg_data_r};
assign start_addr = cfg_store[CONFIG_DWIDTH +: CONFIG_DWIDTH];
assign str_length = cfg_store[0 +: CONFIG_DWIDTH];
@ -132,7 +136,7 @@ module axis_read
always @(posedge clk)
if (c_state[C_CONFIG] & axis_data) begin
cfg_store <= {cfg_store, cfg_data_r};
cfg_store <= cfg_store_i[0 +: STORE_WIDTH];
end