mirror of
https://github.com/bmartini/zynq-axis.git
synced 2024-09-05 19:19:27 +08:00
Add testbench for axis_loopback topfile
Doesn't do anything except to test for any warnings/errors etc. in the full system.
This commit is contained in:
parent
65a3a448fd
commit
1de6b65223
132
hdl/top/axis_loopback_tb.v
Normal file
132
hdl/top/axis_loopback_tb.v
Normal file
@ -0,0 +1,132 @@
|
||||
/**
|
||||
* Testbench:
|
||||
* axis_loopback
|
||||
*
|
||||
* Created:
|
||||
* Sun Jun 3 14:42:30 PDT 2018
|
||||
*
|
||||
* Author:
|
||||
* Berin Martini (berin.martini@gmail.com)
|
||||
*/
|
||||
|
||||
`timescale 1ns/10ps
|
||||
|
||||
`define TB_VERBOSE
|
||||
//`define VERBOSE
|
||||
|
||||
|
||||
`include "axis_loopback.v"
|
||||
|
||||
module axis_loopback_tb;
|
||||
|
||||
/**
|
||||
* Clock and control functions
|
||||
*/
|
||||
|
||||
// Generate a clk
|
||||
reg clk;
|
||||
always #1 clk = !clk;
|
||||
|
||||
// End of simulation event definition
|
||||
event end_trigger;
|
||||
always @(end_trigger) $finish;
|
||||
|
||||
`ifdef TB_VERBOSE
|
||||
// Display header information
|
||||
initial #1 display_header();
|
||||
always @(end_trigger) display_header();
|
||||
|
||||
// And strobe signals at each clk
|
||||
always @(posedge clk) display_signals();
|
||||
`endif
|
||||
|
||||
// initial begin
|
||||
// $dumpfile("result.vcd"); // Waveform file
|
||||
// $dumpvars;
|
||||
// end
|
||||
|
||||
|
||||
/**
|
||||
* Local parameters
|
||||
*/
|
||||
|
||||
|
||||
`ifdef TB_VERBOSE
|
||||
initial $display("Testbench for unit 'axis_loopback'");
|
||||
`endif
|
||||
|
||||
|
||||
/**
|
||||
* signals, registers and wires
|
||||
*/
|
||||
|
||||
reg rst;
|
||||
|
||||
|
||||
/**
|
||||
* Unit under test
|
||||
*/
|
||||
|
||||
axis_loopback
|
||||
uut (
|
||||
.clk (clk),
|
||||
.rst_n ( ~rst)
|
||||
);
|
||||
|
||||
|
||||
/**
|
||||
* Wave form display
|
||||
*/
|
||||
|
||||
task display_signals;
|
||||
$display(
|
||||
"%d\t%d",
|
||||
$time, rst,
|
||||
|
||||
);
|
||||
|
||||
endtask // display_signals
|
||||
|
||||
task display_header;
|
||||
$display(
|
||||
"\t\ttime\trst",
|
||||
|
||||
);
|
||||
endtask
|
||||
|
||||
|
||||
/**
|
||||
* Testbench program
|
||||
*/
|
||||
|
||||
initial begin
|
||||
// init values
|
||||
clk = 0;
|
||||
rst = 0;
|
||||
//end init
|
||||
|
||||
`ifdef TB_VERBOSE
|
||||
$display("RESET");
|
||||
`endif
|
||||
|
||||
repeat(6) @(negedge clk);
|
||||
rst <= 1'b1;
|
||||
repeat(6) @(negedge clk);
|
||||
rst <= 1'b0;
|
||||
@(negedge clk);
|
||||
|
||||
|
||||
`ifdef TB_VERBOSE
|
||||
$display("wait");
|
||||
`endif
|
||||
|
||||
repeat(10) @(negedge clk);
|
||||
|
||||
|
||||
`ifdef TB_VERBOSE
|
||||
$display("END");
|
||||
`endif
|
||||
-> end_trigger;
|
||||
end
|
||||
|
||||
endmodule
|
Loading…
x
Reference in New Issue
Block a user