diff --git a/hdl/axis/axis_addr.v b/hdl/axis/axis_addr.v
index 05e9224..bbcd033 100644
--- a/hdl/axis/axis_addr.v
+++ b/hdl/axis/axis_addr.v
@@ -74,6 +74,7 @@ module axis_addr
     reg                         burst_en;
     reg  [BURST_NB_WIDTH-1:0]   burst_nb;
     reg  [BURST_NB_WIDTH-1:0]   burst_cnt;
+    wire                        burst_done;
 
     reg  [CONFIG_DWIDTH-1:0]    cfg_length_r;
     reg                         cfg_valid_r;
@@ -155,44 +156,44 @@ module axis_addr
 
 
     always @* begin : ADDR_
-        state_nx <= 'b0;
+        state_nx = 'b0;
 
         case (1'b1)
             state[IDLE] : begin
                 if (cfg_valid) begin
-                    state_nx[SETUP] <= 1'b1;
+                    state_nx[SETUP] = 1'b1;
                 end
-                else state_nx[IDLE] <= 1'b1;
+                else state_nx[IDLE] = 1'b1;
             end
             state[SETUP] : begin
                 if (cfg_done & burst_en) begin
-                    state_nx[BURST] <= 1'b1;
+                    state_nx[BURST] = 1'b1;
                 end
                 else if (cfg_done & ~burst_en) begin
-                    state_nx[LAST] <= 1'b1;
+                    state_nx[LAST] = 1'b1;
                 end
-                else state_nx[SETUP] <= 1'b1;
+                else state_nx[SETUP] = 1'b1;
             end
             state[BURST] : begin
                 if (axi_aready & burst_done & last_en) begin
-                    state_nx[LAST] <= 1'b1;
+                    state_nx[LAST] = 1'b1;
                 end
                 else if (axi_aready & burst_done & ~last_en) begin
-                    state_nx[DONE] <= 1'b1;
+                    state_nx[DONE] = 1'b1;
                 end
-                else state_nx[BURST] <= 1'b1;
+                else state_nx[BURST] = 1'b1;
             end
             state[LAST] : begin
                 if (axi_aready) begin
-                    state_nx[DONE] <= 1'b1;
+                    state_nx[DONE] = 1'b1;
                 end
-                else state_nx[LAST] <= 1'b1;
+                else state_nx[LAST] = 1'b1;
             end
             state[DONE] : begin
-                state_nx[IDLE] <= 1'b1;
+                state_nx[IDLE] = 1'b1;
             end
             default : begin
-                state_nx[IDLE] <= 1'b1;
+                state_nx[IDLE] = 1'b1;
             end
         endcase
     end
diff --git a/hdl/axis/axis_deserializer.v b/hdl/axis/axis_deserializer.v
index d820d33..d8c1390 100644
--- a/hdl/axis/axis_deserializer.v
+++ b/hdl/axis/axis_deserializer.v
@@ -57,13 +57,15 @@ module axis_deserializer
 
     genvar ii;
 
-    reg  [DATA_NB-1:0] token;
+    wire [DATA_NB:0]    token_i;
+    reg  [DATA_NB-1:0]  token;
 
 
     /**
      * Implementation
      */
 
+    assign token_i  = {token, token[DATA_NB-1]};
 
     assign up_ready = down_ready;
 
@@ -83,7 +85,7 @@ module axis_deserializer
     always @(posedge clk)
         if (rst | (down_ready & up_last)) token <= 'b1;
         else if (down_ready & up_valid) begin
-            token <= {token, token[DATA_NB-1]};
+            token <= token_i[0 +: DATA_NB];
         end
 
 
diff --git a/hdl/axis/axis_read.v b/hdl/axis/axis_read.v
index f0c3a3b..0c8dbeb 100644
--- a/hdl/axis/axis_read.v
+++ b/hdl/axis/axis_read.v
@@ -62,6 +62,7 @@ module axis_read
 
     localparam WIDTH_RATIO  = AXI_DATA_WIDTH/DATA_WIDTH;
     localparam CONFIG_NB    = 2;
+    localparam STORE_WIDTH  = CONFIG_DWIDTH*CONFIG_NB;
 
     localparam
         C_IDLE      = 0,
@@ -89,7 +90,8 @@ module axis_read
     reg  [CONFIG_AWIDTH-1:0]            cfg_addr_r;
     reg  [CONFIG_DWIDTH-1:0]            cfg_data_r;
     reg                                 cfg_valid_r;
-    reg  [CONFIG_DWIDTH*CONFIG_NB-1:0]  cfg_store;
+    wire [STORE_WIDTH+CONFIG_DWIDTH-1:0]    cfg_store_i;
+    reg  [STORE_WIDTH-1:0]              cfg_store;
     reg  [7:0]                          cfg_cnt;
 
     wire [CONFIG_DWIDTH-1:0]            start_addr;
@@ -97,12 +99,17 @@ module axis_read
     wire [CONFIG_DWIDTH-1:0]            str_length;
     reg  [CONFIG_DWIDTH-1:0]            cfg_length;
     reg                                 cfg_enable;
+    wire                                id_valid;
+    wire                                addressed;
+    wire                                axis_data;
 
 
     /**
      * Implementation
      */
 
+    assign cfg_store_i  = {cfg_store, cfg_data_r};
+
     assign start_addr   = cfg_store[CONFIG_DWIDTH +: CONFIG_DWIDTH];
 
     assign str_length   = cfg_store[0 +: CONFIG_DWIDTH];
@@ -129,7 +136,7 @@ module axis_read
 
     always @(posedge clk)
         if (c_state[C_CONFIG] & axis_data) begin
-            cfg_store <= {cfg_store, cfg_data_r};
+            cfg_store <= cfg_store_i[0 +: STORE_WIDTH];
         end
 
 
@@ -137,7 +144,7 @@ module axis_read
         cfg_cnt <= 'b0;
 
         if (c_state[C_CONFIG]) begin
-            cfg_cnt <= cfg_cnt + axis_data;
+            cfg_cnt <= cfg_cnt + {7'b0, axis_data};
         end
     end
 
diff --git a/hdl/axis/axis_read_data.v b/hdl/axis/axis_read_data.v
index e9c7a6e..1ee988e 100644
--- a/hdl/axis/axis_read_data.v
+++ b/hdl/axis/axis_read_data.v
@@ -24,9 +24,9 @@ module axis_read_data
   #(parameter
     BUF_AWIDTH      = 9,
     CONFIG_DWIDTH   = 32,
-    WIDTH_RATIO     = 16,
+    WIDTH_RATIO     = 2,
 
-    AXI_DATA_WIDTH  = 32,
+    AXI_DATA_WIDTH  = 64,
     DATA_WIDTH      = 32)
    (input                               clk,
     input                               rst,
@@ -92,8 +92,10 @@ module axis_read_data
 
 
     always @(posedge clk)
-        if (state[IDLE])    str_cnt <= 'b0;
-        else                str_cnt <= str_cnt + buf_pop;
+        if (state[IDLE]) str_cnt <= 'b0;
+        else if (buf_pop) begin
+            str_cnt <= str_cnt + 'b1;
+        end
 
 
     always @(posedge clk)
@@ -148,29 +150,29 @@ module axis_read_data
 
 
     always @* begin : DATA_
-        state_nx <= 'b0;
+        state_nx = 'b0;
 
         case (1'b1)
             state[IDLE] : begin
                 if (cfg_valid) begin
-                    state_nx[ACTIVE] <= 1'b1;
+                    state_nx[ACTIVE] = 1'b1;
                 end
-                else state_nx[IDLE] <= 1'b1;
+                else state_nx[IDLE] = 1'b1;
             end
             state[ACTIVE] : begin
                 if (buf_pop & (str_length == str_cnt)) begin
-                    state_nx[WAIT] <= 1'b1;
+                    state_nx[WAIT] = 1'b1;
                 end
-                else state_nx[ACTIVE] <= 1'b1;
+                else state_nx[ACTIVE] = 1'b1;
             end
             state[WAIT] : begin
-                state_nx[DONE] <= 1'b1;
+                state_nx[DONE] = 1'b1;
             end
             state[DONE] : begin
-                state_nx[IDLE] <= 1'b1;
+                state_nx[IDLE] = 1'b1;
             end
             default : begin
-                state_nx[IDLE] <= 1'b1;
+                state_nx[IDLE] = 1'b1;
             end
         endcase
     end
diff --git a/hdl/axis/axis_write.v b/hdl/axis/axis_write.v
index e4f7110..ad6cd47 100644
--- a/hdl/axis/axis_write.v
+++ b/hdl/axis/axis_write.v
@@ -63,6 +63,7 @@ module axis_write
 
     localparam WIDTH_RATIO  = AXI_DATA_WIDTH/DATA_WIDTH;
     localparam CONFIG_NB    = 2;
+    localparam STORE_WIDTH  = CONFIG_DWIDTH*CONFIG_NB;
 
     localparam
         C_IDLE      = 0,
@@ -90,7 +91,8 @@ module axis_write
     reg  [CONFIG_AWIDTH-1:0]            cfg_addr_r;
     reg  [CONFIG_DWIDTH-1:0]            cfg_data_r;
     reg                                 cfg_valid_r;
-    reg  [CONFIG_DWIDTH*CONFIG_NB-1:0]  cfg_store;
+    wire [STORE_WIDTH+CONFIG_DWIDTH-1:0]    cfg_store_i;
+    reg  [STORE_WIDTH-1:0]              cfg_store;
     reg  [7:0]                          cfg_cnt;
 
     wire [CONFIG_DWIDTH-1:0]            start_addr;
@@ -98,12 +100,17 @@ module axis_write
     wire [CONFIG_DWIDTH-1:0]            str_length;
     reg  [CONFIG_DWIDTH-1:0]            cfg_length;
     reg                                 cfg_enable;
+    wire                                id_valid;
+    wire                                addressed;
+    wire                                axis_data;
 
 
     /**
      * Implementation
      */
 
+    assign cfg_store_i  = {cfg_store, cfg_data_r};
+
     assign start_addr   = cfg_store[CONFIG_DWIDTH +: CONFIG_DWIDTH];
 
     assign str_length   = cfg_store[0 +: CONFIG_DWIDTH];
@@ -130,7 +137,7 @@ module axis_write
 
     always @(posedge clk)
         if (c_state[C_CONFIG] & axis_data) begin
-            cfg_store <= {cfg_store, cfg_data_r};
+            cfg_store <= cfg_store_i[0 +: STORE_WIDTH];
         end
 
 
@@ -138,7 +145,7 @@ module axis_write
         cfg_cnt <= 'b0;
 
         if (c_state[C_CONFIG]) begin
-            cfg_cnt <= cfg_cnt + axis_data;
+            cfg_cnt <= cfg_cnt + {7'b0, axis_data};
         end
     end
 
diff --git a/hdl/axis/axis_write_data.v b/hdl/axis/axis_write_data.v
index 085aac0..bad2880 100644
--- a/hdl/axis/axis_write_data.v
+++ b/hdl/axis/axis_write_data.v
@@ -24,11 +24,11 @@ module axis_write_data
   #(parameter
     BUF_AWIDTH      = 9,
     CONFIG_DWIDTH   = 32,
-    WIDTH_RATIO     = 16,
+    WIDTH_RATIO     = 2,
     CONVERT_SHIFT   = 3,
 
     AXI_LEN_WIDTH   = 8,
-    AXI_DATA_WIDTH  = 32,
+    AXI_DATA_WIDTH  = 64,
     DATA_WIDTH      = 32)
    (input                               clk,
     input                               rst,
@@ -112,8 +112,10 @@ module axis_write_data
 
 
     always @(posedge clk)
-        if      (state[IDLE])   str_cnt <= 'b0;
-        else if (axi_wready)    str_cnt <= str_cnt + buf_pop;
+        if (state[IDLE]) str_cnt <= 'b0;
+        else if (axi_wready & buf_pop) begin
+            str_cnt <= str_cnt + 'd1;
+        end
 
 
     always @(posedge clk)
@@ -174,32 +176,32 @@ module axis_write_data
 
 
     always @* begin : DATA_
-        state_nx <= 'b0;
+        state_nx = 'b0;
 
         case (1'b1)
             state[IDLE] : begin
                 if (cfg_valid) begin
-                    state_nx[ACTIVE] <= 1'b1;
+                    state_nx[ACTIVE] = 1'b1;
                 end
-                else state_nx[IDLE] <= 1'b1;
+                else state_nx[IDLE] = 1'b1;
             end
             state[ACTIVE] : begin
                 if (axi_wready & buf_pop & (str_length == str_cnt)) begin
-                    state_nx[WAIT] <= 1'b1;
+                    state_nx[WAIT] = 1'b1;
                 end
-                else state_nx[ACTIVE] <= 1'b1;
+                else state_nx[ACTIVE] = 1'b1;
             end
             state[WAIT] : begin
                 if (axi_wready & axi_wlast) begin
-                    state_nx[DONE] <= 1'b1;
+                    state_nx[DONE] = 1'b1;
                 end
-                else state_nx[WAIT] <= 1'b1;
+                else state_nx[WAIT] = 1'b1;
             end
             state[DONE] : begin
-                state_nx[IDLE] <= 1'b1;
+                state_nx[IDLE] = 1'b1;
             end
             default : begin
-                state_nx[IDLE] <= 1'b1;
+                state_nx[IDLE] = 1'b1;
             end
         endcase
     end
diff --git a/hdl/fifo/fifo_simple.v b/hdl/fifo/fifo_simple.v
index 571ecd1..14b3a9c 100644
--- a/hdl/fifo/fifo_simple.v
+++ b/hdl/fifo/fifo_simple.v
@@ -114,10 +114,10 @@ module fifo_simple
 
 
     // pop next
-    assign pop_ptr_nx   = pop_ptr + (pop & ~empty);
+    assign pop_ptr_nx   = pop_ptr + {{ADDR_WIDTH-1{1'b0}}, (pop & ~empty)};
 
     // push next
-    assign push_ptr_nx  = push_ptr + (push & ~full);
+    assign push_ptr_nx  = push_ptr + {{ADDR_WIDTH-1{1'b0}}, (push & ~full)};
 
 
     // registered population count.