From 4ad550b31a93dbad04ed87d6a5b406a44b4a7c39 Mon Sep 17 00:00:00 2001 From: Berin Martini Date: Sun, 3 Jun 2018 15:12:48 -0700 Subject: [PATCH] Move some of the axis_addr assigns around module Moves them closer to where they are used for readability. --- hdl/axis/axis_addr.v | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/hdl/axis/axis_addr.v b/hdl/axis/axis_addr.v index bd357f4..6ed3cd9 100644 --- a/hdl/axis/axis_addr.v +++ b/hdl/axis/axis_addr.v @@ -91,14 +91,6 @@ module axis_addr assign cfg_ready = state[IDLE]; - assign axi_aaddr = axi_address; - - assign axi_alen = state[BURST] ? (BURST_LENGTH-1) : last_nb; - - assign axi_avalid = state[BURST] | state[LAST]; - - assign burst_done = (burst_nb == burst_cnt); - always @(posedge clk) if (rst) cfg_valid_r <= 1'b0; @@ -150,6 +142,9 @@ module axis_addr end + assign burst_done = (burst_nb == burst_cnt); + + always @(posedge clk) if (rst) begin state <= 'b0; @@ -202,6 +197,13 @@ module axis_addr end + assign axi_aaddr = axi_address; + + assign axi_alen = state[BURST] ? (BURST_LENGTH-1) : last_nb; + + assign axi_avalid = state[BURST] | state[LAST]; + + endmodule `undef MIN