FPGA/zynq-axis
1
0
Fork 0
mirror of https://github.com/bmartini/zynq-axis.git synced 2024-09-05 19:19:27 +08:00
Code Issues Projects Releases Wiki Activity

Move some of the axis_addr assigns around module

Browse Source 
Moves them closer to where they are used for readability.
This commit is contained in:
Berin Martini 2018-06-03 15:12:48 -07:00
parent 0d560dff11
commit 4ad550b31a
1 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
hdl/axis/axis_addr.v
View File

@ -91,14 +91,6 @@ module axis_addr
assign cfg_ready = state[IDLE]; assign cfg_ready = state[IDLE];
assign axi_aaddr = axi_address;
assign axi_alen = state[BURST] ? (BURST_LENGTH-1) : last_nb;
assign axi_avalid = state[BURST] | state[LAST];
assign burst_done = (burst_nb == burst_cnt);
always @(posedge clk) always @(posedge clk)
if (rst) cfg_valid_r <= 1'b0; if (rst) cfg_valid_r <= 1'b0;
@ -150,6 +142,9 @@ module axis_addr
end end
assign burst_done = (burst_nb == burst_cnt);
always @(posedge clk) always @(posedge clk)
if (rst) begin if (rst) begin
state <= 'b0; state <= 'b0;
@ -202,6 +197,13 @@ module axis_addr
end end
assign axi_aaddr = axi_address;
assign axi_alen = state[BURST] ? (BURST_LENGTH-1) : last_nb;
assign axi_avalid = state[BURST] | state[LAST];
endmodule endmodule
`undef MIN `undef MIN