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Associate axi_clk to AXI bus interfaces

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By explicitly pairing the clock running the interface with the interface
in Vivado it allows for better timing analysis and remove some 'CRITICAL
WARNINGS'.
This commit is contained in:
Berin Martini 2015-02-09 14:21:20 -05:00
parent 1074aa90fb
commit 55319e7d19
1 changed files with 6 additions and 1 deletions
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7
syn/project-zedboard_axis/zedboard_axis.srcs/sources_1/bd/system/system.bd
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@ -134,7 +134,12 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters/>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M00_AXI:S_AXI_HP0</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>RST.AXI_RST_N</spirit:name>