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Bug fix: AXI transaction ID usage and generation

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Because the axis modules are minimalist, it assumes that all
transactions are performed without error and that transaction processing
is performed in-order. Thus the transaction IDs can safely be set to
zero. Doing so also fixes a bug in the write path that had prevented
multiple burst of data being sent. This was due to the fact that the
write data burst ID needs to have the same ID as the write address. But
the write address module was incrementing the ID while the write data ID
was not being set at all.
This commit is contained in:
Berin Martini 2015-01-08 11:24:46 -05:00
parent 9ee0ce64ee
commit 76537507eb
5 changed files with 5 additions and 23 deletions
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8
hdl/axis/axis.v
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@ -66,6 +66,7 @@ module axis #(
// AXI write data channel signals
input axi_wready,
output [AXI_ID_WIDTH-1:0] axi_wid,
output [AXI_DATA_WIDTH-1:0] axi_wdata,
output [AXI_DATA_WIDTH/8-1:0] axi_wstrb,
output axi_wlast,
@ -125,6 +126,8 @@ module axis #(
assign axi_awburst = 2'h1; // INCREMENTING
assign axi_awqos = 4'h0; // NOT_QOS_PARTICIPANT
assign axi_awsize = BURST_SIZE;
assign axi_awid = {AXI_ID_WIDTH{1'b0}};
assign axi_wid = {AXI_ID_WIDTH{1'b0}};
assign axi_wstrb = {(AXI_DATA_WIDTH/8){1'b1}};
// read path static values
@ -134,6 +137,7 @@ module axis #(
assign axi_arburst = 2'h1; // INCREMENTING
assign axi_arqos = 4'h0; // NOT_QOS_PARTICIPANT
assign axi_arsize = BURST_SIZE;
assign axi_arid = {AXI_ID_WIDTH{1'b0}};
// assume that all writes are successful and therefore do not need to
@ -150,7 +154,6 @@ module axis #(
.CONFIG_AWIDTH (CONFIG_AWIDTH),
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
@ -164,7 +167,6 @@ module axis #(
.cfg_valid (cfg_valid),
.axi_awready (axi_awready),
.axi_awid (axi_awid),
.axi_awaddr (axi_awaddr),
.axi_awlen (axi_awlen),
.axi_awvalid (axi_awvalid),
@ -189,7 +191,6 @@ module axis #(
.CONFIG_AWIDTH (CONFIG_AWIDTH),
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
@ -203,7 +204,6 @@ module axis #(
.cfg_valid (cfg_valid),
.axi_arready (axi_arready),
.axi_arid (axi_arid),
.axi_araddr (axi_araddr),
.axi_arlen (axi_arlen),
.axi_arvalid (axi_arvalid),

11
hdl/axis/axis_addr.v
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@ -22,7 +22,6 @@ module axis_addr
CONFIG_DWIDTH = 32,
WIDTH_RATIO = 16,
CONVERT_SHIFT = 3,
AXI_ID_WIDTH = 8,
AXI_LEN_WIDTH = 8,
AXI_ADDR_WIDTH = 32,
AXI_DATA_WIDTH = 256)
@ -35,7 +34,6 @@ module axis_addr
output cfg_ready,
input axi_aready,
output reg [AXI_ID_WIDTH-1:0] axi_aid,
output [AXI_ADDR_WIDTH-1:0] axi_aaddr,
output [AXI_LEN_WIDTH-1:0] axi_alen,
output axi_avalid
@ -200,15 +198,6 @@ module axis_addr
end
always @(posedge clk)
if (state[IDLE]) begin
axi_aid <= 'b0;
end
else if (axi_aready & axi_avalid) begin
axi_aid <= axi_aid + 1;
end
endmodule
`endif // `ifndef _axis_addr_

4
hdl/axis/axis_read.v
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@ -31,7 +31,6 @@ module axis_read
CONFIG_AWIDTH = 5,
CONFIG_DWIDTH = 32,
AXI_ID_WIDTH = 8,
AXI_LEN_WIDTH = 8,
AXI_ADDR_WIDTH = 32,
AXI_DATA_WIDTH = 32,
@ -44,7 +43,6 @@ module axis_read
input cfg_valid,
input axi_arready,
output [AXI_ID_WIDTH-1:0] axi_arid,
output [AXI_ADDR_WIDTH-1:0] axi_araddr,
output [AXI_LEN_WIDTH-1:0] axi_arlen,
output axi_arvalid,
@ -203,7 +201,6 @@ module axis_read
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.WIDTH_RATIO (WIDTH_RATIO),
.CONVERT_SHIFT ($clog2(WIDTH_RATIO)),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH))
@ -217,7 +214,6 @@ module axis_read
.cfg_ready (cfg_addr_ready),
.axi_aready (axi_arready),
.axi_aid (axi_arid),
.axi_aaddr (axi_araddr),
.axi_alen (axi_arlen),
.axi_avalid (axi_arvalid)

4
hdl/axis/axis_write.v
View File

@ -31,7 +31,6 @@ module axis_write
CONFIG_AWIDTH = 5,
CONFIG_DWIDTH = 32,
AXI_ID_WIDTH = 8,
AXI_LEN_WIDTH = 8,
AXI_ADDR_WIDTH = 32,
AXI_DATA_WIDTH = 32,
@ -44,7 +43,6 @@ module axis_write
input cfg_valid,
input axi_awready,
output [AXI_ID_WIDTH-1:0] axi_awid,
output [AXI_ADDR_WIDTH-1:0] axi_awaddr,
output [AXI_LEN_WIDTH-1:0] axi_awlen,
output axi_awvalid,
@ -202,7 +200,6 @@ module axis_write
.CONFIG_DWIDTH (CONFIG_DWIDTH),
.WIDTH_RATIO (WIDTH_RATIO),
.CONVERT_SHIFT ($clog2(WIDTH_RATIO)),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_LEN_WIDTH (AXI_LEN_WIDTH),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH))
@ -216,7 +213,6 @@ module axis_write
.cfg_ready (cfg_addr_ready),
.axi_aready (axi_awready),
.axi_aid (axi_awid),
.axi_aaddr (axi_awaddr),
.axi_alen (axi_awlen),
.axi_avalid (axi_awvalid)

1
hdl/top/zedboard_axis.v
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@ -344,6 +344,7 @@ module zedboard_axis
.axi_awvalid (axi_hp0_awvalid),
.axi_wready (axi_hp0_wready),
.axi_wid (axi_hp0_wid),
.axi_wdata (axi_hp0_wdata),
.axi_wstrb (axi_hp0_wstrb),
.axi_wlast (axi_hp0_wlast),