diff --git a/hdl/axis/axis.v b/hdl/axis/axis.v
index bc5cbf2..4803d95 100644
--- a/hdl/axis/axis.v
+++ b/hdl/axis/axis.v
@@ -66,6 +66,7 @@ module axis #(
 
     // AXI write data channel signals
     input                               axi_wready,
+    output      [AXI_ID_WIDTH-1:0]      axi_wid,
     output      [AXI_DATA_WIDTH-1:0]    axi_wdata,
     output      [AXI_DATA_WIDTH/8-1:0]  axi_wstrb,
     output                              axi_wlast,
@@ -125,6 +126,8 @@ module axis #(
     assign axi_awburst  = 2'h1; // INCREMENTING
     assign axi_awqos    = 4'h0; // NOT_QOS_PARTICIPANT
     assign axi_awsize   = BURST_SIZE;
+    assign axi_awid     = {AXI_ID_WIDTH{1'b0}};
+    assign axi_wid      = {AXI_ID_WIDTH{1'b0}};
     assign axi_wstrb    = {(AXI_DATA_WIDTH/8){1'b1}};
 
     // read path static values
@@ -134,6 +137,7 @@ module axis #(
     assign axi_arburst  = 2'h1; // INCREMENTING
     assign axi_arqos    = 4'h0; // NOT_QOS_PARTICIPANT
     assign axi_arsize   = BURST_SIZE;
+    assign axi_arid     = {AXI_ID_WIDTH{1'b0}};
 
 
     //  assume that all writes are successful and therefore do not need to
@@ -150,7 +154,6 @@ module axis #(
         .CONFIG_AWIDTH  (CONFIG_AWIDTH),
         .CONFIG_DWIDTH  (CONFIG_DWIDTH),
 
-        .AXI_ID_WIDTH   (AXI_ID_WIDTH),
         .AXI_LEN_WIDTH  (AXI_LEN_WIDTH),
         .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
         .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
@@ -164,7 +167,6 @@ module axis #(
         .cfg_valid      (cfg_valid),
 
         .axi_awready    (axi_awready),
-        .axi_awid       (axi_awid),
         .axi_awaddr     (axi_awaddr),
         .axi_awlen      (axi_awlen),
         .axi_awvalid    (axi_awvalid),
@@ -189,7 +191,6 @@ module axis #(
         .CONFIG_AWIDTH  (CONFIG_AWIDTH),
         .CONFIG_DWIDTH  (CONFIG_DWIDTH),
 
-        .AXI_ID_WIDTH   (AXI_ID_WIDTH),
         .AXI_LEN_WIDTH  (AXI_LEN_WIDTH),
         .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
         .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
@@ -203,7 +204,6 @@ module axis #(
         .cfg_valid      (cfg_valid),
 
         .axi_arready    (axi_arready),
-        .axi_arid       (axi_arid),
         .axi_araddr     (axi_araddr),
         .axi_arlen      (axi_arlen),
         .axi_arvalid    (axi_arvalid),
diff --git a/hdl/axis/axis_addr.v b/hdl/axis/axis_addr.v
index 7ae46b9..05e9224 100644
--- a/hdl/axis/axis_addr.v
+++ b/hdl/axis/axis_addr.v
@@ -22,7 +22,6 @@ module axis_addr
     CONFIG_DWIDTH   = 32,
     WIDTH_RATIO     = 16,
     CONVERT_SHIFT   = 3,
-    AXI_ID_WIDTH    = 8,
     AXI_LEN_WIDTH   = 8,
     AXI_ADDR_WIDTH  = 32,
     AXI_DATA_WIDTH  = 256)
@@ -35,7 +34,6 @@ module axis_addr
     output                              cfg_ready,
 
     input                               axi_aready,
-    output reg  [AXI_ID_WIDTH-1:0]      axi_aid,
     output      [AXI_ADDR_WIDTH-1:0]    axi_aaddr,
     output      [AXI_LEN_WIDTH-1:0]     axi_alen,
     output                              axi_avalid
@@ -200,15 +198,6 @@ module axis_addr
     end
 
 
-    always @(posedge clk)
-        if (state[IDLE]) begin
-            axi_aid <= 'b0;
-        end
-        else if (axi_aready & axi_avalid) begin
-            axi_aid <= axi_aid + 1;
-        end
-
-
 endmodule
 
 `endif //  `ifndef _axis_addr_
diff --git a/hdl/axis/axis_read.v b/hdl/axis/axis_read.v
index c2bde82..bbc4de6 100644
--- a/hdl/axis/axis_read.v
+++ b/hdl/axis/axis_read.v
@@ -31,7 +31,6 @@ module axis_read
     CONFIG_AWIDTH   = 5,
     CONFIG_DWIDTH   = 32,
 
-    AXI_ID_WIDTH    = 8,
     AXI_LEN_WIDTH   = 8,
     AXI_ADDR_WIDTH  = 32,
     AXI_DATA_WIDTH  = 32,
@@ -44,7 +43,6 @@ module axis_read
     input                               cfg_valid,
 
     input                               axi_arready,
-    output      [AXI_ID_WIDTH-1:0]      axi_arid,
     output      [AXI_ADDR_WIDTH-1:0]    axi_araddr,
     output      [AXI_LEN_WIDTH-1:0]     axi_arlen,
     output                              axi_arvalid,
@@ -203,7 +201,6 @@ module axis_read
         .CONFIG_DWIDTH  (CONFIG_DWIDTH),
         .WIDTH_RATIO    (WIDTH_RATIO),
         .CONVERT_SHIFT  ($clog2(WIDTH_RATIO)),
-        .AXI_ID_WIDTH   (AXI_ID_WIDTH),
         .AXI_LEN_WIDTH  (AXI_LEN_WIDTH),
         .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
         .AXI_DATA_WIDTH (AXI_DATA_WIDTH))
@@ -217,7 +214,6 @@ module axis_read
         .cfg_ready      (cfg_addr_ready),
 
         .axi_aready     (axi_arready),
-        .axi_aid        (axi_arid),
         .axi_aaddr      (axi_araddr),
         .axi_alen       (axi_arlen),
         .axi_avalid     (axi_arvalid)
diff --git a/hdl/axis/axis_write.v b/hdl/axis/axis_write.v
index 10b5d60..e4f7110 100644
--- a/hdl/axis/axis_write.v
+++ b/hdl/axis/axis_write.v
@@ -31,7 +31,6 @@ module axis_write
     CONFIG_AWIDTH   = 5,
     CONFIG_DWIDTH   = 32,
 
-    AXI_ID_WIDTH    = 8,
     AXI_LEN_WIDTH   = 8,
     AXI_ADDR_WIDTH  = 32,
     AXI_DATA_WIDTH  = 32,
@@ -44,7 +43,6 @@ module axis_write
     input                               cfg_valid,
 
     input                               axi_awready,
-    output      [AXI_ID_WIDTH-1:0]      axi_awid,
     output      [AXI_ADDR_WIDTH-1:0]    axi_awaddr,
     output      [AXI_LEN_WIDTH-1:0]     axi_awlen,
     output                              axi_awvalid,
@@ -202,7 +200,6 @@ module axis_write
         .CONFIG_DWIDTH  (CONFIG_DWIDTH),
         .WIDTH_RATIO    (WIDTH_RATIO),
         .CONVERT_SHIFT  ($clog2(WIDTH_RATIO)),
-        .AXI_ID_WIDTH   (AXI_ID_WIDTH),
         .AXI_LEN_WIDTH  (AXI_LEN_WIDTH),
         .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
         .AXI_DATA_WIDTH (AXI_DATA_WIDTH))
@@ -216,7 +213,6 @@ module axis_write
         .cfg_ready      (cfg_addr_ready),
 
         .axi_aready     (axi_awready),
-        .axi_aid        (axi_awid),
         .axi_aaddr      (axi_awaddr),
         .axi_alen       (axi_awlen),
         .axi_avalid     (axi_awvalid)
diff --git a/hdl/top/zedboard_axis.v b/hdl/top/zedboard_axis.v
index 6060ad0..84bd31f 100644
--- a/hdl/top/zedboard_axis.v
+++ b/hdl/top/zedboard_axis.v
@@ -344,6 +344,7 @@ module zedboard_axis
         .axi_awvalid    (axi_hp0_awvalid),
 
         .axi_wready     (axi_hp0_wready),
+        .axi_wid        (axi_hp0_wid),
         .axi_wdata      (axi_hp0_wdata),
         .axi_wstrb      (axi_hp0_wstrb),
         .axi_wlast      (axi_hp0_wlast),