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Bug fix: axi4lite_cfg port list definition

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Berin Martini 2015-01-02 17:31:35 -05:00
parent 8082ee8df7
commit 8a62d2ba82
1 changed files with 1 additions and 1 deletions
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hdl/ctrl/axi4lite_cfg.v
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@ -28,7 +28,7 @@ module axi4lite_cfg
output axi_wready, // Write Data Ready output axi_wready, // Write Data Ready
output [1:0] axi_bresp, // Write Response output [1:0] axi_bresp, // Write Response
output reg axi_bvalid, // Write Response Valid output axi_bvalid, // Write Response Valid
input axi_bready, // Write Response Ready input axi_bready, // Write Response Ready
input [AXI_WIDTH-1:0] axi_araddr, // Read Address input [AXI_WIDTH-1:0] axi_araddr, // Read Address