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Replace nested generate with a clk for loop in axis_gbox

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I prefer the nested generate like I have in the axis_deserializer.v but the
current simulator does not like it so for the moment I'll change the module to
used the clocked for loop.
This commit is contained in:
Berin Martini 2018-06-03 23:32:42 -07:00
parent 12487c3e6e
commit 9418ebcaf0
1 changed files with 4 additions and 5 deletions
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7
hdl/axis/axis_gbox.v
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@ -65,7 +65,6 @@ module axis_gbox
* Internal signals * Internal signals
*/ */
genvar ii;
/** /**
* Implementation * Implementation
@ -176,6 +175,7 @@ module axis_gbox
localparam DATA_NB = DATA_DN_WIDTH/DATA_UP_WIDTH; localparam DATA_NB = DATA_DN_WIDTH/DATA_UP_WIDTH;
integer ii;
wire [2*DATA_NB-1:0] token_nx; wire [2*DATA_NB-1:0] token_nx;
reg [DATA_NB-1:0] token; reg [DATA_NB-1:0] token;
reg [DATA_DN_WIDTH-1:0] dn_data_i; reg [DATA_DN_WIDTH-1:0] dn_data_i;
@ -215,14 +215,13 @@ module axis_gbox
end end
for (ii=0; ii<DATA_NB; ii=ii+1) begin : CONCAT_
always @(posedge clk) always @(posedge clk)
for (ii=0; ii<DATA_NB; ii=ii+1) begin
if (dn_rdy & token[ii]) begin if (dn_rdy & token[ii]) begin
dn_data_i[ii*DATA_UP_WIDTH +: DATA_UP_WIDTH] <= up_data; dn_data_i[ii*DATA_UP_WIDTH +: DATA_UP_WIDTH] <= up_data;
end end
end end
end end
endgenerate endgenerate