From 9c3c828b1f4e58f43c03a9e4b8bc2df27664bb8b Mon Sep 17 00:00:00 2001 From: Berin Martini Date: Mon, 30 May 2016 22:02:29 -0700 Subject: [PATCH] Update axis_serializer for 1-to-1 in/out data size In this configuration the axis_serializer would just register and pass on the input data down stream. --- hdl/axis/axis_serializer.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hdl/axis/axis_serializer.v b/hdl/axis/axis_serializer.v index eea7754..91b3018 100644 --- a/hdl/axis/axis_serializer.v +++ b/hdl/axis/axis_serializer.v @@ -51,7 +51,7 @@ module axis_serializer wire [2*DATA_NB-1:0] token_nx; reg [DATA_NB-1:0] token; - reg [DATA_NB-1:0] serial_valid; + reg [DATA_NB:0] serial_valid; reg [(DATA_WIDTH*DATA_NB)-1:0] serial_data; wire serial_start; @@ -91,9 +91,9 @@ module axis_serializer if (rst) serial_valid <= 'b0; else if (down_ready) begin - serial_valid <= {serial_valid[0 +: DATA_NB-1], 1'b0}; + serial_valid <= {serial_valid[0 +: DATA_NB], 1'b0}; if (up_ready & up_valid) begin - serial_valid <= {serial_valid[0 +: DATA_NB-1], 1'b1}; + serial_valid <= {serial_valid[0 +: DATA_NB], 1'b1}; end end @@ -107,7 +107,7 @@ module axis_serializer always @(posedge clk) if (rst) down_valid <= 1'b0; else if (down_ready) begin - down_valid <= |(serial_valid); + down_valid <= |(serial_valid[0 +: DATA_NB]); end