From b05b6bd6d48d967ad8cefa4aed3e98355a384849 Mon Sep 17 00:00:00 2001
From: Berin Martini <berin.martini@gmail.com>
Date: Mon, 30 May 2016 19:48:30 -0700
Subject: [PATCH] Use blocking assignment in non-clocked always block

Combinational logic shouldn't use the non-blocking assignment.
---
 hdl/axis/axis_write_data.v | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hdl/axis/axis_write_data.v b/hdl/axis/axis_write_data.v
index 085aac0..58ebb0a 100644
--- a/hdl/axis/axis_write_data.v
+++ b/hdl/axis/axis_write_data.v
@@ -174,32 +174,32 @@ module axis_write_data
 
 
     always @* begin : DATA_
-        state_nx <= 'b0;
+        state_nx = 'b0;
 
         case (1'b1)
             state[IDLE] : begin
                 if (cfg_valid) begin
-                    state_nx[ACTIVE] <= 1'b1;
+                    state_nx[ACTIVE] = 1'b1;
                 end
-                else state_nx[IDLE] <= 1'b1;
+                else state_nx[IDLE] = 1'b1;
             end
             state[ACTIVE] : begin
                 if (axi_wready & buf_pop & (str_length == str_cnt)) begin
-                    state_nx[WAIT] <= 1'b1;
+                    state_nx[WAIT] = 1'b1;
                 end
-                else state_nx[ACTIVE] <= 1'b1;
+                else state_nx[ACTIVE] = 1'b1;
             end
             state[WAIT] : begin
                 if (axi_wready & axi_wlast) begin
-                    state_nx[DONE] <= 1'b1;
+                    state_nx[DONE] = 1'b1;
                 end
-                else state_nx[WAIT] <= 1'b1;
+                else state_nx[WAIT] = 1'b1;
             end
             state[DONE] : begin
-                state_nx[IDLE] <= 1'b1;
+                state_nx[IDLE] = 1'b1;
             end
             default : begin
-                state_nx[IDLE] <= 1'b1;
+                state_nx[IDLE] = 1'b1;
             end
         endcase
     end