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mirror of https://github.com/bmartini/zynq-axis.git synced 2024-09-05 19:19:27 +08:00

138 Commits

Author SHA1 Message Date
Berin Martini
61089223ef Merge branch 'update-axis'
More robust configuration that will allow for the use of the AXIS module in a
scatter/gather operation. Will be able to handle contiguous streams of
read/write data even when they are part of different configurations.
2018-07-21 14:57:57 -07:00
Berin Martini
03ba4e7d1c Spread include macro fence over two lines
This was to allow for simulation with ModelSim.
2018-07-21 14:41:01 -07:00
Berin Martini
fb3aa2de39 Increment AXI IDs in both axis_read.v & axis_write.v
When sending a read or write request the axi_(aw|w|ar)id values are now
incremented so that every request has a unique ID. This might be ignored by
downstream IP, however, there are some IP that require uniq IDs.
2018-06-10 14:02:18 -07:00
Berin Martini
ba57ecbf79 Bug fix: axis_write_data contiguous streams
When a stream comes from the user system and is done there is a possibility
that the first data word of the next stream also gets popped from the buffer.
In those cases we need to take note of this so that the 'str_cnt' can be
correctly incremented and the deser_(done|last) values correctly reset.
2018-06-10 13:02:44 -07:00
Berin Martini
d5f185789e Add cfg_ready in axis.v
These are not used but they are added to remove warnings in some linters.
2018-06-04 00:11:45 -07:00
Berin Martini
ff1a558aa5 Change axis_read to accept a stream of cfg words
Also provide a method of optional cfg back pressure when the cfg buffers are
full. This should allow for many small reads to be queued.
2018-06-04 00:08:06 -07:00
Berin Martini
2fb96ca60a Change axis_write to accept a stream of cfg words
Also provide a method of optional cfg back pressure when the cfg buffers are
full. This should allow for many small writes to be queued.
2018-06-04 00:04:37 -07:00
Berin Martini
92745f5a9f Move reg of cfg bus into axis.v from axis_(read|write).v
This makes it easier to now change the config FSM in both the axis_read and
axis_write.
2018-06-03 23:59:50 -07:00
Berin Martini
aee2fcc9b5 Add BUF_CFG_AWIDTH parameter to axis(_read|_write).v 2018-06-03 23:57:29 -07:00
Berin Martini
d3142d742b Remove unused axis_(serializer|deserializer) modules
Since both of these have been replaced by the axis_gbox module.
2018-06-03 23:38:34 -07:00
Berin Martini
3957f36928 Use axis_gbox in axis_write_data
This replaces the axis_deserializer module.
2018-06-03 23:36:09 -07:00
Berin Martini
9418ebcaf0 Replace nested generate with a clk for loop in axis_gbox
I prefer the nested generate like I have in the axis_deserializer.v but the
current simulator does not like it so for the moment I'll change the module to
used the clocked for loop.
2018-06-03 23:32:42 -07:00
Berin Martini
12487c3e6e Move str counter in axis_write_data after data fifo
This will for a continuous stream of data from the user system to be sent for
writing and the axi bus. Currently there would need to be a small gap between
the data streams.
2018-06-03 19:29:18 -07:00
Berin Martini
2caf74e6cd Use axis_gbox in axis_read_data
This replaces the axis_serializer module.
2018-06-03 18:42:13 -07:00
Berin Martini
efcdc99b2d Bug fix: processing consecutive streams of read data
The seriliser needs to be reset when there is leftover data, however, if the
module is processing multiple streams of data that have been read from memory
there might be valid data that has been popped from the data fifo. If that is
the case we must not reset the seriliser.
2018-06-03 18:33:46 -07:00
Berin Martini
8077945a6c Pass axi_rlast into axis_read_data
If we are going to use axis_gbox in axis_read_data it will need to 'axi_rlast'
signal if the system data width is larger then the axi data width.
2018-06-03 18:10:22 -07:00
Berin Martini
c64f7b7bfd Add axis_gbox module and testbench
The AXIS Gear Box will serializes or deserializes a stream of data depending of
the relative widths of the streams. Is only one register deep.

Serializes the 'up' data word into multiple smaller 'down' data words. The
module will stall when the dn_rdy flag deasserts.

Deserializes multiple 'up' flow bus data words into a single, larger 'down'
data words. Arranges them first to the right and moving left. If there is a
pause in the incoming 'up' stream the values already written into the larger
'down' word will stay until enough 'up' data has been sent in to complete the
'down' word unless a 'up_last' signal forces the down transfer. The module will
stall when the 'dn_rdy' flag deasserts.

This module will be used to replace the axis_(serializes|deserializes) modules
as this will allow the system stream to be larger then the AXI stream.
2018-06-03 18:01:49 -07:00
Berin Martini
06972f0dc2 Remove unused DONE state in axis_write_data.v 2018-06-03 17:15:13 -07:00
Berin Martini
aa846c09d3 Add configuration fifo in axis_write_data
This will allow for multiple config values to be queued in the axis_write_data
module for processing.
2018-06-03 17:07:43 -07:00
Berin Martini
a27bb62c7f Change axis_write_data FSM state IDLE->CONFIG
This state is waiting to be configured and thus the new state name is more
descriptive.
2018-06-03 16:47:05 -07:00
Berin Martini
d5a4f64d09 Add configuration fifo in axis_read_data
This will allow for multiple config values to be queued in the axis_read_data
module for processing.
2018-06-03 16:38:27 -07:00
Berin Martini
8ad1e51b36 Change axis_read_data FSM state IDLE->CONFIG
This state is waiting to be configured and thus the new state name is more
descriptive.
2018-06-03 16:26:30 -07:00
Berin Martini
463945324b move fifo in axis_read_data to accept AXI data
This way small reads will be able to complete without using back pressure.
2018-06-03 16:12:26 -07:00
Berin Martini
6ee19e21fd Add configuration fifo in axis_addr
This will allow for multiple config values to be queued in the axis_addr module
for processing.
2018-06-03 15:38:56 -07:00
Berin Martini
cdae1f897b Change axis_addr FSM state IDLE->CONFIG
This state is waiting to be configured and thus the new state name is more
descriptive.
2018-06-03 15:30:42 -07:00
Berin Martini
4ad550b31a Move some of the axis_addr assigns around module
Moves them closer to where they are used for readability.
2018-06-03 15:17:37 -07:00
Berin Martini
0d560dff11 Allow for axi addr width and cfg with to be different
Prevents width miss match warnings in systems that don't have the AXI address
width or the cfg data width being the same.
2018-06-03 14:57:42 -07:00
Berin Martini
05e0b292f2 Change CONFIG_* parameter to CFG_*
Shortens the parameter name without reducing the readability.
2018-06-03 14:49:01 -07:00
Berin Martini
1de6b65223 Add testbench for axis_loopback topfile
Doesn't do anything except to test for any warnings/errors etc. in the full
system.
2018-06-03 14:48:12 -07:00
Berin Martini
65a3a448fd Copy only files that are needed into IP hdl package
This involves parsing the topfile of the package (as determined by the name of
the package) and copying only the 'included' files. The code to do this was
taken from my 'cpvdep' script found at my github account.
2016-07-19 14:55:12 -07:00
Berin Martini
ed67396bde Rename variables in interface.c for clarity
This change makes a clear distention of the physical address and the user space
address for the memory array. It also scopes the variables to the file so they
will not be exported in the object file which can cause naming conflicts in
programs that use it.
2016-07-14 15:35:10 -07:00
Berin Martini
9c3c828b1f Update axis_serializer for 1-to-1 in/out data size
In this configuration the axis_serializer would just register and pass on the
input data down stream.
2016-05-30 22:02:29 -07:00
Berin Martini
2a392df7af Merge branch 'verilator-linter'
Using the Verilator linting tool a number of warnings were identified and
corrected in the 'axis' hdl code.
2016-05-30 21:58:39 -07:00
Berin Martini
611aaa8066 Augments of equal size for operator + for fifo_simple.v 2016-05-30 21:58:08 -07:00
Berin Martini
c77f0abac8 Update default parameters axis_(read|write)_data.v
This is to remove Verilator warnings due to invalid default parameter values.
2016-05-30 21:55:59 -07:00
Berin Martini
a72a9898fe Augments of equal size for operator + 2016-05-30 21:50:00 -07:00
Berin Martini
686c604d9a Augments of equal size for operator + 2016-05-30 21:49:19 -07:00
Berin Martini
bd9ed40ff0 Augments of equal size for operator + 2016-05-30 21:47:26 -07:00
Berin Martini
52726f3f0d Augments of equal size for operator + 2016-05-30 21:46:28 -07:00
Berin Martini
8984a29ed9 Ensure correct width during bus assignment 2016-05-30 20:13:19 -07:00
Berin Martini
f976f569ab Ensure correct width during bus assignment 2016-05-30 20:12:13 -07:00
Berin Martini
0c3c7599fb Ensure correct width during bus assignment 2016-05-30 20:08:39 -07:00
Berin Martini
aae41b52d1 Define variables before use in axis_write.v 2016-05-30 19:55:37 -07:00
Berin Martini
fae937bf52 Define variables before use in axis_read.v 2016-05-30 19:53:45 -07:00
Berin Martini
b05b6bd6d4 Use blocking assignment in non-clocked always block
Combinational logic shouldn't use the non-blocking assignment.
2016-05-30 19:48:30 -07:00
Berin Martini
1885150a4c Use blocking assignment in non-clocked always block
Combinational logic shouldn't use the non-blocking assignment.
2016-05-30 19:47:58 -07:00
Berin Martini
180d20067b Use blocking assignment in non-clocked always block
Combinational logic shouldn't use the non-blocking assignment.
2016-05-30 19:45:58 -07:00
Berin Martini
e1dd988185 Define burst_done before use in axi_addr.v 2016-05-30 19:45:16 -07:00
Berin Martini
d048db507b Update doc with latest version of Vivado (2015.4)
The project has been updated to use the latest version (as of writing) of
Vivado.
2016-03-17 19:27:48 -04:00
Berin Martini
34a5c422cf Merge branch 'package-project'
Update project to use Xilinx IP Packages and Vivado 2015.4 tools. Add project
for Zedboard, MicroZed and the ZC706.
2016-02-28 18:11:56 -05:00