The AXI4 Lite bus Xilinx uses addresses the bytes in the 32 bit data word.
Since the config registers used in by the Linux system only cares about the 32
bit registers the lower two address bits get ignored. These changes makes it
easier to integrate the module when using it in an IP Package.
Some projects will name the bitstream files a standard name and thus by
renaming them we can ensure that the bitstream files are easily identified
after syntheses.
This allows for the the 'pkg-module' script to have bash tab completion when
invoked in the repos root directory. Its the same as the 'sim-module' auto
completion in that it looks in the 'hdl' directory for module file names.
Invoking this script with a modules filename as argument will try and create a
Xilinx IP Package. Once crated the package is moved to a 'ip/ip_repo' directory
and can be used in a Vivado project.
The method of package creation is simple and for the most part automatic and
thus we assume that Xilinx naming conventions etc are observed.
IP Packages are going to be created using HDL files in the repo. These files
need to be moved into the package directory for use in the package. This change
ensure that the files are made available. Its not the best as it copies ALL
files into the package directory and not just the needed files.
The functionality of the axis_memory_offset function can be replicated by using
mem_alloc_state while at the same times provides a more powerful interface to
the memory allocation system.
The 1st argument passed to the new mem_alloc_state functions is a pointer to a
void pointer (start) whose value will be overwritten to be the start pointer of
the CMA memory area. The 2nd argument is a pointer to a unsigned int whose
values will be overwritten to be the current 'offset' from that start pointer
and thus represents how many bytes has been allocated.
This function takes as argument an offset indexed from zero and returns a usage
pointer corresponding to the offset from the start of the CMA region. Thus an
argument offset of zero would give the pointer to the start of the CMA region.
This change prepends the CROSS_COMPILE environmental variable to the compilers
definition. Thus adding the possibility of cross compiling when the cross
compiling tool chain has been setup correctly.
By explicitly pairing the clock running the interface with the interface
in Vivado it allows for better timing analysis and remove some 'CRITICAL
WARNINGS'.
The memory is addressable using the AXIS ports in 64 bit (8 byte) chunks. Thus
when allocating memory from CMA region, the start address needs to be 64 bit
aligned, not page aligned. This change will thus reduce the 'padding' at the
end of arrays and thus RAM.
This devicetree code is an altered version of the
'arch/arm/boot/dts/zynq-7000.dtsi' file found in the linux-xlnx Xilinx
repo, master branch commit (da2d296bb6b89f7bc7644f6b552b9766ac1c17d5).
The only thing that was added was the following axis node:-
```
axis: axis@43C00000 {
compatible = "xlnx,axis-1.00";
reg = < 0x43C00000 0x10000 >;
xlnx,num-mem = <0x1>;
xlnx,num-reg = <0x20>;
xlnx,s-axi-min-size = <0x1ff>;
xlnx,slv-awidth = <0x20>;
xlnx,slv-dwidth = <0x20>;
};
```
Similar functions could be constructed using calls to the already existing
functions, however, it seems more efficient to add them to the library in case
the application cannot optimizes external library calls.
