FPGA/zynq-axis
1
0
Fork 0
mirror of https://github.com/bmartini/zynq-axis.git synced 2024-09-05 19:19:27 +08:00
Code Issues Projects Releases Wiki Activity
117 Commits 2 Branches 0 Tags
Commit Graph

117 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Berin Martini
8ad1e51b36 Change axis_read_data FSM state IDLE->CONFIG 
This state is waiting to be configured and thus the new state name is more
descriptive.
 2018-06-03 16:26:30 -07:00
Berin Martini
463945324b move fifo in axis_read_data to accept AXI data 
This way small reads will be able to complete without using back pressure.
 2018-06-03 16:12:26 -07:00
Berin Martini
6ee19e21fd Add configuration fifo in axis_addr 
This will allow for multiple config values to be queued in the axis_addr module
for processing.
 2018-06-03 15:38:56 -07:00
Berin Martini
cdae1f897b Change axis_addr FSM state IDLE->CONFIG 
This state is waiting to be configured and thus the new state name is more
descriptive.
 2018-06-03 15:30:42 -07:00
Berin Martini
4ad550b31a Move some of the axis_addr assigns around module 
Moves them closer to where they are used for readability.
 2018-06-03 15:17:37 -07:00
Berin Martini
0d560dff11 Allow for axi addr width and cfg with to be different 
Prevents width miss match warnings in systems that don't have the AXI address
width or the cfg data width being the same.
 2018-06-03 14:57:42 -07:00
Berin Martini
05e0b292f2 Change CONFIG_* parameter to CFG_* 
Shortens the parameter name without reducing the readability.
 2018-06-03 14:49:01 -07:00
Berin Martini
1de6b65223 Add testbench for axis_loopback topfile 
Doesn't do anything except to test for any warnings/errors etc. in the full
system.
 2018-06-03 14:48:12 -07:00
Berin Martini
65a3a448fd Copy only files that are needed into IP hdl package 
This involves parsing the topfile of the package (as determined by the name of
the package) and copying only the 'included' files. The code to do this was
taken from my 'cpvdep' script found at my github account.
 2016-07-19 14:55:12 -07:00
Berin Martini
ed67396bde Rename variables in interface.c for clarity 
This change makes a clear distention of the physical address and the user space
address for the memory array. It also scopes the variables to the file so they
will not be exported in the object file which can cause naming conflicts in
programs that use it.
 2016-07-14 15:35:10 -07:00
Berin Martini
9c3c828b1f Update axis_serializer for 1-to-1 in/out data size 
In this configuration the axis_serializer would just register and pass on the
input data down stream.
 2016-05-30 22:02:29 -07:00
Berin Martini
2a392df7af Merge branch 'verilator-linter' 
Using the Verilator linting tool a number of warnings were identified and
corrected in the 'axis' hdl code.
 2016-05-30 21:58:39 -07:00
Berin Martini
611aaa8066 Augments of equal size for operator + for fifo_simple.v 2016-05-30 21:58:08 -07:00
Berin Martini
c77f0abac8 Update default parameters axis_(read|write)_data.v 
This is to remove Verilator warnings due to invalid default parameter values.
 2016-05-30 21:55:59 -07:00
Berin Martini
a72a9898fe Augments of equal size for operator + 2016-05-30 21:50:00 -07:00
Berin Martini
686c604d9a Augments of equal size for operator + 2016-05-30 21:49:19 -07:00
Berin Martini
bd9ed40ff0 Augments of equal size for operator + 2016-05-30 21:47:26 -07:00
Berin Martini
52726f3f0d Augments of equal size for operator + 2016-05-30 21:46:28 -07:00
Berin Martini
8984a29ed9 Ensure correct width during bus assignment 2016-05-30 20:13:19 -07:00
Berin Martini
f976f569ab Ensure correct width during bus assignment 2016-05-30 20:12:13 -07:00
Berin Martini
0c3c7599fb Ensure correct width during bus assignment 2016-05-30 20:08:39 -07:00
Berin Martini
aae41b52d1 Define variables before use in axis_write.v 2016-05-30 19:55:37 -07:00
Berin Martini
fae937bf52 Define variables before use in axis_read.v 2016-05-30 19:53:45 -07:00
Berin Martini
b05b6bd6d4 Use blocking assignment in non-clocked always block 
Combinational logic shouldn't use the non-blocking assignment.
 2016-05-30 19:48:30 -07:00
Berin Martini
1885150a4c Use blocking assignment in non-clocked always block 
Combinational logic shouldn't use the non-blocking assignment.
 2016-05-30 19:47:58 -07:00
Berin Martini
180d20067b Use blocking assignment in non-clocked always block 
Combinational logic shouldn't use the non-blocking assignment.
 2016-05-30 19:45:58 -07:00
Berin Martini
e1dd988185 Define burst_done before use in axi_addr.v 2016-05-30 19:45:16 -07:00
Berin Martini
d048db507b Update doc with latest version of Vivado (2015.4) 
The project has been updated to use the latest version (as of writing) of
Vivado.
 2016-03-17 19:27:48 -04:00
Berin Martini
34a5c422cf Merge branch 'package-project' 
Update project to use Xilinx IP Packages and Vivado 2015.4 tools. Add project
for Zedboard, MicroZed and the ZC706.
 2016-02-28 18:11:56 -05:00
Berin Martini
7f79a64983 Remove old 2014.2 Xilinx projects 
This project has been superseded by the new loopback IP Package project.
 2016-02-28 18:06:43 -05:00
Berin Martini
45487e1b98 Lower clk rate of Zedboard to meet timing 
The Zedboard system could not meet timing at 250 MHz so the clock has been
reduced to 142 MHz.
 2016-02-28 17:56:38 -05:00
Berin Martini
d4fcec367d Add MicroZed project that uses IP Packages 
This project is generated from scratch using a TCL script and relies on all
code that is to be added being wrapped in an IP Package.
 2016-02-28 17:11:24 -05:00
Berin Martini
90434213c4 Add Zedboard project that uses IP Packages 
This project is generated from scratch using a TCL script and relies on all
code that is to be added being wrapped in an IP Package.
 2016-02-28 15:53:37 -05:00
Berin Martini
295d3a1ea6 Add ZC706 project that uses IP Packages 
This project is generated from scratch using a TCL script and relies on all
code that is to be added being wrapped in an IP Package.
 2016-02-28 15:12:16 -05:00
Berin Martini
9c83c4695f Add axis_loopback IP Package generated by pkg-module 
This package contains the configuration files but not the code. The code is
added to the IP Package directory with the 'syn-proj-prep' script.
 2016-02-28 15:12:15 -05:00
Berin Martini
78cbf0d955 Add IP Package top file for axis loopback code 
This module is a rewrite of the zedboard_axis module but done so such that it
can be used to automatically generate an IP Package.
 2016-02-28 14:50:45 -05:00
Berin Martini
6c481f894b Update axi4lite_cfg parameters for standard compatibility 
The AXI4 Lite bus Xilinx uses addresses the bytes in the 32 bit data word.
Since the config registers used in by the Linux system only cares about the 32
bit registers the lower two address bits get ignored. These changes makes it
easier to integrate the module when using it in an IP Package.
 2016-02-27 18:38:40 -05:00
Berin Martini
0b5fc2534e Merge branch 'update-scripts' 
Update bash helper scripts. With these changes more Zynq boards are supported
and the ability to create simple package's has been added.
 2016-02-27 16:37:39 -05:00
Berin Martini
e619e0289a pkg-module to create packages for any supported platform 
The new option is passed to the make-proj.sh script and thus any platform that
script supports can be used by the 'pkg-module' script.
 2016-02-27 16:35:36 -05:00
Berin Martini
c30562deec Rename bitstream file to projects name after synthesizes 
Some projects will name the bitstream files a standard name and thus by
renaming them we can ensure that the bitstream files are easily identified
after syntheses.
 2016-02-27 16:23:48 -05:00
Berin Martini
8c22d67eec Update bash script completion definitions 
This allows for the the 'pkg-module' script to have bash tab completion when
invoked in the repos root directory. Its the same as the 'sim-module' auto
completion in that it looks in the 'hdl' directory for module file names.
 2016-02-27 16:19:50 -05:00
Berin Martini
91a3256ae6 Add script to automate simple IP Package creation 
Invoking this script with a modules filename as argument will try and create a
Xilinx IP Package. Once crated the package is moved to a 'ip/ip_repo' directory
and can be used in a Vivado project.

The method of package creation is simple and for the most part automatic and
thus we assume that Xilinx naming conventions etc are observed.
 2016-02-27 16:18:06 -05:00
Berin Martini
a2008f71b8 Prep user IP Packages for use in synth 
IP Packages are going to be created using HDL files in the repo. These files
need to be moved into the package directory for use in the package. This change
ensure that the files are made available. Its not the best as it copies ALL
files into the package directory and not just the needed files.
 2016-02-27 15:52:14 -05:00
Berin Martini
11c556b29b Update make-proj to support more FPGA platforms 
Be able to select more Zynq boards as a project target.
 2016-02-26 23:36:34 -05:00
Berin Martini
a53998a69d Replace axis_memory_offset function with mem_alloc_state 
The functionality of the axis_memory_offset function can be replicated by using
mem_alloc_state while at the same times provides a more powerful interface to
the memory allocation system.

The 1st argument passed to the new mem_alloc_state functions is a pointer to a
void pointer (start) whose value will be overwritten to be the start pointer of
the CMA memory area. The 2nd argument is a pointer to a unsigned int whose
values will be overwritten to be the current 'offset' from that start pointer
and thus represents how many bytes has been allocated.
 2015-10-29 14:42:25 +00:00
Berin Martini
586efff1a9 White space correction for interface.c 2015-10-29 02:12:29 +00:00
Berin Martini
dafc85637a New function in library 'axis_memory_offset' 
This function takes as argument an offset indexed from zero and returns a usage
pointer corresponding to the offset from the start of the CMA region. Thus an
argument offset of zero would give the pointer to the start of the CMA region.
 2015-10-29 02:12:29 +00:00
Berin Martini
a0c2bde576 Increase the CMA region to 126MB from 63MB 
This gives more room to play with in the FPGA project.
 2015-10-29 00:58:33 +00:00
Berin Martini
0ab669e7c0 Remove assert for AXIS port max number 
It is possible to have more then 4 AXIS modules if 2 or more are connected to
the same AXI Interconnect.
 2015-09-24 20:05:15 +00:00
Berin Martini
0bb945c62d Add doc on building u-boot, kernel and devicetree 
Some bare bones instructions on how to compile the above list of components.
 2015-09-23 01:22:45 -04:00