Similar functions could be constructed using calls to the already existing
functions, however, it seems more efficient to add them to the library in case
the application cannot optimizes external library calls.
Arrays that will be used to pass data between the host and fpga need to be page
aligned and be slices of the DMA array the driver has reserved. These new
functions allocate slices from the DMA array and ensures that the starting
address is page aligned.
The driver sets ups a DMA contiguous array that will be used as a memory area
to share data between the PS and PL. The library memory maps this DMA array to
make it available to the host applications. The array is cache coherent and
thus data written or read from it bypass the CPU cache and read/write directly
from main memory. This ensures that the data is always the same between the
host and fpga but at a cost of long data accesses from the host CPU.
