By explicitly pairing the clock running the interface with the interface
in Vivado it allows for better timing analysis and remove some 'CRITICAL
WARNINGS'.
Under "Design Sources" right click the "system_i" board design. From the
menu select "Create HDL Wrapper" to generate the system top file for the
project.
Within the "Block Diagram" areas "Diagram" tab select "Add IP". From the list
that appears select "AXI Interconnect".
Double click on the new AXI Interconnect block to customise it. Reduce
the number of master ports to 1.
In the right hand "Signals" tab drag all "Unconnected Clocks" to the
ps7/FCLK_CLK0 Clock Domain (there should be a few).
Connect the AXI Interconnect resets to the ps7 the FCLK_RESET0_N reset.
Click on the "S00_AXI" pin in the new AXI Interconnect and use "Connection
Mode" to connect it to the ps7 GP0 port.
Right click "M00_AXI" pin in the new AXI Interconnect and select "Make
External" from the drop down menu.
Double click the newly created "M00_AXI" external port to customise. Set
protocol as "AXI4Lite".
In "Address Editor" tab, right click "ps7"->"Data"->"Unmapped
Slaves"->"M00_AXI" and select "Assign Address".
In the "Block Design" "Diagram" tab right click and select "Create Port..."
from the drop down menu. In the "Create Port" dialog box name the port
"axi_clk", set its direction to "Output" and type to "Clock".
Click on the FCLK_CLK0 pin on the ps7 block and use the "Connection Mode" to
connect the FCLK_CLK0" to the new "axi_clk" port.
Create another port named "axi_rst_n", direction "Output" and type "Reset".
Click on the "axi_rst_n" port and use the "Connection Mode" to connect it to
the reset tree being used by the axi_dma module (not to FCLK_RESET0_N".
Open the project in the Vivado GUI. In the left hand "Flow Navigator" area
select the "Create Block Design". When prompted for a name, use "system".
A green bar appears at the top of the "Block Design" areas "Diagram" tab
prompting to "Add IP". Select to add ip and from the list that appear select
"ZYNQ7 Processing System" (2nd from the end). Click on the processing systems
block and rename to "ps7" from the "Block Properties". The green bar will now
be prompting you to run "Block Automation", select this and the ps7 will be
reconfigured with the Zedboard defaults.
Running the script will create an empty Xilinx project directory.
Optionally takes the project name as an argument. When no project name
is passed it, the script defaults to 'tmp'.
