FPGA/zynq-axis
1
0
Fork 0
mirror of https://github.com/bmartini/zynq-axis.git synced 2024-09-05 19:19:27 +08:00
Code Issues Projects Releases Wiki Activity
104 Commits 2 Branches 0 Tags
Commit Graph

35 Commits

Author SHA1 Message Date
Berin Martini
c77f0abac8 Update default parameters axis_(read|write)_data.v 
This is to remove Verilator warnings due to invalid default parameter values.
 2016-05-30 21:55:59 -07:00
Berin Martini
a72a9898fe Augments of equal size for operator + 2016-05-30 21:50:00 -07:00
Berin Martini
686c604d9a Augments of equal size for operator + 2016-05-30 21:49:19 -07:00
Berin Martini
bd9ed40ff0 Augments of equal size for operator + 2016-05-30 21:47:26 -07:00
Berin Martini
52726f3f0d Augments of equal size for operator + 2016-05-30 21:46:28 -07:00
Berin Martini
8984a29ed9 Ensure correct width during bus assignment 2016-05-30 20:13:19 -07:00
Berin Martini
f976f569ab Ensure correct width during bus assignment 2016-05-30 20:12:13 -07:00
Berin Martini
0c3c7599fb Ensure correct width during bus assignment 2016-05-30 20:08:39 -07:00
Berin Martini
aae41b52d1 Define variables before use in axis_write.v 2016-05-30 19:55:37 -07:00
Berin Martini
fae937bf52 Define variables before use in axis_read.v 2016-05-30 19:53:45 -07:00
Berin Martini
b05b6bd6d4 Use blocking assignment in non-clocked always block 
Combinational logic shouldn't use the non-blocking assignment.
 2016-05-30 19:48:30 -07:00
Berin Martini
1885150a4c Use blocking assignment in non-clocked always block 
Combinational logic shouldn't use the non-blocking assignment.
 2016-05-30 19:47:58 -07:00
Berin Martini
180d20067b Use blocking assignment in non-clocked always block 
Combinational logic shouldn't use the non-blocking assignment.
 2016-05-30 19:45:58 -07:00
Berin Martini
e1dd988185 Define burst_done before use in axi_addr.v 2016-05-30 19:45:16 -07:00
Berin Martini
7f79a64983 Remove old 2014.2 Xilinx projects 
This project has been superseded by the new loopback IP Package project.
 2016-02-28 18:06:43 -05:00
Berin Martini
78cbf0d955 Add IP Package top file for axis loopback code 
This module is a rewrite of the zedboard_axis module but done so such that it
can be used to automatically generate an IP Package.
 2016-02-28 14:50:45 -05:00
Berin Martini
6c481f894b Update axi4lite_cfg parameters for standard compatibility 
The AXI4 Lite bus Xilinx uses addresses the bytes in the 32 bit data word.
Since the config registers used in by the Linux system only cares about the 32
bit registers the lower two address bits get ignored. These changes makes it
easier to integrate the module when using it in an IP Package.
 2016-02-27 18:38:40 -05:00
Berin Martini
7636ed6277 Bug fix: axis_addr testbench 
Had not updated it to remove the address ID tag.
 2015-01-11 13:12:20 -05:00
Berin Martini
0ff47fafb6 Bug fix: axis_write testbench 
Had not updated it to remove the address ID tag.
 2015-01-11 13:10:29 -05:00
Berin Martini
65d8079cda Terminate axi_rresp & axi_rlast in axis.v 
Since these signals are never used, they do not need to be propagated
past the axis.v module.
 2015-01-11 13:04:29 -05:00
Berin Martini
48a322ba60 Bug fix: axis_read testbench 
Had not updated it to remove the address ID tag.
 2015-01-11 12:54:29 -05:00
Berin Martini
76537507eb Bug fix: AXI transaction ID usage and generation 
Because the axis modules are minimalist, it assumes that all
transactions are performed without error and that transaction processing
is performed in-order. Thus the transaction IDs can safely be set to
zero. Doing so also fixes a bug in the write path that had prevented
multiple burst of data being sent. This was due to the fact that the
write data burst ID needs to have the same ID as the write address. But
the write address module was incrementing the ID while the write data ID
was not being set at all.
 2015-01-08 11:39:07 -05:00
Berin Martini
9ee0ce64ee Indicates burst size in bytes of each transfer 
This signal encoding is determined using the axi data width parameter as
per Section 4.3 of the AXI Protocol Specification (v1.0).
 2015-01-08 10:58:20 -05:00
Berin Martini
852e507af2 Bug fix: axis burst size wr/rd values 
By setting the values as larger then they should be the data was over
writing itself in memory.
 2015-01-07 14:13:29 -05:00
Berin Martini
19390ccca8 Bug fix: axis port list variable sizes 
There was a miss-match that was giving warnings but as the variables
were not used there were no errors.
 2015-01-07 12:53:31 -05:00
Berin Martini
d1db9ce3b3 Parametrize address step size in axis_addr 
Had been assuming that the AXI word width was 256 bits and thus the
address would step 32 bytes * burst_length.
 2015-01-07 11:43:56 -05:00
Berin Martini
f435570745 Connect axis read to cfg reg 
This *should* allow for the axis port to read data the the memory and
transmit the read value to the host via the cfg bus.
 2015-01-06 17:13:34 -05:00
Berin Martini
624e40c03e Connect axis wr port to cfg registers 
For debug purposes the axis is connected to the cfg registers so data
patterns can be written to the system memory.
 2015-01-04 19:36:02 -05:00
Berin Martini
04f7ccd2a2 Instantiate axis module & attache to HP0 
Setup as a simple loopback system.
 2015-01-03 05:21:13 -05:00
Berin Martini
e881359f25 Connect HP0 to zedboard top file 
Currently not doing anything.
 2015-01-02 20:23:57 -05:00
Berin Martini
d9d8540a6c Add axis and related modules 
The axis module instantiates the AXI read and write path modules. It
performs a simple stream over the AXI port interface with no error
checking. It is configured by first addressing the module and then
sending a physical memory address and the number of streaming words to
be written.

The streaming interface is not exactly like the Xilinx stream interface
in that the data is always valid when the valid flag is high, the ready
flag being low does not invalidate the data but is used to signal up
stream to stop sending data. Down stream has a buffer able to absorb to
incoming valid data until such time as up stream stop sending.
 2015-01-02 17:32:39 -05:00
Berin Martini
ac07bb9114 Add synchronous FIFO & testbench 
A simple FIFO, with synchronous clock for both the pop and push ports.
 2015-01-02 17:32:39 -05:00
Berin Martini
8a62d2ba82 Bug fix: axi4lite_cfg port list definition 2015-01-02 17:31:35 -05:00
Berin Martini
c9bef3cda3 Add module to decode AXI4 Lite bus 
The module copies the protocol responses/handling from a Xilinx example.
As such it works but to my eye does not look very efficient.
 2015-01-01 21:42:38 -05:00
Berin Martini
d5a798ad41 Create working top file based on system_wrapper.v 
The project now generates a bitstream file but only from the build directory
created by the syn-proj-prep script.
 2014-12-31 20:03:44 -05:00