Under "Design Sources" right click the "system_i" board design. From the
menu select "Create HDL Wrapper" to generate the system top file for the
project.
Within the "Block Diagram" areas "Diagram" tab select "Add IP". From the list
that appears select "AXI Interconnect".
Double click on the new AXI Interconnect block to customise it. Reduce
the number of master ports to 1.
In the right hand "Signals" tab drag all "Unconnected Clocks" to the
ps7/FCLK_CLK0 Clock Domain (there should be a few).
Connect the AXI Interconnect resets to the ps7 the FCLK_RESET0_N reset.
Click on the "S00_AXI" pin in the new AXI Interconnect and use "Connection
Mode" to connect it to the ps7 GP0 port.
Right click "M00_AXI" pin in the new AXI Interconnect and select "Make
External" from the drop down menu.
Double click the newly created "M00_AXI" external port to customise. Set
protocol as "AXI4Lite".
In "Address Editor" tab, right click "ps7"->"Data"->"Unmapped
Slaves"->"M00_AXI" and select "Assign Address".
In the "Block Design" "Diagram" tab right click and select "Create Port..."
from the drop down menu. In the "Create Port" dialog box name the port
"axi_clk", set its direction to "Output" and type to "Clock".
Click on the FCLK_CLK0 pin on the ps7 block and use the "Connection Mode" to
connect the FCLK_CLK0" to the new "axi_clk" port.
Create another port named "axi_rst_n", direction "Output" and type "Reset".
Click on the "axi_rst_n" port and use the "Connection Mode" to connect it to
the reset tree being used by the axi_dma module (not to FCLK_RESET0_N".
Open the project in the Vivado GUI. In the left hand "Flow Navigator" area
select the "Create Block Design". When prompted for a name, use "system".
A green bar appears at the top of the "Block Design" areas "Diagram" tab
prompting to "Add IP". Select to add ip and from the list that appear select
"ZYNQ7 Processing System" (2nd from the end). Click on the processing systems
block and rename to "ps7" from the "Block Properties". The green bar will now
be prompting you to run "Block Automation", select this and the ps7 will be
reconfigured with the Zedboard defaults.
Script will copy source code, 3rd party IP and Xilinx project directory
into a scratch directory which it also creates. Script can be invoked
using the following option.
-c Copy Verilog source code and 3rd party IP to an already existing
syn/scratch/ directory. Perform no other functions.
-h Print this help info.
-l Symbolically link project files into the scratch dir instead of
copying them. Any changes to these file during building will thus be
propagated back into the repo.
-L Symbolically link project directory into the scratch instead of
copying it. This takes precedents over the '-l'.
Running the script will create an empty Xilinx project directory.
Optionally takes the project name as an argument. When no project name
is passed it, the script defaults to 'tmp'.
This number can then be used to release the I/O memory regions that have
been requested in the probe function. This will thus allow for other
types of mappable memory to be exposed by the driver.
Use devm_kzalloc function to simplify driver error path. This function
is a per driver/device memory management function that will auto free
any memory when driver is released.
Currently do not have interrupts defined in hardware and thus they are
not defined in the devicetree. Since the code/kernel thinks there should
be interrupts defined in the devicetree node it throws an error when
there is not. There should be a better way to do this but this works for
now.
This rules file gets copied into the udev system directory so that when
the axis uio driver is loaded a device file is created that users
applications can access.
sudo cp util/80-axis.rules /etc/udev/rules.d/
