FPGA/zynq-axis
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zynq-axis/hdl/axis
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Berin Martini 12487c3e6e Move str counter in axis_write_data after data fifo 
This will for a continuous stream of data from the user system to be sent for
writing and the axi bus. Currently there would need to be a small gap between
the data streams.
2018-06-03 19:29:18 -07:00
..
axis_addr_tb.v
Add configuration fifo in axis_addr
2018-06-03 15:38:56 -07:00
axis_addr.v
Add configuration fifo in axis_addr
2018-06-03 15:38:56 -07:00
axis_deserializer_tb.v
Add axis and related modules
2015-01-02 17:32:39 -05:00
axis_deserializer.v
Ensure correct width during bus assignment
2016-05-30 20:13:19 -07:00
axis_gbox_tb.v
Add axis_gbox module and testbench
2018-06-03 18:01:49 -07:00
axis_gbox.v
Add axis_gbox module and testbench
2018-06-03 18:01:49 -07:00
axis_read_data_tb.v
Use axis_gbox in axis_read_data
2018-06-03 18:42:13 -07:00
axis_read_data.v
Use axis_gbox in axis_read_data
2018-06-03 18:42:13 -07:00
axis_read_tb.v
Change CONFIG_* parameter to CFG_*
2018-06-03 14:49:01 -07:00
axis_read.v
Use axis_gbox in axis_read_data
2018-06-03 18:42:13 -07:00
axis_serializer_tb.v
Add axis and related modules
2015-01-02 17:32:39 -05:00
axis_serializer.v
Update axis_serializer for 1-to-1 in/out data size
2016-05-30 22:02:29 -07:00
axis_write_data_tb.v
Add configuration fifo in axis_write_data
2018-06-03 17:07:43 -07:00
axis_write_data.v
Move str counter in axis_write_data after data fifo
2018-06-03 19:29:18 -07:00
axis_write_tb.v
Change CONFIG_* parameter to CFG_*
2018-06-03 14:49:01 -07:00
axis_write.v
Add configuration fifo in axis_write_data
2018-06-03 17:07:43 -07:00
axis.v
Pass axi_rlast into axis_read_data
2018-06-03 18:10:22 -07:00