zynq-axis

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Berin Martini 2f10fb29d2 Memory map CMA array from driver

The driver sets ups a DMA contiguous array that will be used as a memory area
to share data between the PS and PL. The library memory maps this DMA array to
make it available to the host applications. The array is cache coherent and
thus data written or read from it bypass the CPU cache and read/write directly
from main memory. This ensures that the data is always the same between the
host and fpga but at a cost of long data accesses from the host CPU.

2015-01-09 13:07:51 -05:00

app

Update read-memory application

2015-01-08 14:46:19 -05:00

dev

Allocate CMA memory on driver probe

2014-12-31 11:15:11 -05:00

hdl

Bug fix: AXI transaction ID usage and generation

2015-01-08 11:39:07 -05:00

lib

Memory map CMA array from driver