Berin Martini 55319e7d19 Associate axi_clk to AXI bus interfaces ...

By explicitly pairing the clock running the interface with the interface
in Vivado it allows for better timing analysis and remove some 'CRITICAL
WARNINGS'.

2015-02-09 14:21:20 -05:00

..

project-zedboard_axis

Associate axi_clk to AXI bus interfaces

2015-02-09 14:21:20 -05:00

make-proj.sh

Add bash script to prepare an empty Xilinx project

2014-12-31 15:34:29 -05:00