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https://github.com/bmartini/zynq-axis.git
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d9d8540a6c
The axis module instantiates the AXI read and write path modules. It performs a simple stream over the AXI port interface with no error checking. It is configured by first addressing the module and then sending a physical memory address and the number of streaming words to be written. The streaming interface is not exactly like the Xilinx stream interface in that the data is always valid when the valid flag is high, the ready flag being low does not invalidate the data but is used to signal up stream to stop sending data. Down stream has a buffer able to absorb to incoming valid data until such time as up stream stop sending.
244 lines
4.6 KiB
Verilog
244 lines
4.6 KiB
Verilog
/**
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* Testbench for:
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* axis_serializer
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*
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* Created:
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* Fri Nov 7 11:49:55 EST 2014
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*
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* Author:
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* Berin Martini (berin.martini@gmail.com)
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*/
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`timescale 1ns/10ps
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`define TB_VERBOSE
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//`define VERBOSE
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`include "axis_serializer.v"
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module axis_serializer_tb;
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/**
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* Clock and control functions
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*/
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// Generate a clk
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reg clk;
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always #1 clk = !clk;
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// End of simulation event definition
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event end_trigger;
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always @(end_trigger) $finish;
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`ifdef TB_VERBOSE
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// Display header information
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initial #1 display_header();
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always @(end_trigger) display_header();
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// And strobe signals at each clk
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always @(posedge clk) display_signals();
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`endif
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// initial begin
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// $dumpfile("result.vcd"); // Waveform file
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// $dumpvars;
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// end
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/**
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* Local parameters
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*/
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localparam DATA_NB = 3;
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localparam DATA_WIDTH = 8;
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localparam STREAM_LENGTH = 256;
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`ifdef TB_VERBOSE
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initial begin
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$display("Testbench for unit 'axis_serializer' data width: %d, nb: %d",
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DATA_WIDTH, DATA_NB);
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end
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`endif
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/**
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* signals, registers and wires
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*/
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reg rst;
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reg [DATA_NB*DATA_WIDTH-1:0] up_data;
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wire up_valid;
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wire up_ready;
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wire [DATA_WIDTH-1:0] down_data;
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wire down_valid;
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reg down_ready;
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reg [DATA_WIDTH-1:0] stream [0:STREAM_LENGTH-1];
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integer cnt;
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/**
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* Unit under test
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*/
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axis_serializer #(
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.DATA_NB (DATA_NB),
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.DATA_WIDTH (DATA_WIDTH))
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uut (
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.clk (clk),
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.rst (rst),
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.up_data (up_data),
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.up_valid (up_valid),
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.up_ready (up_ready),
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.down_data (down_data),
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.down_valid (down_valid),
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.down_ready (down_ready)
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);
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/**
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* Wave form display
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*/
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task display_signals;
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$display(
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"%d\t%d",
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$time, rst,
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"\tu2: %d\tu1: %d\tu0: %d",
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up_data[2*DATA_WIDTH+:DATA_WIDTH],
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up_data[1*DATA_WIDTH+:DATA_WIDTH],
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up_data[0*DATA_WIDTH+:DATA_WIDTH],
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"\tv %b\tr %b",
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up_valid,
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up_ready,
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"\t%d\t%b\t%b",
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down_data,
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down_valid,
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down_ready,
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"\t%b",
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uut.token,
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"\t%x\t%b",
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uut.serial_data,
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uut.serial_valid,
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);
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endtask // display_signals
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task display_header;
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$display(
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"\t\ttime\trst",
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"\tu2_d",
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"\tu1_d",
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"\tu0_d",
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"\tu_v",
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"\tu_r",
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"\td_d",
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"\td_v",
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"\td_r",
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);
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endtask
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/**
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* Testbench program
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*/
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//assign up_valid = up_ready;
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assign up_valid = 1'b1;
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always @(posedge clk)
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if (up_ready & up_valid) begin
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cnt <= cnt + 1;
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end
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always @(posedge clk)
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up_data <= {stream[cnt]+4'd2, stream[cnt]+4'd1, stream[cnt]};
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initial begin
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// init values
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clk = 0;
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rst = 0;
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down_ready = 'b0;
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cnt = 0;
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repeat (STREAM_LENGTH) begin
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stream[cnt] = (DATA_NB*cnt)+1;
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cnt = cnt + 1;
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end
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cnt = 0;
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//end init
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`ifdef TB_VERBOSE
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$display("RESET");
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`endif
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repeat(6) @(negedge clk);
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rst <= 1'b1;
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repeat(6) @(negedge clk);
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rst <= 1'b0;
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repeat(6) @(negedge clk);
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`ifdef TB_VERBOSE
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$display("test continuous ready");
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`endif
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@(negedge clk);
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down_ready <= 1'b1;
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repeat(20) @(negedge clk);
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down_ready <= 1'b0;
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repeat(10) @(negedge clk);
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`ifdef TB_VERBOSE
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$display("test non-continuous ready");
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`endif
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down_ready <= 1'b1;
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repeat(20) @(negedge clk);
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down_ready <= 1'b0;
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@(negedge clk);
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down_ready <= 1'b1;
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repeat(5) @(negedge clk);
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down_ready <= 1'b0;
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repeat(5) @(negedge clk);
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down_ready <= 1'b1;
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repeat(5) @(negedge clk);
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down_ready <= 1'b0;
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repeat(10) @(negedge clk);
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down_ready <= 1'b1;
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@(negedge clk);
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down_ready <= 1'b0;
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@(negedge clk);
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down_ready <= 1'b1;
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@(negedge clk);
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down_ready <= 1'b0;
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repeat(10) @(negedge clk);
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`ifdef TB_VERBOSE
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$display("END");
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`endif
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-> end_trigger;
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end
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endmodule
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