mirror of
https://github.com/bmartini/zynq-axis.git
synced 2024-09-05 19:19:27 +08:00
437 lines
8.9 KiB
Verilog
437 lines
8.9 KiB
Verilog
/**
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* Testbench:
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* axis_write
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*
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* Created:
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* Tue Nov 4 22:17:15 EST 2014
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*
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* Author:
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* Berin Martini (berin.martini@gmail.com)
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*/
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`timescale 1ns/10ps
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`define TB_VERBOSE
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//`define VERBOSE
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`include "axis_write.v"
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module axis_write_tb;
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/**
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* Clock and control functions
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*/
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// Generate a clk
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reg clk;
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always #1 clk = !clk;
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// End of simulation event definition
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event end_trigger;
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always @(end_trigger) $finish;
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`ifdef TB_VERBOSE
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// Display header information
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initial #1 display_header();
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always @(end_trigger) display_header();
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// And strobe signals at each clk
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always @(posedge clk) display_signals();
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`endif
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// initial begin
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// $dumpfile("result.vcd"); // Waveform file
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// $dumpvars;
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// end
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/**
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* Local parameters
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*/
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localparam STREAM_LENGTH = (256*8*2)-4;
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localparam BUF_AWIDTH = 4;
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localparam CONFIG_ID = 1;
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localparam CONFIG_ADDR = 23;
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localparam CONFIG_DATA = 24;
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localparam CONFIG_AWIDTH = 5;
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localparam CONFIG_DWIDTH = 32;
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localparam AXI_LEN_WIDTH = 2;
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localparam AXI_ADDR_WIDTH = 32;
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localparam AXI_DATA_WIDTH = 256;
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localparam DATA_WIDTH = 32;
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`ifdef TB_VERBOSE
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initial $display("Testbench for unit 'axis_write'");
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`endif
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/**
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* signals, registers and wires
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*/
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reg rst;
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reg [CONFIG_AWIDTH-1:0] cfg_addr;
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reg [CONFIG_DWIDTH-1:0] cfg_data;
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reg cfg_valid;
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reg axi_awready;
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wire [AXI_ADDR_WIDTH-1:0] axi_awaddr;
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wire [AXI_LEN_WIDTH-1:0] axi_awlen;
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wire axi_awvalid;
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wire axi_wlast;
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wire [AXI_DATA_WIDTH-1:0] axi_wdata;
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wire axi_wvalid;
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reg axi_wready;
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reg [DATA_WIDTH-1:0] data;
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reg valid;
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wire ready;
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/**
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* Unit under test
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*/
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axis_write #(
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.BUF_AWIDTH (BUF_AWIDTH),
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.CONFIG_ID (CONFIG_ID),
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.CONFIG_ADDR (CONFIG_ADDR),
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.CONFIG_DATA (CONFIG_DATA),
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.CONFIG_AWIDTH (CONFIG_AWIDTH),
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.CONFIG_DWIDTH (CONFIG_DWIDTH),
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.AXI_LEN_WIDTH (AXI_LEN_WIDTH),
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.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.DATA_WIDTH (DATA_WIDTH))
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uut (
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.clk (clk),
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.rst (rst),
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.cfg_addr (cfg_addr),
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.cfg_data (cfg_data),
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.cfg_valid (cfg_valid),
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.axi_awready (axi_awready),
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.axi_awaddr (axi_awaddr),
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.axi_awlen (axi_awlen),
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.axi_awvalid (axi_awvalid),
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.axi_wlast (axi_wlast),
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.axi_wdata (axi_wdata),
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.axi_wvalid (axi_wvalid),
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.axi_wready (axi_wready),
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.data (data),
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.valid (valid),
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.ready (ready)
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);
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/**
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* Wave form display
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*/
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task display_signals;
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$display(
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"%d\t%d",
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$time, rst,
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"\t%d\t%d\t%b",
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cfg_addr,
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cfg_data,
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cfg_valid,
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"\t%d\t%d\t%b\t%b",
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axi_awaddr,
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axi_awlen,
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axi_awvalid,
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axi_awready,
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"\t%x\t%b\t%b\t%b",
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axi_wdata,
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axi_wvalid,
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axi_wready,
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axi_wlast,
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"\t%d\t%b\t%b",
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data,
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valid,
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ready,
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"\t%b",
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uut.c_state,
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"\t%b",
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uut.axis_addr_.state,
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);
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endtask // display_signals
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task display_header;
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$display(
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"\t\ttime\trst",
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"\tc_a",
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"\t\tc_d",
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"\tc_v",
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"\t\taw_a",
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"\taw_l",
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"\taw_v",
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"\taw_r",
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"\t\t\t\t\t\tw_d",
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"\t\t\t\tw_v",
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"\tw_r",
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"\tw_l",
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"\t\ts_d",
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"\ts_v",
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"\tm_r",
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);
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endtask
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/**
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* Testbench program
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*/
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initial begin
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// init values
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clk = 0;
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rst = 0;
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cfg_addr = 'b0;
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cfg_data = 'b0;
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cfg_valid = 'b0;
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axi_awready = 'b0;
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axi_wready = 'b0;
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data = 'b0;
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valid = 'b0;
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//end init
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`ifdef TB_VERBOSE
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$display("RESET");
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`endif
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repeat(6) @(negedge clk);
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rst <= 1'b1;
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repeat(6) @(negedge clk);
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rst <= 1'b0;
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@(negedge clk);
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`ifdef TB_VERBOSE
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$display("send config id, start address and length");
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`endif
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repeat(5) @(negedge clk);
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cfg_addr <= CONFIG_ADDR;
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cfg_data <= CONFIG_ID;
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cfg_valid <= 1'b1;
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@(negedge clk)
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cfg_addr <= 'b0;
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cfg_data <= 'b0;
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cfg_valid <= 1'b0;
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repeat(5) @(negedge clk);
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cfg_addr <= CONFIG_DATA;
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cfg_data <= 4;
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cfg_valid <= 1'b1;
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@(negedge clk)
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cfg_addr <= 'b0;
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cfg_data <= 'b0;
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cfg_valid <= 1'b0;
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repeat(5) @(negedge clk);
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cfg_addr <= CONFIG_DATA;
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cfg_data <= 8;
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cfg_valid <= 1'b1;
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@(negedge clk)
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cfg_addr <= 'b0;
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cfg_data <= 'b0;
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cfg_valid <= 1'b0;
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repeat(5) @(negedge clk);
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`ifdef TB_VERBOSE
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$display("test write address channel");
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`endif
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repeat(3) @(negedge clk);
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axi_awready <= 1'b1;
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repeat(5) @(negedge clk);
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axi_wready <= 1'b1;
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data <= 'b0;
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valid <= 1'b0;
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repeat(5) @(negedge clk);
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repeat (5) begin
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data <= data + 1;
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valid <= 1'b1;
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@(negedge clk);
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end
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axi_wready <= 1'b0;
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//data <= 'b0;
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valid <= 1'b0;
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repeat(5) @(negedge clk);
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repeat (3) begin
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data <= data + 1;
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valid <= 1'b1;
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@(negedge clk);
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end
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axi_wready <= 1'b1;
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data <= 'b0;
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valid <= 1'b0;
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//repeat(4) @(negedge clk);
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repeat(5) @(negedge clk);
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//repeat(6) @(negedge clk);
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axi_wready <= 1'b0;
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@(negedge clk);
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axi_wready <= 1'b1;
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repeat(15) @(negedge clk);
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`ifdef TB_VERBOSE
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$display("send config id, start address and length");
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`endif
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repeat(5) @(negedge clk);
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cfg_addr <= CONFIG_ADDR;
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cfg_data <= CONFIG_ID;
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cfg_valid <= 1'b1;
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@(negedge clk)
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cfg_addr <= CONFIG_DATA;
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cfg_data <= 4;
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cfg_valid <= 1'b1;
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@(negedge clk)
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cfg_addr <= CONFIG_DATA;
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cfg_data <= 8;
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cfg_valid <= 1'b1;
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@(negedge clk)
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cfg_addr <= 'b0;
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cfg_data <= 'b0;
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cfg_valid <= 1'b0;
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repeat(5) @(negedge clk);
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`ifdef TB_VERBOSE
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$display("test write address channel");
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`endif
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repeat(3) @(negedge clk);
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axi_awready <= 1'b1;
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repeat(5) @(negedge clk);
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axi_wready <= 1'b1;
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data <= 'b0;
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valid <= 1'b0;
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repeat(5) @(negedge clk);
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repeat (8) begin
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data <= data + 1;
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valid <= 1'b1;
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@(negedge clk);
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valid <= 1'b0;
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repeat(5) @(negedge clk);
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end
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axi_awready <= 1'b0;
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axi_wready <= 1'b0;
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repeat(15) @(negedge clk);
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`ifdef TB_VERBOSE
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$display("send config id, start address and length");
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`endif
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repeat(5) @(negedge clk);
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cfg_addr <= CONFIG_ADDR;
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cfg_data <= CONFIG_ID;
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cfg_valid <= 1'b1;
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@(negedge clk)
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cfg_addr <= CONFIG_DATA;
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cfg_data <= 255;
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cfg_valid <= 1'b1;
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@(negedge clk)
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cfg_addr <= CONFIG_DATA;
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cfg_data <= STREAM_LENGTH;
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cfg_valid <= 1'b1;
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@(negedge clk)
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cfg_addr <= 'b0;
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cfg_data <= 'b0;
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cfg_valid <= 1'b0;
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repeat(5) @(negedge clk);
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`ifdef TB_VERBOSE
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$display("test long write");
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`endif
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repeat(3) @(negedge clk);
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// ready to recive address
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axi_awready <= 1'b1;
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repeat(5) @(negedge clk);
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// ready to recive data
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axi_wready <= 1'b1;
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data <= 'b0;
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valid <= 1'b0;
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repeat(5) @(negedge clk);
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repeat (STREAM_LENGTH) begin
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// stream data into axis
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data <= data + 1;
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valid <= 1'b1;
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@(negedge clk);
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end
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valid <= 1'b0;
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repeat(15) @(negedge clk);
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axi_wready <= 1'b0;
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repeat(15) @(negedge clk);
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`ifdef TB_VERBOSE
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$display("END");
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`endif
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-> end_trigger;
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end
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endmodule
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