mirror of
https://github.com/bmartini/zynq-axis.git
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3370f1bd32
This script copies all Verilog file from the hdl directories into a 'sim' directory. It then uses the Icarus Verilog simulator to run the desired modules testbench.
68 lines
1.4 KiB
Bash
Executable File
68 lines
1.4 KiB
Bash
Executable File
#!/bin/bash
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set -o errexit
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# Should give an arg
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if [ $# == 0 ]
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then
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echo "? executes the testbench for the module"
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echo "syntax:"
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echo " ./sim-module <module-name>"
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exit
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fi
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# create sim scratch work directory
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test -d sim/scratch && rm -rf sim/scratch
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mkdir -p sim/scratch/src
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# copy verilog code files from hdl directory into sim work dir
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for FILE in $(find ./hdl/* -name "*.v" -type f -print)
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do
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cp -n $FILE ./sim/scratch/src/ || { echo "ERROR duplicate filename ${FILE}" ; exit 1; }
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done
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# copy verilog header files from hdl directory into sim work dir
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for FILE in $(find ./hdl/*/ -name "*.vh" -type f -print)
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do
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cp -n $FILE ./sim/scratch/src/ || { echo "ERROR duplicate filename ${FILE}" ; exit 1; }
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done
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# copy SystemVerilog code files from hdl directory into sim work dir
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for FILE in $(find ./hdl/*/ -name "*.sv" -type f -print)
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do
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cp -n $FILE ./sim/scratch/src/ || { echo "ERROR duplicate filename ${FILE}" ; exit 1; }
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done
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# cd into the working dir
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cd sim/scratch/src
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# UUT should contain the name of the unit under test
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if [ -f $1_tb.v ]
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then
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UUT=$1
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else
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echo "syntax:"
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echo " ./sim-module <module-name>"
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echo ""
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echo "Where <module-name>_tb.v should exist"
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exit
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fi
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# compile current unit
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echo "UUT = $UUT"
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iverilog -o ../$UUT ${UUT}_tb.v
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cd ..
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# run current simul/testbench
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if [ -f $UUT ]
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then
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./$UUT
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else
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echo "iverilog failed"
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exit
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fi
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echo "test for unit ${UUT} done"
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