Berin Martini c9bef3cda3 Add module to decode AXI4 Lite bus ...

The module copies the protocol responses/handling from a Xilinx example.
As such it works but to my eye does not look very efficient.

2015-01-01 21:42:38 -05:00

app

Add cfg bus read/write function to interface lib

2014-12-31 13:30:36 -05:00

dev

Allocate CMA memory on driver probe

2014-12-31 11:15:11 -05:00

hdl

Add module to decode AXI4 Lite bus

2015-01-01 21:42:38 -05:00

lib

Add cfg bus read/write function to interface lib

2014-12-31 13:30:36 -05:00

syn

Add scripts to synthesize bitstream via CLI

2014-12-31 20:20:40 -05:00

util

Add indent script for linux kernel code formatting

2014-12-31 11:15:11 -05:00

.gitignore

Add gitignore file to vim swap file and others

2014-12-31 13:18:54 -05:00

syn-proj

Add scripts to synthesize bitstream via CLI

2014-12-31 20:20:40 -05:00

syn-proj-prep

Add bash script to prepare project build directories

2014-12-31 15:34:29 -05:00

Description

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232 KiB

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Verilog 73.4%

C 10.8%

Shell 8.5%

Tcl 6.5%

Makefile 0.8%