FPGA/zynq-axis
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Berin Martini c9bef3cda3 Add module to decode AXI4 Lite bus 
The module copies the protocol responses/handling from a Xilinx example.
As such it works but to my eye does not look very efficient.
2015-01-01 21:42:38 -05:00
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Add module to decode AXI4 Lite bus
2015-01-01 21:42:38 -05:00
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Add module to decode AXI4 Lite bus
2015-01-01 21:42:38 -05:00