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The axis module instantiates the AXI read and write path modules. It performs a simple stream over the AXI port interface with no error checking. It is configured by first addressing the module and then sending a physical memory address and the number of streaming words to be written. The streaming interface is not exactly like the Xilinx stream interface in that the data is always valid when the valid flag is high, the ready flag being low does not invalidate the data but is used to signal up stream to stop sending data. Down stream has a buffer able to absorb to incoming valid data until such time as up stream stop sending.