mirror of
https://github.com/candle-usb/candleLight_fw.git
synced 2025-01-14 05:42:53 +08:00
can: rename can_data_t hcan -> channel
No functional change.
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fd1c0c8471
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84ec4d5501
@ -45,25 +45,25 @@ typedef struct {
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uint8_t sjw;
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} can_data_t;
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void can_init(can_data_t *hcan, CAN_TypeDef *instance);
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bool can_set_bittiming(can_data_t *hcan, uint16_t brp, uint8_t phase_seg1, uint8_t phase_seg2, uint8_t sjw);
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void can_enable(can_data_t *hcan, bool loop_back, bool listen_only, bool one_shot);
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void can_disable(can_data_t *hcan);
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bool can_is_enabled(can_data_t *hcan);
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void can_init(can_data_t *channel, CAN_TypeDef *instance);
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bool can_set_bittiming(can_data_t *channel, uint16_t brp, uint8_t phase_seg1, uint8_t phase_seg2, uint8_t sjw);
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void can_enable(can_data_t *channel, bool loop_back, bool listen_only, bool one_shot);
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void can_disable(can_data_t *channel);
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bool can_is_enabled(can_data_t *channel);
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bool can_receive(can_data_t *hcan, struct gs_host_frame *rx_frame);
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bool can_is_rx_pending(can_data_t *hcan);
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bool can_receive(can_data_t *channel, struct gs_host_frame *rx_frame);
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bool can_is_rx_pending(can_data_t *channel);
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bool can_send(can_data_t *hcan, struct gs_host_frame *frame);
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bool can_send(can_data_t *channel, struct gs_host_frame *frame);
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/** return CAN->ESR register which contains tx/rx error counters and
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* LEC (last error code).
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*/
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uint32_t can_get_error_status(can_data_t *hcan);
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uint32_t can_get_error_status(can_data_t *channel);
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/** parse status value returned by can_get_error_status().
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* @param frame : will hold the generated error frame
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* @param err : holds the contents of the ESR register
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* @return 1 when status changes (if any) need a new error frame sent
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*/
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bool can_parse_error_status(can_data_t *hcan, struct gs_host_frame *frame, uint32_t err);
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bool can_parse_error_status(can_data_t *channel, struct gs_host_frame *frame, uint32_t err);
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@ -29,6 +29,6 @@ THE SOFTWARE.
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#include "can.h"
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#include "hal_include.h"
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void device_can_init(can_data_t *hcan, CAN_TypeDef *instance);
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void device_can_init(can_data_t *channel, CAN_TypeDef *instance);
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void device_sysclock_config(void);
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62
src/can.c
62
src/can.c
@ -55,41 +55,41 @@ static void rcc_reset(CAN_TypeDef *instance)
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#endif
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}
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void can_init(can_data_t *hcan, CAN_TypeDef *instance)
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void can_init(can_data_t *channel, CAN_TypeDef *instance)
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{
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device_can_init(hcan, instance);
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device_can_init(channel, instance);
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}
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bool can_set_bittiming(can_data_t *hcan, uint16_t brp, uint8_t phase_seg1, uint8_t phase_seg2, uint8_t sjw)
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bool can_set_bittiming(can_data_t *channel, uint16_t brp, uint8_t phase_seg1, uint8_t phase_seg2, uint8_t sjw)
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{
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if ( (brp>0) && (brp<=1024)
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&& (phase_seg1>0) && (phase_seg1<=16)
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&& (phase_seg2>0) && (phase_seg2<=8)
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&& (sjw>0) && (sjw<=4)
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) {
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hcan->brp = brp & 0x3FF;
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hcan->phase_seg1 = phase_seg1;
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hcan->phase_seg2 = phase_seg2;
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hcan->sjw = sjw;
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channel->brp = brp & 0x3FF;
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channel->phase_seg1 = phase_seg1;
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channel->phase_seg2 = phase_seg2;
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channel->sjw = sjw;
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return true;
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} else {
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return false;
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}
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}
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void can_enable(can_data_t *hcan, bool loop_back, bool listen_only, bool one_shot)
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void can_enable(can_data_t *channel, bool loop_back, bool listen_only, bool one_shot)
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{
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CAN_TypeDef *can = hcan->instance;
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CAN_TypeDef *can = channel->instance;
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uint32_t mcr = CAN_MCR_INRQ
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| CAN_MCR_ABOM
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| CAN_MCR_TXFP
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| (one_shot ? CAN_MCR_NART : 0);
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uint32_t btr = ((uint32_t)(hcan->sjw-1)) << 24
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| ((uint32_t)(hcan->phase_seg1-1)) << 16
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| ((uint32_t)(hcan->phase_seg2-1)) << 20
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| (hcan->brp - 1)
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uint32_t btr = ((uint32_t)(channel->sjw-1)) << 24
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| ((uint32_t)(channel->phase_seg1-1)) << 16
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| ((uint32_t)(channel->phase_seg2-1)) << 20
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| (channel->brp - 1)
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| (loop_back ? CAN_MODE_LOOPBACK : 0)
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| (listen_only ? CAN_MODE_SILENT : 0);
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@ -128,32 +128,32 @@ void can_enable(can_data_t *hcan, bool loop_back, bool listen_only, bool one_sho
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#endif
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}
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void can_disable(can_data_t *hcan)
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void can_disable(can_data_t *channel)
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{
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CAN_TypeDef *can = hcan->instance;
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CAN_TypeDef *can = channel->instance;
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#ifdef nCANSTBY_Pin
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HAL_GPIO_WritePin(nCANSTBY_Port, nCANSTBY_Pin, GPIO_INIT_STATE(nCANSTBY_Active_High));
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#endif
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can->MCR |= CAN_MCR_INRQ; // send can controller into initialization mode
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}
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bool can_is_enabled(can_data_t *hcan)
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bool can_is_enabled(can_data_t *channel)
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{
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CAN_TypeDef *can = hcan->instance;
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CAN_TypeDef *can = channel->instance;
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return (can->MCR & CAN_MCR_INRQ) == 0;
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}
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bool can_is_rx_pending(can_data_t *hcan)
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bool can_is_rx_pending(can_data_t *channel)
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{
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CAN_TypeDef *can = hcan->instance;
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CAN_TypeDef *can = channel->instance;
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return ((can->RF0R & CAN_RF0R_FMP0) != 0);
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}
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bool can_receive(can_data_t *hcan, struct gs_host_frame *rx_frame)
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bool can_receive(can_data_t *channel, struct gs_host_frame *rx_frame)
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{
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CAN_TypeDef *can = hcan->instance;
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CAN_TypeDef *can = channel->instance;
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if (can_is_rx_pending(hcan)) {
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if (can_is_rx_pending(channel)) {
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CAN_FIFOMailBox_TypeDef *fifo = &can->sFIFOMailBox[0];
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if (fifo->RIR & CAN_RI0R_IDE) {
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@ -185,9 +185,9 @@ bool can_receive(can_data_t *hcan, struct gs_host_frame *rx_frame)
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}
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}
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static CAN_TxMailBox_TypeDef *can_find_free_mailbox(can_data_t *hcan)
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static CAN_TxMailBox_TypeDef *can_find_free_mailbox(can_data_t *channel)
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{
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CAN_TypeDef *can = hcan->instance;
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CAN_TypeDef *can = channel->instance;
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uint32_t tsr = can->TSR;
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if ( tsr & CAN_TSR_TME0 ) {
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@ -201,9 +201,9 @@ static CAN_TxMailBox_TypeDef *can_find_free_mailbox(can_data_t *hcan)
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}
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}
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bool can_send(can_data_t *hcan, struct gs_host_frame *frame)
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bool can_send(can_data_t *channel, struct gs_host_frame *frame)
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{
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CAN_TxMailBox_TypeDef *mb = can_find_free_mailbox(hcan);
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CAN_TxMailBox_TypeDef *mb = can_find_free_mailbox(channel);
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if (mb != 0) {
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/* first, clear transmission request */
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@ -243,9 +243,9 @@ bool can_send(can_data_t *hcan, struct gs_host_frame *frame)
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}
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}
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uint32_t can_get_error_status(can_data_t *hcan)
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uint32_t can_get_error_status(can_data_t *channel)
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{
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CAN_TypeDef *can = hcan->instance;
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CAN_TypeDef *can = channel->instance;
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uint32_t err = can->ESR;
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@ -260,15 +260,15 @@ static bool status_is_active(uint32_t err)
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return !(err & (CAN_ESR_BOFF | CAN_ESR_EPVF));
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}
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bool can_parse_error_status(can_data_t *hcan, struct gs_host_frame *frame, uint32_t err)
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bool can_parse_error_status(can_data_t *channel, struct gs_host_frame *frame, uint32_t err)
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{
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uint32_t last_err = hcan->reg_esr_old;
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uint32_t last_err = channel->reg_esr_old;
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/* We build up the detailed error information at the same time as we decide
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* whether there's anything worth sending. This variable tracks that final
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* result. */
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bool should_send = false;
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hcan->reg_esr_old = err;
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channel->reg_esr_old = err;
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frame->echo_id = 0xFFFFFFFF;
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frame->can_id = CAN_ERR_FLAG;
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@ -31,7 +31,7 @@ THE SOFTWARE.
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#include "device.h"
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#include "hal_include.h"
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void device_can_init(can_data_t *hcan, CAN_TypeDef *instance) {
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void device_can_init(can_data_t *channel, CAN_TypeDef *instance) {
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__HAL_RCC_CAN1_CLK_ENABLE();
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GPIO_InitTypeDef itd;
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@ -43,11 +43,11 @@ void device_can_init(can_data_t *hcan, CAN_TypeDef *instance) {
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itd.Alternate = GPIO_AF4_CAN;
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HAL_GPIO_Init(GPIOB, &itd);
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hcan->instance = instance;
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hcan->brp = 6;
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hcan->sjw = 1;
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hcan->phase_seg1 = 13;
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hcan->phase_seg2 = 2;
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channel->instance = instance;
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channel->brp = 6;
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channel->sjw = 1;
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channel->phase_seg1 = 13;
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channel->phase_seg2 = 2;
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return;
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}
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@ -29,7 +29,7 @@ THE SOFTWARE.
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#include "device.h"
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#include "hal_include.h"
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void device_can_init(can_data_t *hcan, CAN_TypeDef *instance) {
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void device_can_init(can_data_t *channel, CAN_TypeDef *instance) {
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__HAL_RCC_CAN1_CLK_ENABLE();
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GPIO_InitTypeDef itd;
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@ -41,11 +41,11 @@ void device_can_init(can_data_t *hcan, CAN_TypeDef *instance) {
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itd.Alternate = GPIO_AF9_CAN1;
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HAL_GPIO_Init(GPIOD, &itd);
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hcan->instance = instance;
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hcan->brp = 6;
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hcan->sjw = 1;
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hcan->phase_seg1 = 12;
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hcan->phase_seg2 = 1;
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channel->instance = instance;
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channel->brp = 6;
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channel->sjw = 1;
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channel->phase_seg1 = 12;
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channel->phase_seg2 = 1;
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return;
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}
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@ -31,7 +31,7 @@ THE SOFTWARE.
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#include "device.h"
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#include "hal_include.h"
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void device_can_init(can_data_t *hcan, CAN_TypeDef *instance) {
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void device_can_init(can_data_t *channel, CAN_TypeDef *instance) {
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// XXX TODO
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while (1);
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return;
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