mirror of
https://github.com/candle-usb/candleLight_fw.git
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100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/*
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The MIT License (MIT)
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Copyright (c) 2016, 2019 Hubert Denkmair
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include <cmsis_device.h>
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void hex32(char *out, uint32_t val);
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// ARM's
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// "Application Note 321 ARM Cortex-M Programming Guide to Memory Barrier Instructions"
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// (from https://developer.arm.com/documentation/dai0321/latest) says that
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// the ISBs are actually necessary on Cortex-M0 to avoid a 2-instruction
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// delay in the effect of enabling and disabling interrupts.
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// That probably doesn't matter here, but it's hard to say what the compiler
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// will put in those 2 instructions so it's safer to leave it. The DSB isn't
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// necessary on Cortex-M0, but it's architecturally required so we'll
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// include it to be safe.
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//
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// The "memory" and "cc" clobbers tell GCC to avoid moving memory loads or
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// stores across the instructions. This is important when an interrupt and the
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// code calling disable_irq/enable_irq share memory. The fact that these are
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// non-inlined functions probably forces GCC to flush everything to memory
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// anyways, but trying to outsmart the compiler is a bad strategy (you never
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// know when somebody will turn on LTO or something).
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static inline bool is_irq_enabled(void)
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{
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return (__get_PRIMASK() & 1u) == 0u; // interrupts not prevented
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}
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static inline bool disable_irq(void)
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{
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bool was_enabled = is_irq_enabled();
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__disable_irq();
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__ISB();
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return was_enabled;
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}
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static inline void enable_irq(void)
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{
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__enable_irq();
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__ISB();
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}
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static inline void restore_irq(bool was_enabled)
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{
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if (was_enabled) {
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enable_irq();
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}
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}
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/* Lightweight assert macro to replace standard assert()
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*
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* Standard assert() needs fprint, __FILE__ , __LINE__ string consts etc.
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*
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* stm32's library has "USE_FULL_ASSERT" to enable some checks, but they have
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* their own assert_param() macro that also passes in __FILE__, __LINE__ so
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* I'm not sure if (and how) it'll be possible to combine both.
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*
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* Interesting notes on
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* https://barrgroup.com/embedded-systems/how-to/define-assert-macro
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*
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*/
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#define assert_basic(exp) \
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if (exp) { \
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} else \
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assert_failed()
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/** halt / set core to debug state with BKPT.
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*
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* TODO : save extra info somewhere in RAM, and let WDT auto-reset ?
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*/
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void assert_failed(void);
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