diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/.config b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/.config index 0661a19..747cb68 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/.config +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/.config @@ -118,7 +118,6 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set -# CONFIG_RT_USING_DFS_NFS is not set # # Device Drivers @@ -130,7 +129,7 @@ CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=128 +CONFIG_RT_SERIAL_RB_BUFSZ=512 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set @@ -195,7 +194,6 @@ CONFIG_RT_USING_SAL=y # # protocol stack implement # -CONFIG_SAL_USING_LWIP=y CONFIG_SAL_USING_AT=y CONFIG_SAL_USING_POSIX=y @@ -215,58 +213,7 @@ CONFIG_NETDEV_IPV6=0 # # light weight TCP/IP stack # -CONFIG_RT_USING_LWIP=y -# CONFIG_RT_USING_LWIP141 is not set -CONFIG_RT_USING_LWIP202=y -# CONFIG_RT_USING_LWIP210 is not set -# CONFIG_RT_USING_LWIP_IPV6 is not set -CONFIG_RT_LWIP_IGMP=y -CONFIG_RT_LWIP_ICMP=y -# CONFIG_RT_LWIP_SNMP is not set -CONFIG_RT_LWIP_DNS=y -CONFIG_RT_LWIP_DHCP=y -CONFIG_IP_SOF_BROADCAST=1 -CONFIG_IP_SOF_BROADCAST_RECV=1 - -# -# Static IPv4 Address -# -CONFIG_RT_LWIP_IPADDR="192.168.1.30" -CONFIG_RT_LWIP_GWADDR="192.168.1.1" -CONFIG_RT_LWIP_MSKADDR="255.255.255.0" -CONFIG_RT_LWIP_UDP=y -CONFIG_RT_LWIP_TCP=y -CONFIG_RT_LWIP_RAW=y -# CONFIG_RT_LWIP_PPP is not set -CONFIG_RT_MEMP_NUM_NETCONN=8 -CONFIG_RT_LWIP_PBUF_NUM=16 -CONFIG_RT_LWIP_RAW_PCB_NUM=4 -CONFIG_RT_LWIP_UDP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_SEG_NUM=40 -CONFIG_RT_LWIP_TCP_SND_BUF=8196 -CONFIG_RT_LWIP_TCP_WND=8196 -CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 -CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 -# CONFIG_LWIP_NO_RX_THREAD is not set -# CONFIG_LWIP_NO_TX_THREAD is not set -CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 -CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 -# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set -CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 -CONFIG_LWIP_NETIF_LINK_CALLBACK=1 -CONFIG_SO_REUSE=1 -CONFIG_LWIP_SO_RCVTIMEO=1 -CONFIG_LWIP_SO_SNDTIMEO=1 -CONFIG_LWIP_SO_RCVBUF=1 -# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set -CONFIG_LWIP_NETIF_LOOPBACK=0 -# CONFIG_RT_LWIP_STATS is not set -# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set -CONFIG_RT_LWIP_USING_PING=y -# CONFIG_RT_LWIP_DEBUG is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -279,9 +226,8 @@ CONFIG_AT_CLIENT_NUM_MAX=1 CONFIG_AT_USING_SOCKET=y CONFIG_AT_USING_CLI=y # CONFIG_AT_PRINT_RAW_CMD is not set -CONFIG_AT_CMD_MAX_LEN=512 +CONFIG_AT_CMD_MAX_LEN=128 CONFIG_AT_SW_VERSION_NUM=0x10300 -# CONFIG_LWIP_USING_DHCPD is not set # # VBUS(Virtual Software BUS) @@ -362,14 +308,12 @@ CONFIG_PKG_USING_NETUTILS=y CONFIG_PKG_NETUTILS_PATH="/packages/iot/netutils" # CONFIG_PKG_NETUTILS_TFTP is not set # CONFIG_PKG_NETUTILS_IPERF is not set -# CONFIG_PKG_NETUTILS_NETIO is not set CONFIG_PKG_NETUTILS_NTP=y CONFIG_NETUTILS_NTP_TIMEZONE=8 CONFIG_NETUTILS_NTP_HOSTNAME="cn.ntp.org.cn" CONFIG_NETUTILS_NTP_HOSTNAME2="ntp.rt-thread.org" CONFIG_NETUTILS_NTP_HOSTNAME3="edu.ntp.org.cn" # CONFIG_PKG_NETUTILS_TELNET is not set -# CONFIG_PKG_NETUTILS_TCPDUMP is not set # CONFIG_PKG_USING_NETUTILS_V110 is not set # CONFIG_PKG_USING_NETUTILS_V100 is not set CONFIG_PKG_USING_NETUTILS_LATEST_VERSION=y @@ -383,8 +327,8 @@ CONFIG_PKG_AT_DEVICE_PATH="/packages/iot/at_device" CONFIG_AT_DEVICE_USING_ESP8266=y CONFIG_AT_DEVICE_ESP8266_INIT_ASYN=y CONFIG_AT_DEVICE_ESP8266_SAMPLE=y -CONFIG_ESP8266_SAMPLE_WIFI_SSID="ChinaNet-ssssss" -CONFIG_ESP8266_SAMPLE_WIFI_PASSWORD="SQHWLK9394" +CONFIG_ESP8266_SAMPLE_WIFI_SSID="xgld1" +CONFIG_ESP8266_SAMPLE_WIFI_PASSWORD="xgld64627816" CONFIG_ESP8266_SAMPLE_CLIENT_NAME="uart3" CONFIG_ESP8266_SAMPLE_RECV_BUFF_LEN=512 # CONFIG_AT_DEVICE_USING_RW007 is not set @@ -603,7 +547,6 @@ CONFIG_BSP_USING_SDRAM=y # CONFIG_BSP_USING_QSPI_FLASH is not set CONFIG_BSP_USING_QSPI_MemoryMapped=y # CONFIG_BSP_USING_LCD is not set -CONFIG_BSP_USING_ETH=y # CONFIG_BSP_USING_MPU6050 is not set # CONFIG_BSP_USING_POT is not set # CONFIG_BSP_USING_SDCARD is not set diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/applications/gtxx_ccollect.c b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/applications/gtxx_ccollect.c index 4a81942..13c5623 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/applications/gtxx_ccollect.c +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/applications/gtxx_ccollect.c @@ -10,9 +10,9 @@ #include #include "gt9147.h" -#define LOG_LVL LOG_LVL_DBG -#define LOG_TAG "gt9147" -#include +#define DRV_DEBUG +#define LOG_TAG "gt9147" +#include #define THREAD_PRIORITY 5 #define THREAD_STACK_SIZE 1024 #define THREAD_TIMESLICE 5 diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/applications/sht30_ccollect.c b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/applications/sht30_ccollect.c index a9db5fc..876377c 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/applications/sht30_ccollect.c +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/applications/sht30_ccollect.c @@ -11,9 +11,9 @@ #include #include #include -#define LOG_LVL LOG_LVL_DBG +#define DRV_DEBUG #define LOG_TAG "sht30" -#include +#include #define THREAD_PRIORITY 9 #define THREAD_STACK_SIZE 1024 #define THREAD_TIMESLICE 5 diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/.mxproject b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/.mxproject index 07de937..7184f7c 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/.mxproject +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/.mxproject @@ -5,10 +5,10 @@ SourcePath=D:/Project/hellotouchGFX/demo/3_STM32F767_RTThread_TouchGFX/4_rtthrea SourceFiles=freertos.c;TouchGFXConfiguration.cpp;TouchGFXGeneratedHAL.cpp;TouchGFXHAL.cpp;STM32TouchController.cpp;STM32DMA.cpp;OSWrappers.cpp;TouchGFXGPIO.cpp;app_touchgfx.c;stm32f7xx_it.c;stm32f7xx_hal_msp.c;stm32f7xx_hal_timebase_tim.c;main.c; [PreviousLibFiles] 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HeaderPath=..\Drivers\STM32F7xx_HAL_Driver\Inc;..\Drivers\STM32F7xx_HAL_Driver\Inc\Legacy;..\Middlewares\Third_Party\FreeRTOS\Source\include;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS;..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM7\r0p1;..\Drivers\CMSIS\Device\ST\STM32F7xx\Include;..\Drivers\CMSIS\Include;..\Inc;..\Src; CDefines=USE_HAL_DRIVER;STM32F767xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h deleted file mode 100644 index fbc7b35..0000000 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h +++ /dev/null @@ -1,2217 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_eth.h - * @author MCD Application Team - * @brief Header file of ETH HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_ETH_H -#define __STM32F7xx_HAL_ETH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined (ETH) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup ETH - * @{ - */ - -/** @addtogroup ETH_Private_Macros - * @{ - */ -#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) -#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ - ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) -#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ - ((SPEED) == ETH_SPEED_100M)) -#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ - ((MODE) == ETH_MODE_HALFDUPLEX)) -#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ - ((MODE) == ETH_RXINTERRUPT_MODE)) -#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ - ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) -#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ - ((MODE) == ETH_MEDIA_INTERFACE_RMII)) -#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ - ((CMD) == ETH_WATCHDOG_DISABLE)) -#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ - ((CMD) == ETH_JABBER_DISABLE)) -#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_40BIT)) -#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ - ((CMD) == ETH_CARRIERSENCE_DISABLE)) -#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ - ((CMD) == ETH_RECEIVEOWN_DISABLE)) -#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ - ((CMD) == ETH_LOOPBACKMODE_DISABLE)) -#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ - ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) -#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ - ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) -#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ - ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) -#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_1)) -#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ - ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) -#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ - ((CMD) == ETH_RECEIVEAll_DISABLE)) -#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) -#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) -#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ - ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) -#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ - ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) -#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ - ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) -#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) -#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) -#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) -#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ - ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) -#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) -#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ - ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) -#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) -#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) -#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ - ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) -#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) -#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ - ((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ - ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) -#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) -#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ - ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) -#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) -#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ - ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) -#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) -#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) -#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) -#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) -#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) -#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ - ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) -#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ - ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) -#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ - ((CMD) == ETH_FIXEDBURST_DISABLE)) -#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) -#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ - ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) -#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ - ((FLAG) == ETH_DMATXDESC_IC) || \ - ((FLAG) == ETH_DMATXDESC_LS) || \ - ((FLAG) == ETH_DMATXDESC_FS) || \ - ((FLAG) == ETH_DMATXDESC_DC) || \ - ((FLAG) == ETH_DMATXDESC_DP) || \ - ((FLAG) == ETH_DMATXDESC_TTSE) || \ - ((FLAG) == ETH_DMATXDESC_TER) || \ - ((FLAG) == ETH_DMATXDESC_TCH) || \ - ((FLAG) == ETH_DMATXDESC_TTSS) || \ - ((FLAG) == ETH_DMATXDESC_IHE) || \ - ((FLAG) == ETH_DMATXDESC_ES) || \ - ((FLAG) == ETH_DMATXDESC_JT) || \ - ((FLAG) == ETH_DMATXDESC_FF) || \ - ((FLAG) == ETH_DMATXDESC_PCE) || \ - ((FLAG) == ETH_DMATXDESC_LCA) || \ - ((FLAG) == ETH_DMATXDESC_NC) || \ - ((FLAG) == ETH_DMATXDESC_LCO) || \ - ((FLAG) == ETH_DMATXDESC_EC) || \ - ((FLAG) == ETH_DMATXDESC_VF) || \ - ((FLAG) == ETH_DMATXDESC_CC) || \ - ((FLAG) == ETH_DMATXDESC_ED) || \ - ((FLAG) == ETH_DMATXDESC_UF) || \ - ((FLAG) == ETH_DMATXDESC_DB)) -#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ - ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) -#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) -#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) -#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ - ((FLAG) == ETH_DMARXDESC_AFM) || \ - ((FLAG) == ETH_DMARXDESC_ES) || \ - ((FLAG) == ETH_DMARXDESC_DE) || \ - ((FLAG) == ETH_DMARXDESC_SAF) || \ - ((FLAG) == ETH_DMARXDESC_LE) || \ - ((FLAG) == ETH_DMARXDESC_OE) || \ - ((FLAG) == ETH_DMARXDESC_VLAN) || \ - ((FLAG) == ETH_DMARXDESC_FS) || \ - ((FLAG) == ETH_DMARXDESC_LS) || \ - ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ - ((FLAG) == ETH_DMARXDESC_LC) || \ - ((FLAG) == ETH_DMARXDESC_FT) || \ - ((FLAG) == ETH_DMARXDESC_RWT) || \ - ((FLAG) == ETH_DMARXDESC_RE) || \ - ((FLAG) == ETH_DMARXDESC_DBE) || \ - ((FLAG) == ETH_DMARXDESC_CE) || \ - ((FLAG) == ETH_DMARXDESC_MAMPCE)) -#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ - ((BUFFER) == ETH_DMARXDESC_BUFFER2)) -#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ - ((FLAG) == ETH_PMT_FLAG_MPR)) -#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) -#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ - ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ - ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ - ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ - ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ - ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ - ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ - ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ - ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ - ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ - ((FLAG) == ETH_DMA_FLAG_T)) -#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00)) -#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ - ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ - ((IT) == ETH_MAC_IT_PMT)) -#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ - ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ - ((FLAG) == ETH_MAC_FLAG_PMT)) -#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00)) -#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ - ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ - ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ - ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ - ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ - ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ - ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ - ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ - ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) -#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ - ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) -#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ - ((IT) != 0x00)) -#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ - ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ - ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) -#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ - ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) - - -/** - * @} - */ - -/** @addtogroup ETH_Private_Defines - * @{ - */ -/* Delay to wait when writing to some Ethernet registers */ -#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U) - -/* Ethernet Errors */ -#define ETH_SUCCESS ((uint32_t)0U) -#define ETH_ERROR ((uint32_t)1U) - -/* Ethernet DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U) - -/* Ethernet DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) - -/* Ethernet DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U) - -/* Ethernet DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) - -/* Ethernet DMA Rx descriptors Frame length Shift */ -#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16) - -/* Ethernet MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */ - -/* Ethernet MACMIIAR register Mask */ -#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U) - -/* Ethernet MACCR register Mask */ -#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU) - -/* Ethernet MACFCR register Mask */ -#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U) - -/* Ethernet DMAOMR register Mask */ -#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U) - -/* Ethernet Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8U - -/* Ethernet Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U - /** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ETH_Exported_Types ETH Exported Types - * @{ - */ - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ - HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ - HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ - HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ - HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ - HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ - HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -}HAL_ETH_StateTypeDef; - -/** - * @brief ETH Init Structure definition - */ - -typedef struct -{ - uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY - The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) - and the mode (half/full-duplex). - This parameter can be a value of @ref ETH_AutoNegotiation */ - - uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. - This parameter can be a value of @ref ETH_Speed */ - - uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode - This parameter can be a value of @ref ETH_Duplex_Mode */ - - uint16_t PhyAddress; /*!< Ethernet PHY address. - This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - - uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ - - uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. - This parameter can be a value of @ref ETH_Rx_Mode */ - - uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. - This parameter can be a value of @ref ETH_Checksum_Mode */ - - uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. - This parameter can be a value of @ref ETH_Media_Interface */ - -} ETH_InitTypeDef; - - - /** - * @brief ETH MAC Configuration Structure definition - */ - -typedef struct -{ - uint32_t Watchdog; /*!< Selects or not the Watchdog timer - When enabled, the MAC allows no more then 2048 bytes to be received. - When disabled, the MAC can receive up to 16384 bytes. - This parameter can be a value of @ref ETH_Watchdog */ - - uint32_t Jabber; /*!< Selects or not Jabber timer - When enabled, the MAC allows no more then 2048 bytes to be sent. - When disabled, the MAC can send up to 16384 bytes. - This parameter can be a value of @ref ETH_Jabber */ - - uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. - This parameter can be a value of @ref ETH_Inter_Frame_Gap */ - - uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. - This parameter can be a value of @ref ETH_Carrier_Sense */ - - uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, - ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - in Half-Duplex mode. - This parameter can be a value of @ref ETH_Receive_Own */ - - uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. - This parameter can be a value of @ref ETH_Loop_Back_Mode */ - - uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. - This parameter can be a value of @ref ETH_Checksum_Offload */ - - uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, - when a collision occurs (Half-Duplex mode). - This parameter can be a value of @ref ETH_Retry_Transmission */ - - uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. - This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ - - uint32_t BackOffLimit; /*!< Selects the BackOff limit value. - This parameter can be a value of @ref ETH_Back_Off_Limit */ - - uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). - This parameter can be a value of @ref ETH_Deferral_Check */ - - uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). - This parameter can be a value of @ref ETH_Receive_All */ - - uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. - This parameter can be a value of @ref ETH_Source_Addr_Filter */ - - uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) - This parameter can be a value of @ref ETH_Pass_Control_Frames */ - - uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. - This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ - - uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. - This parameter can be a value of @ref ETH_Destination_Addr_Filter */ - - uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode - This parameter can be a value of @ref ETH_Promiscuous_Mode */ - - uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. - This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ - - uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. - This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ - - uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ - - uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ - - uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ - - uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. - This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ - - uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame. - This parameter can be a value of @ref ETH_Pause_Low_Threshold */ - - uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 - unicast address and unique multicast address). - This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ - - uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and - disable its transmitter for a specified time (Pause Time) - This parameter can be a value of @ref ETH_Receive_Flow_Control */ - - uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) - or the MAC back-pressure operation (Half-Duplex mode) - This parameter can be a value of @ref ETH_Transmit_Flow_Control */ - - uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - comparison and filtering. - This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ - - uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ - -} ETH_MACInitTypeDef; - - -/** - * @brief ETH DMA Configuration Structure definition - */ - -typedef struct -{ - uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. - This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ - - uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. - This parameter can be a value of @ref ETH_Receive_Store_Forward */ - - uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. - This parameter can be a value of @ref ETH_Flush_Received_Frame */ - - uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. - This parameter can be a value of @ref ETH_Transmit_Store_Forward */ - - uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. - This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ - - uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. - This parameter can be a value of @ref ETH_Forward_Error_Frames */ - - uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error - and length less than 64 bytes) including pad-bytes and CRC) - This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ - - uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. - This parameter can be a value of @ref ETH_Receive_Threshold_Control */ - - uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second - frame of Transmit data even before obtaining the status for the first frame. - This parameter can be a value of @ref ETH_Second_Frame_Operate */ - - uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. - This parameter can be a value of @ref ETH_Address_Aligned_Beats */ - - uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. - This parameter can be a value of @ref ETH_Fixed_Burst */ - - uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. - This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ - - uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. - This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ - - uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. - This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ - - uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) - This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - - uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. - This parameter can be a value of @ref ETH_DMA_Arbitration */ -} ETH_DMAInitTypeDef; - - -/** - * @brief ETH DMA Descriptors data structure definition - */ - -typedef struct -{ - __IO uint32_t Status; /*!< Status */ - - uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ - - uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ - - uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ - - /*!< Enhanced Ethernet DMA PTP Descriptors */ - uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ - - uint32_t Reserved1; /*!< Reserved */ - - uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ - - uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ - -} ETH_DMADescTypeDef; - - -/** - * @brief Received Frame Informations structure definition - */ -typedef struct -{ - ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ - - ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ - - uint32_t SegCount; /*!< Segment count */ - - uint32_t length; /*!< Frame length */ - - uint32_t buffer; /*!< Frame buffer */ - -} ETH_DMARxFrameInfos; - - -/** - * @brief ETH Handle Structure definition - */ - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -typedef struct __ETH_HandleTypeDef -#else -typedef struct -#endif -{ - ETH_TypeDef *Instance; /*!< Register base address */ - - ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ - - uint32_t LinkStatus; /*!< Ethernet link status */ - - ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ - - ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ - - ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ - - __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ - - HAL_LockTypeDef Lock; /*!< ETH Lock */ - - #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - - void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */ - void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */ - void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */ - void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */ - void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */ - -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -} ETH_HandleTypeDef; - - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -/** - * @brief HAL ETH Callback ID enumeration definition - */ -typedef enum -{ - HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ - HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ - HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ - HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ - HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ - -}HAL_ETH_CallbackIDTypeDef; - -/** - * @brief HAL ETH Callback pointer definition - */ -typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */ - -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ETH_Exported_Constants ETH Exported Constants - * @{ - */ - -/** @defgroup ETH_Buffers_setting ETH Buffers setting - * @{ - */ -#define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */ -#define ETH_EXTRA ((uint32_t)2U) /*!< Extra bytes in some cases */ -#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ -#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */ -#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ -#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */ - - /* Ethernet driver receive buffers are organized in a chained linked-list, when - an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO - to the driver receive buffers memory. - - Depending on the size of the received Ethernet packet and the size of - each Ethernet driver receive buffer, the received packet can take one or more - Ethernet driver receive buffer. - - In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE - and the total count of the driver receive buffers ETH_RXBUFNB. - - The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as - example, they can be reconfigured in the application layer to fit the application - needs */ - -/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet - packet */ -#ifndef ETH_RX_BUF_SIZE - #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ -#ifndef ETH_RXBUFNB - #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ -#endif - - - /* Ethernet driver transmit buffers are organized in a chained linked-list, when - an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the - driver transmit buffers memory to the TxFIFO. - - Depending on the size of the Ethernet packet to be transmitted and the size of - each Ethernet driver transmit buffer, the packet to be transmitted can take - one or more Ethernet driver transmit buffer. - - In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE - and the total count of the driver transmit buffers ETH_TXBUFNB. - - The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as - example, they can be reconfigured in the application layer to fit the application - needs */ - -/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet - packet */ -#ifndef ETH_TX_BUF_SIZE - #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/ -#ifndef ETH_TXBUFNB - #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ -#endif - - /** - * @} - */ - -/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor - * @{ - */ - -/* - DMA Tx Descriptor - ----------------------------------------------------------------------------------------------- - TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | - ----------------------------------------------------------------------------------------------- - TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | - ----------------------------------------------------------------------------------------------- - TDES2 | Buffer1 Address [31:0] | - ----------------------------------------------------------------------------------------------- - TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - ----------------------------------------------------------------------------------------------- -*/ - -/** - * @brief Bit definition of TDES0 register: DMA Tx descriptor status register - */ -#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */ -#define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */ -#define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */ -#define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */ -#define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */ -#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */ -#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */ -#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */ -#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */ -#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */ -#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */ -#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */ -#define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ -#define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */ -#define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ -#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */ -#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */ -#define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */ -#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */ -#define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */ -#define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */ -#define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */ -#define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */ -#define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */ -#define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */ - -/** - * @brief Bit definition of TDES1 register - */ -#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */ -#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */ - -/** - * @brief Bit definition of TDES2 register - */ -#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of TDES3 register - */ -#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ - - /*--------------------------------------------------------------------------------------------- - TDES6 | Transmit Time Stamp Low [31:0] | - ----------------------------------------------------------------------------------------------- - TDES7 | Transmit Time Stamp High [31:0] | - ----------------------------------------------------------------------------------------------*/ - -/* Bit definition of TDES6 register */ - #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */ - -/* Bit definition of TDES7 register */ - #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */ - -/** - * @} - */ -/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor - * @{ - */ - -/* - DMA Rx Descriptor - -------------------------------------------------------------------------------------------------------------------- - RDES0 | OWN(31) | Status [30:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES2 | Buffer1 Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- -*/ - -/** - * @brief Bit definition of RDES0 register: DMA Rx descriptor status register - */ -#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */ -#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */ -#define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ -#define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */ -#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */ -#define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */ -#define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */ -#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */ -#define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */ -#define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */ -#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ -#define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */ -#define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */ -#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ -#define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */ -#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ -#define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */ -#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ - -/** - * @brief Bit definition of RDES1 register - */ -#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */ -#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */ -#define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */ -#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */ -#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */ - -/** - * @brief Bit definition of RDES2 register - */ -#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of RDES3 register - */ -#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ - -/*--------------------------------------------------------------------------------------------------------------------- - RDES4 | Reserved[31:15] | Extended Status [14:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES5 | Reserved[31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES6 | Receive Time Stamp Low [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES7 | Receive Time Stamp High [31:0] | - --------------------------------------------------------------------------------------------------------------------*/ - -/* Bit definition of RDES4 register */ -#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */ -#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */ -#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */ -#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ -#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ -#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ -#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */ -#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */ -#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */ -#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */ -#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */ -#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */ -#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */ -#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */ -#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */ - -/* Bit definition of RDES6 register */ -#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */ - -/* Bit definition of RDES7 register */ -#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */ -/** - * @} - */ - /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation - * @{ - */ -#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U) -#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U) - -/** - * @} - */ -/** @defgroup ETH_Speed ETH Speed - * @{ - */ -#define ETH_SPEED_10M ((uint32_t)0x00000000U) -#define ETH_SPEED_100M ((uint32_t)0x00004000U) - -/** - * @} - */ -/** @defgroup ETH_Duplex_Mode ETH Duplex Mode - * @{ - */ -#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U) -#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U) -/** - * @} - */ -/** @defgroup ETH_Rx_Mode ETH Rx Mode - * @{ - */ -#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U) -#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U) -/** - * @} - */ - -/** @defgroup ETH_Checksum_Mode ETH Checksum Mode - * @{ - */ -#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U) -#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U) -/** - * @} - */ - -/** @defgroup ETH_Media_Interface ETH Media Interface - * @{ - */ -#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U) -#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) -/** - * @} - */ - -/** @defgroup ETH_Watchdog ETH Watchdog - * @{ - */ -#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U) -#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U) -/** - * @} - */ - -/** @defgroup ETH_Jabber ETH Jabber - * @{ - */ -#define ETH_JABBER_ENABLE ((uint32_t)0x00000000U) -#define ETH_JABBER_DISABLE ((uint32_t)0x00400000U) -/** - * @} - */ - -/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap - * @{ - */ -#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) /*!< minimum IFG between frames during transmission is 96Bit */ -#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) /*!< minimum IFG between frames during transmission is 88Bit */ -#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) /*!< minimum IFG between frames during transmission is 80Bit */ -#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) /*!< minimum IFG between frames during transmission is 72Bit */ -#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) /*!< minimum IFG between frames during transmission is 64Bit */ -#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) /*!< minimum IFG between frames during transmission is 56Bit */ -#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) /*!< minimum IFG between frames during transmission is 48Bit */ -#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) /*!< minimum IFG between frames during transmission is 40Bit */ -/** - * @} - */ - -/** @defgroup ETH_Carrier_Sense ETH Carrier Sense - * @{ - */ -#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U) -#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U) -/** - * @} - */ - -/** @defgroup ETH_Receive_Own ETH Receive Own - * @{ - */ -#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) -#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U) -/** - * @} - */ - -/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode - * @{ - */ -#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U) -#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Checksum_Offload ETH Checksum Offload - * @{ - */ -#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U) -#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Retry_Transmission ETH Retry Transmission - * @{ - */ -#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) -#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U) -/** - * @} - */ - -/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip - * @{ - */ -#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U) -#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit - * @{ - */ -#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U) -#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U) -#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U) -#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U) -/** - * @} - */ - -/** @defgroup ETH_Deferral_Check ETH Deferral Check - * @{ - */ -#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U) -#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Receive_All ETH Receive All - * @{ - */ -#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U) -#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter - * @{ - */ -#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U) -#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U) -#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames - * @{ - */ -#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) /*!< MAC filters all control frames from reaching the application */ -#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ -#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) /*!< MAC forwards control frames that pass the Address Filter. */ -/** - * @} - */ - -/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception - * @{ - */ -#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U) -#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U) -/** - * @} - */ - -/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter - * @{ - */ -#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U) -#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode - * @{ - */ -#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U) -#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter - * @{ - */ -#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U) -#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U) -#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) -#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U) -/** - * @} - */ - -/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter - * @{ - */ -#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U) -#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U) -#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause - * @{ - */ -#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U) -#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U) -/** - * @} - */ - -/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold - * @{ - */ -#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) /*!< Pause time minus 4 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) /*!< Pause time minus 28 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) /*!< Pause time minus 144 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) /*!< Pause time minus 256 slot times */ -/** - * @} - */ - -/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect - * @{ - */ -#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U) -#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control - * @{ - */ -#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U) -#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control - * @{ - */ -#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U) -#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison - * @{ - */ -#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U) -#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses ETH MAC addresses - * @{ - */ -#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U) -#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U) -#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U) -#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA - * @{ - */ -#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U) -#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes - * @{ - */ -#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) /*!< Mask MAC Address high reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) /*!< Mask MAC Address high reg bits [7:0] */ -#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) /*!< Mask MAC Address low reg bits [31:24] */ -#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) /*!< Mask MAC Address low reg bits [23:16] */ -#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) /*!< Mask MAC Address low reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) /*!< Mask MAC Address low reg bits [70] */ -/** - * @} - */ - -/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame - * @{ - */ -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U) -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U) -/** - * @} - */ - -/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward - * @{ - */ -#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U) -#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame - * @{ - */ -#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U) -#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward - * @{ - */ -#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U) -#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control - * @{ - */ -#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ -/** - * @} - */ - -/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames - * @{ - */ -#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U) -#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames - * @{ - */ -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U) -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control - * @{ - */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ -/** - * @} - */ - -/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate - * @{ - */ -#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U) -#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats - * @{ - */ -#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U) -#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Fixed_Burst ETH Fixed Burst - * @{ - */ -#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U) -#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length - * @{ - */ -#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ -#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ -#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ -/** - * @} - */ - -/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length - * @{ - */ -#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ -#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ -#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format - * @{ - */ -#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U) -#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration - * @{ - */ -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U) -#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U) -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment - * @{ - */ -#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) /*!< Last Segment */ -#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) /*!< First Segment */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control - * @{ - */ -#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) /*!< Checksum engine bypass */ -#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) /*!< IPv4 header checksum insertion */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers - * @{ - */ -#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) /*!< DMA Rx Desc Buffer1 */ -#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) /*!< DMA Rx Desc Buffer2 */ -/** - * @} - */ - -/** @defgroup ETH_PMT_Flags ETH PMT Flags - * @{ - */ -#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) /*!< Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) /*!< Wake-Up Frame Received */ -#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) /*!< Magic Packet Received */ -/** - * @} - */ - -/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts - * @{ - */ -#define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) /*!< When Tx good frame counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) /*!< When Tx good multi col counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) /*!< When Tx good single col counter reaches half the maximum value */ -/** - * @} - */ - -/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts - * @{ - */ -#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) /*!< When Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) /*!< When Rx alignment error counter reaches half the maximum value */ -#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) /*!< When Rx crc error counter reaches half the maximum value */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Flags ETH MAC Flags - * @{ - */ -#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger flag (on MAC) */ -#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit flag */ -#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) /*!< MMC receive flag */ -#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) /*!< MMC flag (on MAC) */ -#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) /*!< PMT flag (on MAC) */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Flags ETH DMA Flags - * @{ - */ -#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) /*!< Error bits 0-write transfer, 1-read transfer */ -#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) /*!< Error bits 0-data buffer, 1-desc. access */ -#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary flag */ -#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary flag */ -#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) /*!< Early receive flag */ -#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error flag */ -#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) /*!< Early transmit flag */ -#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout flag */ -#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped flag */ -#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable flag */ -#define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) /*!< Receive flag */ -#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) /*!< Underflow flag */ -#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) /*!< Overflow flag */ -#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout flag */ -#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable flag */ -#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped flag */ -#define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) /*!< Transmit flag */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts - * @{ - */ -#define ETH_MAC_IT_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger interrupt (on MAC) */ -#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit interrupt */ -#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) /*!< MMC receive interrupt */ -#define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) /*!< MMC interrupt (on MAC) */ -#define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) /*!< PMT interrupt (on MAC) */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts - * @{ - */ -#define ETH_DMA_IT_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary */ -#define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary */ -#define ETH_DMA_IT_ER ((uint32_t)0x00004000U) /*!< Early receive interrupt */ -#define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error interrupt */ -#define ETH_DMA_IT_ET ((uint32_t)0x00000400U) /*!< Early transmit interrupt */ -#define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout interrupt */ -#define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped interrupt */ -#define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable interrupt */ -#define ETH_DMA_IT_R ((uint32_t)0x00000040U) /*!< Receive interrupt */ -#define ETH_DMA_IT_TU ((uint32_t)0x00000020U) /*!< Underflow interrupt */ -#define ETH_DMA_IT_RO ((uint32_t)0x00000010U) /*!< Overflow interrupt */ -#define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout interrupt */ -#define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable interrupt */ -#define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped interrupt */ -#define ETH_DMA_IT_T ((uint32_t)0x00000001U) /*!< Transmit interrupt */ -/** - * @} - */ - -/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state - * @{ - */ -#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Tx Command issued */ -#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) /*!< Running - fetching the Tx descriptor */ -#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) /*!< Running - waiting for status */ -#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) /*!< Running - reading the data from host memory */ -#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) /*!< Suspended - Tx Descriptor unavailable */ -#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) /*!< Running - closing Rx descriptor */ - -/** - * @} - */ - - -/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state - * @{ - */ -#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Rx Command issued */ -#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) /*!< Running - fetching the Rx descriptor */ -#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) /*!< Running - waiting for packet */ -#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) /*!< Suspended - Rx Descriptor unavailable */ -#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) /*!< Running - closing descriptor */ -#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) /*!< Running - queuing the receive frame into host memory */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_overflow ETH DMA overflow - * @{ - */ -#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) /*!< Overflow bit for FIFO overflow counter */ -#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) /*!< Overflow bit for missed frame counter */ -/** - * @} - */ - -/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP - * @{ - */ -#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ETH_Exported_Macros ETH Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ - -/** @brief Reset ETH handle state - * @param __HANDLE__ specifies the ETH handle. - * @retval None - */ -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) -#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag of TDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag of RDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Enables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) - -/** - * @brief Disables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) - -/** - * @brief Set the specified DMA Rx Desc Own bit. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) - -/** - * @brief Returns the specified Ethernet DMA Tx Desc collision count. - * @param __HANDLE__ ETH Handle - * @retval The Transmit descriptor collision counter value. - */ -#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) - -/** - * @brief Set the specified DMA Tx Desc Own bit. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) - -/** - * @brief Enables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) - -/** - * @brief Disables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) - -/** - * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion. - * @param __HANDLE__ ETH Handle - * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. - * This parameter can be one of the following values: - * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass - * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) - -/** - * @brief Enables the DMA Tx Desc CRC. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) - -/** - * @brief Disables the DMA Tx Desc CRC. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) - -/** - * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) - -/** - * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) - -/** - * @brief Enables the specified Ethernet MAC interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) - -/** - * @brief Disables the specified Ethernet MAC interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) - -/** - * @brief Initiate a Pause Control Frame (Full-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the Ethernet flow control busy bit is set or not. - * @param __HANDLE__ ETH Handle - * @retval The new state of flow control busy status bit (SET or RESET). - */ -#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) - -/** - * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Disables the MAC BackPressure operation activation (Half-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the specified Ethernet MAC flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval The state of Ethernet MAC flag. - */ -#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Enables the specified Ethernet DMA interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be - * enabled @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) - -/** - * @brief Disables the specified Ethernet DMA interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be - * disabled. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) - -/** - * @brief Clears the Ethernet DMA IT pending bit. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) - -/** - * @brief Checks whether the specified Ethernet DMA flag is set or not. -* @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Checks whether the specified Ethernet DMA flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) - -/** - * @brief Checks whether the specified Ethernet DMA overflow flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __OVERFLOW__ specifies the DMA overflow flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter - * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter - * @retval The state of Ethernet DMA overflow Flag (SET or RESET). - */ -#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) - -/** - * @brief Set the DMA Receive status watchdog timer register value - * @param __HANDLE__ ETH Handle - * @param __VALUE__ DMA Receive status watchdog timer register value - * @retval None - */ -#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) - -/** - * @brief Enables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) - -/** - * @brief Disables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) - -/** - * @brief Enables the MAC Wake-Up Frame Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) - -/** - * @brief Disables the MAC Wake-Up Frame Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Magic Packet Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) - -/** - * @brief Disables the MAC Magic Packet Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Power Down. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) - -/** - * @brief Disables the MAC Power Down. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) - -/** - * @brief Checks whether the specified Ethernet PMT flag is set or not. - * @param __HANDLE__ ETH Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset - * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received - * @arg ETH_PMT_FLAG_MPR : Magic Packet Received - * @retval The new state of Ethernet PMT Flag (SET or RESET). - */ -#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) - -/** - * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ - (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) - -/** - * @brief Enables the MMC Counter Freeze. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) - -/** - * @brief Disables the MMC Counter Freeze. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) - -/** - * @brief Enables the MMC Reset On Read. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) - -/** - * @brief Disables the MMC Reset On Read. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) - -/** - * @brief Enables the MMC Counter Stop Rollover. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) - -/** - * @brief Disables the MMC Counter Stop Rollover. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) - -/** - * @brief Resets the MMC Counters. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) - -/** - * @brief Enables the specified Ethernet MMC Rx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) -/** - * @brief Disables the specified Ethernet MMC Rx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) -/** - * @brief Enables the specified Ethernet MMC Tx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) - -/** - * @brief Disables the specified Ethernet MMC Tx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) - -/** - * @brief Enables the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disables the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enable event on ETH External event line. - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disable event on ETH External event line - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Get flag of the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Clear flag of the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables rising edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP - -/** - * @brief Disables the rising edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disables falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ - }while(0) - -/** - * @brief Disables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - }while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP - -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup ETH_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ - -/** @addtogroup ETH_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* IO operation functions ****************************************************/ - -/** @addtogroup ETH_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); -/* Communication with PHY functions*/ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); -/* Callback in non blocking modes (Interrupt) */ -void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ - -/** @addtogroup ETH_Exported_Functions_Group3 - * @{ - */ - -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ - -/** @addtogroup ETH_Exported_Functions_Group4 - * @{ - */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* ETH */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_ETH_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c deleted file mode 100644 index 0dea114..0000000 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c +++ /dev/null @@ -1,2291 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_eth.c - * @author MCD Application Team - * @brief ETH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Ethernet (ETH) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#)Declare a ETH_HandleTypeDef handle structure, for example: - ETH_HandleTypeDef heth; - - (#)Fill parameters of Init structure in heth handle - - (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) - - (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: - (##) Enable the Ethernet interface clock using - (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); - (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); - (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); - - (##) Initialize the related GPIO clocks - (##) Configure Ethernet pin-out - (##) Configure Ethernet NVIC interrupt (IT mode) - - (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: - (##) HAL_ETH_DMATxDescListInit(); for Transmission process - (##) HAL_ETH_DMARxDescListInit(); for Reception process - - (#)Enable MAC and DMA transmission and reception: - (##) HAL_ETH_Start(); - - (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer - the frame to MAC TX FIFO: - (##) HAL_ETH_TransmitFrame(); - - (#)Poll for a received frame in ETH RX DMA Descriptors and get received - frame parameters - (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) - - (#) Get a received frame when an ETH RX interrupt occurs: - (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) - - (#) Communicate with external PHY device: - (##) Read a specific register from the PHY - HAL_ETH_ReadPHYRegister(); - (##) Write data to a specific RHY register: - HAL_ETH_WritePHYRegister(); - - (#) Configure the Ethernet MAC after ETH peripheral initialization - HAL_ETH_ConfigMAC(); all MAC parameters should be filled. - - (#) Configure the Ethernet DMA after ETH peripheral initialization - HAL_ETH_ConfigDMA(); all DMA parameters should be filled. - -*** Callback registration *** - ============================================= - - The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback. - - Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks: - (+) TxCpltCallback : Tx Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) DMAErrorCallback : DMA Error Callback. - (+) MspInitCallback : MspInit Callback. - (+) MspDeInitCallback: MspDeInit Callback. - - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default - weak function. - @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxCpltCallback : Tx Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) DMAErrorCallback : DMA Error Callback. - (+) MspInitCallback : MspInit Callback. - (+) MspDeInitCallback: MspDeInit Callback. - - By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit - or HAL_ETH_Init function. - - When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup ETH ETH - * @brief ETH HAL module driver - * @{ - */ - -#ifdef HAL_ETH_MODULE_ENABLED -#if defined (ETH) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup ETH_Private_Constants ETH Private Constants - * @{ - */ -#define ETH_TIMEOUT_SWRESET ((uint32_t)500) -#define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000) -#define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000) - -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup ETH_Private_Functions ETH Private Functions - * @{ - */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err); -static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); -static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth); -static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth); -static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth); -static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth); -static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth); -static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth); -static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth); -static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth); -static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ETH_Exported_Functions ETH Exported Functions - * @{ - */ - -/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the Ethernet peripheral - (+) De-initialize the Ethernet peripheral - - @endverbatim - * @{ - */ - -/** - * @brief Initializes the Ethernet MAC and DMA according to default - * parameters. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) -{ - uint32_t tempreg = 0, phyreg = 0; - uint32_t hclk = 60000000; - uint32_t tickstart = 0; - uint32_t err = ETH_SUCCESS; - - /* Check the ETH peripheral state */ - if(heth == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); - assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); - assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); - assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); - - if(heth->State == HAL_ETH_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - heth->Lock = HAL_UNLOCKED; -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - ETH_InitCallbacksToDefault(heth); - - if(heth->MspInitCallback == NULL) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC. */ - heth->MspInitCallback = HAL_ETH_MspInit; - } - heth->MspInitCallback(heth); - -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspInit(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - } - - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Select MII or RMII Mode*/ - SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); - SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; - - /* Ethernet Software reset */ - /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ - /* After reset all the registers holds their respective reset values */ - (heth->Instance)->DMABMR |= ETH_DMABMR_SR; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for software reset */ - while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET) - { - heth->State= HAL_ETH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are - not available, please check your external PHY or the IO configuration */ - - return HAL_TIMEOUT; - } - } - - /*-------------------------------- MAC Initialization ----------------------*/ - /* Get the ETHERNET MACMIIAR value */ - tempreg = (heth->Instance)->MACMIIAR; - /* Clear CSR Clock Range CR[2:0] bits */ - tempreg &= ETH_MACMIIAR_CR_MASK; - - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - /* Set CR bits depending on hclk value */ - if((hclk >= 20000000)&&(hclk < 35000000)) - { - /* CSR Clock Range between 20-35 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; - } - else if((hclk >= 35000000)&&(hclk < 60000000)) - { - /* CSR Clock Range between 35-60 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } - else if((hclk >= 60000000)&&(hclk < 100000000)) - { - /* CSR Clock Range between 60-100 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; - } - else if((hclk >= 100000000)&&(hclk < 150000000)) - { - /* CSR Clock Range between 100-150 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; - } - else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */ - { - /* CSR Clock Range between 150-216 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; - } - - /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - (heth->Instance)->MACMIIAR = (uint32_t)tempreg; - - /*-------------------- PHY initialization and configuration ----------------*/ - /* Put the PHY in reset mode */ - if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Delay to assure PHY reset */ - HAL_Delay(PHY_RESET_DELAY); - - if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* We wait for linked status */ - do - { - HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); - - - /* Enable Auto-Negotiation */ - if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the auto-negotiation will be completed */ - do - { - HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); - - /* Read the result of the auto-negotiation */ - if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ - if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) - { - /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - } - else - { - /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; - } - /* Configure the MAC with the speed fixed by the auto-negotiation process */ - if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS) - { - /* Set Ethernet speed to 10M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_10M; - } - else - { - /* Set Ethernet speed to 100M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_100M; - } - } - else /* AutoNegotiation Disable */ - { - /* Check parameters */ - assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - - /* Set MAC Speed and Duplex Mode */ - if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) | - (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Delay to assure PHY configuration */ - HAL_Delay(PHY_CONFIG_DELAY); - } - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief De-Initializes the ETH peripheral. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) -{ - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - if(heth->MspDeInitCallback == NULL) - { - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - } - /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ - heth->MspDeInitCallback(heth); -#else - /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspDeInit(heth); -#endif - - /* Set ETH HAL state to Disabled */ - heth->State= HAL_ETH_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the DMA Tx descriptors in chain mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMATxDescTab Pointer to the first Tx desc list - * @param TxBuff Pointer to the first TxBuffer list - * @param TxBuffCount Number of the used Tx desc in the list - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) -{ - uint32_t i = 0; - ETH_DMADescTypeDef *dmatxdesc; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ - heth->TxDesc = DMATxDescTab; - - /* Fill each DMATxDesc descriptor with the right values */ - for(i=0; i < TxBuffCount; i++) - { - /* Get the pointer on the ith member of the Tx Desc list */ - dmatxdesc = DMATxDescTab + i; - - /* Set Second Address Chained bit */ - dmatxdesc->Status = ETH_DMATXDESC_TCH; - - /* Set Buffer1 address pointer */ - dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); - - if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) - { - /* Set the DMA Tx descriptors checksum insertion */ - dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (TxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; - } - } - - /* Set Transmit Descriptor List Address Register */ - (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab; - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the DMA Rx descriptors in chain mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMARxDescTab Pointer to the first Rx desc list - * @param RxBuff Pointer to the first RxBuffer list - * @param RxBuffCount Number of the used Rx desc in the list - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) -{ - uint32_t i = 0; - ETH_DMADescTypeDef *DMARxDesc; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */ - heth->RxDesc = DMARxDescTab; - - /* Fill each DMARxDesc descriptor with the right values */ - for(i=0; i < RxBuffCount; i++) - { - /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; - - /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = ETH_DMARXDESC_OWN; - - /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; - - /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); - - if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) - { - /* Enable Ethernet DMA Rx Descriptor interrupt */ - DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC; - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (RxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - } - - /* Set Receive Descriptor List Address Register */ - (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab; - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the ETH MSP. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes ETH MSP. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User ETH Callback - * To be used instead of the weak predefined callback - * @param heth eth handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID - * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(pCallback == NULL) - { - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(heth); - - if(heth->State == HAL_ETH_STATE_READY) - { - switch (CallbackID) - { - case HAL_ETH_TX_COMPLETE_CB_ID : - heth->TxCpltCallback = pCallback; - break; - - case HAL_ETH_RX_COMPLETE_CB_ID : - heth->RxCpltCallback = pCallback; - break; - - case HAL_ETH_DMA_ERROR_CB_ID : - heth->DMAErrorCallback = pCallback; - break; - - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if(heth->State == HAL_ETH_STATE_RESET) - { - switch (CallbackID) - { - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(heth); - - return status; -} - -/** - * @brief Unregister an ETH Callback - * ETH callabck is redirected to the weak predefined callback - * @param heth eth handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID - * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(heth); - - if(heth->State == HAL_ETH_STATE_READY) - { - switch (CallbackID) - { - case HAL_ETH_TX_COMPLETE_CB_ID : - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; - break; - - case HAL_ETH_RX_COMPLETE_CB_ID : - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; - break; - - case HAL_ETH_DMA_ERROR_CB_ID : - heth->DMAErrorCallback = HAL_ETH_ErrorCallback; - break; - - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = HAL_ETH_MspInit; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if(heth->State == HAL_ETH_STATE_RESET) - { - switch (CallbackID) - { - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = HAL_ETH_MspInit; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(heth); - - return status; -} -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * - @verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Transmit a frame - HAL_ETH_TransmitFrame(); - (+) Receive a frame - HAL_ETH_GetReceivedFrame(); - HAL_ETH_GetReceivedFrame_IT(); - (+) Read from an External PHY register - HAL_ETH_ReadPHYRegister(); - (+) Write to an External PHY register - HAL_ETH_WritePHYRegister(); - - @endverbatim - - * @{ - */ - -/** - * @brief Sends an Ethernet frame. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param FrameLength Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) -{ - uint32_t bufcount = 0, size = 0, i = 0; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - if (FrameLength == 0) - { - /* Set ETH HAL state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_ERROR; - } - - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) - { - /* OWN bit set */ - heth->State = HAL_ETH_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_ERROR; - } - - /* Get the number of needed Tx buffers for the current frame */ - if (FrameLength > ETH_TX_BUF_SIZE) - { - bufcount = FrameLength/ETH_TX_BUF_SIZE; - if (FrameLength % ETH_TX_BUF_SIZE) - { - bufcount++; - } - } - else - { - bufcount = 1; - } - if (bufcount == 1) - { - /* Set LAST and FIRST segment */ - heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS; - /* Set frame size */ - heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1); - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - heth->TxDesc->Status |= ETH_DMATXDESC_OWN; - /* Point to next descriptor */ - heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); - } - else - { - for (i=0; i< bufcount; i++) - { - /* Clear FIRST and LAST segment bits */ - heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); - - if (i == 0) - { - /* Setting the first segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_FS; - } - - /* Program size */ - heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); - - if (i == (bufcount-1)) - { - /* Setting the last segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_LS; - size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE; - heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); - } - - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - heth->TxDesc->Status |= ETH_DMATXDESC_OWN; - /* point to next descriptor */ - heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); - } - } - - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - (heth->Instance)->DMASR = ETH_DMASR_TBUS; - /* Resume DMA transmission*/ - (heth->Instance)->DMATPDR = 0; - } - - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Checks for received frames. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) -{ - uint32_t framelength = 0; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Check the ETH state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Check if segment is not owned by DMA */ - /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)) - { - /* Check if last segment */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) - { - /* increment segment count */ - (heth->RxFrameInfos).SegCount++; - - /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos).SegCount == 1) - { - (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; - } - - heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; - heth->RxFrameInfos.length = framelength; - - /* Get the address of the buffer start address */ - heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - /* point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; - } - /* Check if first segment */ - else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) - { - (heth->RxFrameInfos).FSRxDesc = heth->RxDesc; - (heth->RxFrameInfos).LSRxDesc = NULL; - (heth->RxFrameInfos).SegCount = 1; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - /* Check if intermediate segment */ - else - { - (heth->RxFrameInfos).SegCount++; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - } - - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_ERROR; -} - -/** - * @brief Gets the Received frame in interrupt mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) -{ - uint32_t descriptorscancounter = 0; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set ETH HAL State to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Scan descriptors owned by CPU */ - while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB)) - { - /* Just for security */ - descriptorscancounter++; - - /* Check if first segment in frame */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ - if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) - { - heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - heth->RxFrameInfos.SegCount = 1; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - /* Check if intermediate segment */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */ - else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET) - { - /* Increment segment count */ - (heth->RxFrameInfos.SegCount)++; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr); - } - /* Should be last segment */ - else - { - /* Last segment */ - heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - - /* Increment segment count */ - (heth->RxFrameInfos.SegCount)++; - - /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos.SegCount) == 1) - { - heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - } - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; - - /* Get the address of the buffer start address */ - heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; - } - } - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_ERROR; -} - -/** - * @brief This function handles ETH interrupt request. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) -{ - /* Frame received */ - if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) - { -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered Receive complete callback*/ - heth->RxCpltCallback(heth); -#else - /* Receive complete callback */ - HAL_ETH_RxCpltCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the Eth DMA Rx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - } - /* Frame transmitted */ - else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) - { -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /* Call resgistered Transfer complete callback*/ - heth->TxCpltCallback(heth); -#else - /* Transfer complete callback */ - HAL_ETH_TxCpltCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the Eth DMA Tx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - } - - /* Clear the interrupt flags */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS); - - /* ETH DMA Error */ - if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS)) - { -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - heth->DMAErrorCallback(heth); -#else - /* Ethernet Error callback */ - HAL_ETH_ErrorCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the interrupt flags */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - } -} - -/** - * @brief Tx Transfer completed callbacks. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Ethernet transfer error callbacks - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Reads a PHY register - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Basic Control Register, - * PHY_BSR: Transceiver Basic Status Register. - * More PHY register could be read depending on the used PHY - * @param RegValue PHY register value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) -{ - uint32_t tmpreg = 0; - uint32_t tickstart = 0; - - /* Check parameters */ - assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - - /* Check the ETH peripheral state */ - if(heth->State == HAL_ETH_STATE_BUSY_RD) - { - return HAL_BUSY; - } - /* Set ETH HAL State to BUSY_RD */ - heth->State = HAL_ETH_STATE_BUSY_RD; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII address register value */ - tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check for the Busy flag */ - while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > PHY_READ_TO) - { - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - tmpreg = heth->Instance->MACMIIAR; - } - - /* Get MACMIIDR value */ - *RegValue = (uint16_t)(heth->Instance->MACMIIDR); - - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Writes to a PHY register. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Control Register. - * More PHY register could be written depending on the used PHY - * @param RegValue the value to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) -{ - uint32_t tmpreg = 0; - uint32_t tickstart = 0; - - /* Check parameters */ - assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - - /* Check the ETH peripheral state */ - if(heth->State == HAL_ETH_STATE_BUSY_WR) - { - return HAL_BUSY; - } - /* Set ETH HAL State to BUSY_WR */ - heth->State = HAL_ETH_STATE_BUSY_WR; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII register address value */ - tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Give the value to the MII data register */ - heth->Instance->MACMIIDR = (uint16_t)RegValue; - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check for the Busy flag */ - while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) - { - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - tmpreg = heth->Instance->MACMIIAR; - } - - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Enable MAC and DMA transmission and reception. - HAL_ETH_Start(); - (+) Disable MAC and DMA transmission and reception. - HAL_ETH_Stop(); - (+) Set the MAC configuration in runtime mode - HAL_ETH_ConfigMAC(); - (+) Set the DMA configuration in runtime mode - HAL_ETH_ConfigDMA(); - -@endverbatim - * @{ - */ - - /** - * @brief Enables Ethernet MAC and DMA reception/transmission - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) -{ - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Enable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionEnable(heth); - - /* Enable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionEnable(heth); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Start DMA transmission */ - ETH_DMATransmissionEnable(heth); - - /* Start DMA reception */ - ETH_DMAReceptionEnable(heth); - - /* Set the ETH state to READY*/ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) -{ - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Stop DMA transmission */ - ETH_DMATransmissionDisable(heth); - - /* Stop DMA reception */ - ETH_DMAReceptionDisable(heth); - - /* Disable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionDisable(heth); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Disable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionDisable(heth); - - /* Set the ETH state*/ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set ETH MAC Configuration. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param macconf MAC Configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) -{ - uint32_t tmpreg = 0; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State= HAL_ETH_STATE_BUSY; - - assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - - if (macconf != NULL) - { - /* Check the parameters */ - assert_param(IS_ETH_WATCHDOG(macconf->Watchdog)); - assert_param(IS_ETH_JABBER(macconf->Jabber)); - assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap)); - assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense)); - assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn)); - assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode)); - assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload)); - assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission)); - assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip)); - assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit)); - assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck)); - assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll)); - assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter)); - assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames)); - assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception)); - assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter)); - assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode)); - assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter)); - assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter)); - assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime)); - assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause)); - assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold)); - assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect)); - assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl)); - assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); - assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); - assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = (heth->Instance)->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= ETH_MACCR_CLEAR_MASK; - - tmpreg |= (uint32_t)(macconf->Watchdog | - macconf->Jabber | - macconf->InterFrameGap | - macconf->CarrierSense | - (heth->Init).Speed | - macconf->ReceiveOwn | - macconf->LoopbackMode | - (heth->Init).DuplexMode | - macconf->ChecksumOffload | - macconf->RetryTransmission | - macconf->AutomaticPadCRCStrip | - macconf->BackOffLimit | - macconf->DeferralCheck); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | - macconf->SourceAddrFilter | - macconf->PassControlFrames | - macconf->BroadcastFramesReception | - macconf->DestinationAddrFilter | - macconf->PromiscuousMode | - macconf->MulticastFramesFilter | - macconf->UnicastFramesFilter); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFFR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ - /* Write to ETHERNET MACHTHR */ - (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg &= ETH_MACFCR_CLEAR_MASK; - - tmpreg |= (uint32_t)((macconf->PauseTime << 16) | - macconf->ZeroQuantaPause | - macconf->PauseLowThreshold | - macconf->UnicastPauseFrameDetect | - macconf->ReceiveFlowControl | - macconf->TransmitFlowControl); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg; - - /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | - macconf->VLANTagIdentifier); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACVLANTR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg; - } - else /* macconf == NULL : here we just configure Speed and Duplex mode */ - { - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = (heth->Instance)->MACCR; - - /* Clear FES and DM bits */ - tmpreg &= ~((uint32_t)0x00004800); - - tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; - } - - /* Set the ETH state to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Sets ETH DMA Configuration. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param dmaconf DMA Configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) -{ - uint32_t tmpreg = 0; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State= HAL_ETH_STATE_BUSY; - - /* Check parameters */ - assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame)); - assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward)); - assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame)); - assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward)); - assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl)); - assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames)); - assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames)); - assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl)); - assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate)); - assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats)); - assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst)); - assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength)); - assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength)); - assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); - assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); - assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); - - /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ - /* Get the ETHERNET DMAOMR value */ - tmpreg = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg &= ETH_DMAOMR_CLEAR_MASK; - - tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | - dmaconf->ReceiveStoreForward | - dmaconf->FlushReceivedFrame | - dmaconf->TransmitStoreForward | - dmaconf->TransmitThresholdControl | - dmaconf->ForwardErrorFrames | - dmaconf->ForwardUndersizedGoodFrames | - dmaconf->ReceiveThresholdControl | - dmaconf->SecondFrameOperate); - - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg; - - /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | - dmaconf->FixedBurst | - dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmaconf->TxDMABurstLength | - dmaconf->EnhancedDescriptorFormat | - (dmaconf->DescriptorSkipLength << 2) | - dmaconf->DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMABMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg; - - /* Set the ETH state to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * - @verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - (+) Get the ETH handle state: - HAL_ETH_GetState(); - - - @endverbatim - * @{ - */ - -/** - * @brief Return the ETH HAL state - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL state - */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) -{ - /* Return ETH state */ - return heth->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup ETH_Private_Functions - * @{ - */ - -/** - * @brief Configures Ethernet MAC and DMA with default parameters. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param err Ethernet Init error - * @retval HAL status - */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) -{ - ETH_MACInitTypeDef macinit; - ETH_DMAInitTypeDef dmainit; - uint32_t tmpreg = 0; - - if (err != ETH_SUCCESS) /* Auto-negotiation failed */ - { - /* Set Ethernet duplex mode to Full-duplex */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - - /* Set Ethernet speed to 100M */ - (heth->Init).Speed = ETH_SPEED_100M; - } - - /* Ethernet MAC default initialization **************************************/ - macinit.Watchdog = ETH_WATCHDOG_ENABLE; - macinit.Jabber = ETH_JABBER_ENABLE; - macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; - macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; - macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; - macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; - if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; - } - else - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; - } - macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; - macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; - macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; - macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; - macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; - macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; - macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; - macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; - macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; - macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; - macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; - macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; - macinit.HashTableHigh = 0x0; - macinit.HashTableLow = 0x0; - macinit.PauseTime = 0x0; - macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; - macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; - macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; - macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; - macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; - macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; - macinit.VLANTagIdentifier = 0x0; - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = (heth->Instance)->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= ETH_MACCR_CLEAR_MASK; - /* Set the WD bit according to ETH Watchdog value */ - /* Set the JD: bit according to ETH Jabber value */ - /* Set the IFG bit according to ETH InterFrameGap value */ - /* Set the DCRS bit according to ETH CarrierSense value */ - /* Set the FES bit according to ETH Speed value */ - /* Set the DO bit according to ETH ReceiveOwn value */ - /* Set the LM bit according to ETH LoopbackMode value */ - /* Set the DM bit according to ETH Mode value */ - /* Set the IPCO bit according to ETH ChecksumOffload value */ - /* Set the DR bit according to ETH RetryTransmission value */ - /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ - /* Set the BL bit according to ETH BackOffLimit value */ - /* Set the DC bit according to ETH DeferralCheck value */ - tmpreg |= (uint32_t)(macinit.Watchdog | - macinit.Jabber | - macinit.InterFrameGap | - macinit.CarrierSense | - (heth->Init).Speed | - macinit.ReceiveOwn | - macinit.LoopbackMode | - (heth->Init).DuplexMode | - macinit.ChecksumOffload | - macinit.RetryTransmission | - macinit.AutomaticPadCRCStrip | - macinit.BackOffLimit | - macinit.DeferralCheck); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Set the RA bit according to ETH ReceiveAll value */ - /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ - /* Set the PCF bit according to ETH PassControlFrames value */ - /* Set the DBF bit according to ETH BroadcastFramesReception value */ - /* Set the DAIF bit according to ETH DestinationAddrFilter value */ - /* Set the PR bit according to ETH PromiscuousMode value */ - /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ - /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | - macinit.SourceAddrFilter | - macinit.PassControlFrames | - macinit.BroadcastFramesReception | - macinit.DestinationAddrFilter | - macinit.PromiscuousMode | - macinit.MulticastFramesFilter | - macinit.UnicastFramesFilter); - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFFR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ - /* Write to ETHERNET MACHTHR */ - (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration -------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg &= ETH_MACFCR_CLEAR_MASK; - - /* Set the PT bit according to ETH PauseTime value */ - /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ - /* Set the PLT bit according to ETH PauseLowThreshold value */ - /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ - /* Set the RFE bit according to ETH ReceiveFlowControl value */ - /* Set the TFE bit according to ETH TransmitFlowControl value */ - tmpreg |= (uint32_t)((macinit.PauseTime << 16) | - macinit.ZeroQuantaPause | - macinit.PauseLowThreshold | - macinit.UnicastPauseFrameDetect | - macinit.ReceiveFlowControl | - macinit.TransmitFlowControl); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg; - - /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ - /* Set the ETV bit according to ETH VLANTagComparison value */ - /* Set the VL bit according to ETH VLANTagIdentifier value */ - (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | - macinit.VLANTagIdentifier); - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACVLANTR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg; - - /* Ethernet DMA default initialization ************************************/ - dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; - dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; - dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; - dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; - dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; - dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; - dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; - dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; - dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; - dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; - dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; - dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; - dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; - dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; - dmainit.DescriptorSkipLength = 0x0; - dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; - - /* Get the ETHERNET DMAOMR value */ - tmpreg = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg &= ETH_DMAOMR_CLEAR_MASK; - - /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ - /* Set the RSF bit according to ETH ReceiveStoreForward value */ - /* Set the DFF bit according to ETH FlushReceivedFrame value */ - /* Set the TSF bit according to ETH TransmitStoreForward value */ - /* Set the TTC bit according to ETH TransmitThresholdControl value */ - /* Set the FEF bit according to ETH ForwardErrorFrames value */ - /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ - /* Set the RTC bit according to ETH ReceiveThresholdControl value */ - /* Set the OSF bit according to ETH SecondFrameOperate value */ - tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | - dmainit.ReceiveStoreForward | - dmainit.FlushReceivedFrame | - dmainit.TransmitStoreForward | - dmainit.TransmitThresholdControl | - dmainit.ForwardErrorFrames | - dmainit.ForwardUndersizedGoodFrames | - dmainit.ReceiveThresholdControl | - dmainit.SecondFrameOperate); - - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg; - - /*----------------------- ETHERNET DMABMR Configuration ------------------*/ - /* Set the AAL bit according to ETH AddressAlignedBeats value */ - /* Set the FB bit according to ETH FixedBurst value */ - /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ - /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ - /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ - /* Set the DSL bit according to ETH DesciptorSkipLength value */ - /* Set the PR and DA bits according to ETH DMAArbitration value */ - (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | - dmainit.FixedBurst | - dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmainit.TxDMABurstLength | - dmainit.EnhancedDescriptorFormat | - (dmainit.DescriptorSkipLength << 2) | - dmainit.DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMABMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg; - - if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) - { - /* Enable the Ethernet Rx Interrupt */ - __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R); - } - - /* Initialize MAC address in ethernet MAC */ - ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); -} - -/** - * @brief Configures the selected MAC address. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param MacAddr The MAC address to configure - * This parameter can be one of the following values: - * @arg ETH_MAC_Address0: MAC Address0 - * @arg ETH_MAC_Address1: MAC Address1 - * @arg ETH_MAC_Address2: MAC Address2 - * @arg ETH_MAC_Address3: MAC Address3 - * @param Addr Pointer to MAC address buffer data (6 bytes) - * @retval HAL status - */ -static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - - /* Calculate the selected MAC address high register */ - tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; - /* Load the selected MAC address high register */ - (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg; - /* Calculate the selected MAC address low register */ - tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; - - /* Load the selected MAC address low register */ - (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg; -} - -/** - * @brief Enables the MAC transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Enable the MAC transmission */ - (heth->Instance)->MACCR |= ETH_MACCR_TE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; -} - -/** - * @brief Disables the MAC transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Disable the MAC transmission */ - (heth->Instance)->MACCR &= ~ETH_MACCR_TE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; -} - -/** - * @brief Enables the MAC reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Enable the MAC reception */ - (heth->Instance)->MACCR |= ETH_MACCR_RE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; -} - -/** - * @brief Disables the MAC reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Disable the MAC reception */ - (heth->Instance)->MACCR &= ~ETH_MACCR_RE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; -} - -/** - * @brief Enables the DMA transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) -{ - /* Enable the DMA transmission */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; -} - -/** - * @brief Disables the DMA transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) -{ - /* Disable the DMA transmission */ - (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; -} - -/** - * @brief Enables the DMA reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) -{ - /* Enable the DMA reception */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; -} - -/** - * @brief Disables the DMA reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) -{ - /* Disable the DMA reception */ - (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; -} - -/** - * @brief Clears the ETHERNET transmit FIFO. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Set the Flush Transmit FIFO bit */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg; -} - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) -{ - /* Init the ETH Callback settings */ - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ - heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */ -} -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ - -#endif /* ETH */ -#endif /* HAL_ETH_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Inc/main.h b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Inc/main.h index 396d743..d40174e 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Inc/main.h +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Inc/main.h @@ -64,6 +64,8 @@ void Error_Handler(void); #define LED_G_GPIO_Port GPIOH #define LED_B_Pin GPIO_PIN_12 #define LED_B_GPIO_Port GPIOH +#define DISP_Pin GPIO_PIN_4 +#define DISP_GPIO_Port GPIOD #define CTDL_BL_Pin GPIO_PIN_7 #define CTDL_BL_GPIO_Port GPIOD #define WIFI_DISABLE_Pin GPIO_PIN_9 diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h index 9ff4ca8..b30166e 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h @@ -45,7 +45,7 @@ /* #define HAL_DAC_MODULE_ENABLED */ /* #define HAL_DCMI_MODULE_ENABLED */ #define HAL_DMA2D_MODULE_ENABLED -#define HAL_ETH_MODULE_ENABLED +/* #define HAL_ETH_MODULE_ENABLED */ /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ @@ -178,7 +178,7 @@ /* Section 2: PHY configuration section */ /* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 1 +#define DP83848_PHY_ADDRESS 0x01U /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY ((uint32_t)0x000000FFU) /* PHY Configuration delay */ @@ -189,8 +189,8 @@ /* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ #define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ @@ -208,19 +208,10 @@ #define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ /* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x1FU) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ -#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ /* ################## SPI peripheral configuration ########################## */ diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/demo1.uvprojx b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/demo1.uvprojx index babd812..9de34b6 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/demo1.uvprojx +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/demo1.uvprojx @@ -566,11 +566,6 @@ 1 ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c - - stm32f7xx_hal_eth.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c - stm32f7xx_ll_fmc.c 1 diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Src/main.c b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Src/main.c index f8db46d..642e47f 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Src/main.c +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Src/main.c @@ -49,8 +49,6 @@ CRC_HandleTypeDef hcrc; DMA2D_HandleTypeDef hdma2d; -ETH_HandleTypeDef heth; - LTDC_HandleTypeDef hltdc; QSPI_HandleTypeDef hqspi; @@ -76,7 +74,6 @@ static void MX_FMC_Init(void); static void MX_LTDC_Init(void); static void MX_QUADSPI_Init(void); static void MX_USART1_UART_Init(void); -static void MX_ETH_Init(void); static void MX_RTC_Init(void); static void MX_USART3_UART_Init(void); void StartDefaultTask(void const * argument); @@ -201,7 +198,6 @@ int main(void) MX_LTDC_Init(); MX_QUADSPI_Init(); MX_USART1_UART_Init(); - MX_ETH_Init(); MX_RTC_Init(); MX_USART3_UART_Init(); MX_TouchGFX_Init(); @@ -387,48 +383,6 @@ static void MX_DMA2D_Init(void) } -/** - * @brief ETH Initialization Function - * @param None - * @retval None - */ -static void MX_ETH_Init(void) -{ - - /* USER CODE BEGIN ETH_Init 0 */ - - /* USER CODE END ETH_Init 0 */ - - /* USER CODE BEGIN ETH_Init 1 */ - - /* USER CODE END ETH_Init 1 */ - heth.Instance = ETH; - heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE; - heth.Init.PhyAddress = DP83848_PHY_ADDRESS; - heth.Init.MACAddr[0] = 0x00; - heth.Init.MACAddr[1] = 0x80; - heth.Init.MACAddr[2] = 0xE1; - heth.Init.MACAddr[3] = 0x00; - heth.Init.MACAddr[4] = 0x00; - heth.Init.MACAddr[5] = 0x00; - heth.Init.RxMode = ETH_RXPOLLING_MODE; - heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; - heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII; - - /* USER CODE BEGIN MACADDRESS */ - - /* USER CODE END MACADDRESS */ - - if (HAL_ETH_Init(&heth) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ETH_Init 2 */ - - /* USER CODE END ETH_Init 2 */ - -} - /** * @brief LTDC Initialization Function * @param None @@ -702,10 +656,7 @@ static void MX_GPIO_Init(void) HAL_GPIO_WritePin(GPIOH, LED_R_Pin|LED_G_Pin|LED_B_Pin, GPIO_PIN_SET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4, GPIO_PIN_RESET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(CTDL_BL_GPIO_Port, CTDL_BL_Pin, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOD, DISP_Pin|CTDL_BL_Pin, GPIO_PIN_SET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(WIFI_DISABLE_GPIO_Port, WIFI_DISABLE_Pin, GPIO_PIN_RESET); @@ -717,19 +668,12 @@ static void MX_GPIO_Init(void) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - /*Configure GPIO pin : PD4 */ - GPIO_InitStruct.Pin = GPIO_PIN_4; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - /*Configure GPIO pin : CTDL_BL_Pin */ - GPIO_InitStruct.Pin = CTDL_BL_Pin; + /*Configure GPIO pins : DISP_Pin CTDL_BL_Pin */ + GPIO_InitStruct.Pin = DISP_Pin|CTDL_BL_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(CTDL_BL_GPIO_Port, &GPIO_InitStruct); + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); /*Configure GPIO pin : WIFI_DISABLE_Pin */ GPIO_InitStruct.Pin = WIFI_DISABLE_Pin; diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c index 54d12e4..722370b 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c @@ -173,133 +173,6 @@ void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) } -/** -* @brief ETH MSP Initialization -* This function configures the hardware resources used in this example -* @param heth: ETH handle pointer -* @retval None -*/ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(heth->Instance==ETH) - { - /* USER CODE BEGIN ETH_MspInit 0 */ - - /* USER CODE END ETH_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_ETH_CLK_ENABLE(); - - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**ETH GPIO Configuration - PC1 ------> ETH_MDC - PC2 ------> ETH_TXD2 - PC3 ------> ETH_TX_CLK - PA0/WKUP ------> ETH_CRS - PA1 ------> ETH_RX_CLK - PA2 ------> ETH_MDIO - PH3 ------> ETH_COL - PA7 ------> ETH_RX_DV - PC4 ------> ETH_RXD0 - PC5 ------> ETH_RXD1 - PB0 ------> ETH_RXD2 - PB1 ------> ETH_RXD3 - PB11 ------> ETH_TX_EN - PB12 ------> ETH_TXD0 - PB13 ------> ETH_TXD1 - PB8 ------> ETH_TXD3 - */ - GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 - |GPIO_PIN_5; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_11|GPIO_PIN_12 - |GPIO_PIN_13|GPIO_PIN_8; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* USER CODE BEGIN ETH_MspInit 1 */ - - /* USER CODE END ETH_MspInit 1 */ - } - -} - -/** -* @brief ETH MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param heth: ETH handle pointer -* @retval None -*/ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) -{ - if(heth->Instance==ETH) - { - /* USER CODE BEGIN ETH_MspDeInit 0 */ - - /* USER CODE END ETH_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration - PC1 ------> ETH_MDC - PC2 ------> ETH_TXD2 - PC3 ------> ETH_TX_CLK - PA0/WKUP ------> ETH_CRS - PA1 ------> ETH_RX_CLK - PA2 ------> ETH_MDIO - PH3 ------> ETH_COL - PA7 ------> ETH_RX_DV - PC4 ------> ETH_RXD0 - PC5 ------> ETH_RXD1 - PB0 ------> ETH_RXD2 - PB1 ------> ETH_RXD3 - PB11 ------> ETH_TX_EN - PB12 ------> ETH_TXD0 - PB13 ------> ETH_TXD1 - PB8 ------> ETH_TXD3 - */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 - |GPIO_PIN_5); - - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); - - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_3); - - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_11|GPIO_PIN_12 - |GPIO_PIN_13|GPIO_PIN_8); - - /* USER CODE BEGIN ETH_MspDeInit 1 */ - - /* USER CODE END ETH_MspDeInit 1 */ - } - -} - /** * @brief LTDC MSP Initialization * This function configures the hardware resources used in this example @@ -320,20 +193,20 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) __HAL_RCC_GPIOI_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); /**LTDC GPIO Configuration PI9 ------> LTDC_VSYNC PI10 ------> LTDC_HSYNC PF10 ------> LTDC_DE PA3 ------> LTDC_B5 - PH9 ------> LTDC_R3 + PB0 ------> LTDC_R3 + PB1 ------> LTDC_R6 PG6 ------> LTDC_R7 PG7 ------> LTDC_CLK PC7 ------> LTDC_G6 - PA8 ------> LTDC_R6 PA11 ------> LTDC_R4 PA12 ------> LTDC_R5 PH13 ------> LTDC_G2 @@ -342,12 +215,12 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) PI2 ------> LTDC_G7 PG10 ------> LTDC_G3 PG11 ------> LTDC_B3 + PB8 ------> LTDC_B6 PB9 ------> LTDC_B7 - PI4 ------> LTDC_B4 - PI6 ------> LTDC_B6 + PI4 ------> LTDC_B4 */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 - |GPIO_PIN_4|GPIO_PIN_6; + |GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; @@ -361,19 +234,19 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_13|GPIO_PIN_15; + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -389,6 +262,13 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -396,7 +276,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; @@ -434,11 +314,11 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) PI10 ------> LTDC_HSYNC PF10 ------> LTDC_DE PA3 ------> LTDC_B5 - PH9 ------> LTDC_R3 + PB0 ------> LTDC_R3 + PB1 ------> LTDC_R6 PG6 ------> LTDC_R7 PG7 ------> LTDC_CLK PC7 ------> LTDC_G6 - PA8 ------> LTDC_R6 PA11 ------> LTDC_R4 PA12 ------> LTDC_R5 PH13 ------> LTDC_G2 @@ -447,24 +327,24 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) PI2 ------> LTDC_G7 PG10 ------> LTDC_G3 PG11 ------> LTDC_B3 + PB8 ------> LTDC_B6 PB9 ------> LTDC_B7 - PI4 ------> LTDC_B4 - PI6 ------> LTDC_B6 + PI4 ------> LTDC_B4 */ HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 - |GPIO_PIN_4|GPIO_PIN_6); + |GPIO_PIN_4); HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10); - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3|GPIO_PIN_11|GPIO_PIN_12); - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_9|GPIO_PIN_13|GPIO_PIN_15); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_8|GPIO_PIN_9); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7); - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9); + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_13|GPIO_PIN_15); /* LTDC interrupt DeInit */ HAL_NVIC_DisableIRQ(LTDC_IRQn); @@ -500,7 +380,7 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) PF8 ------> QUADSPI_BK1_IO0 PF9 ------> QUADSPI_BK1_IO1 PB2 ------> QUADSPI_CLK - PB10 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -516,13 +396,20 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_10; + GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /* QUADSPI interrupt Init */ HAL_NVIC_SetPriority(QUADSPI_IRQn, 5, 0); HAL_NVIC_EnableIRQ(QUADSPI_IRQn); @@ -555,11 +442,11 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) PF8 ------> QUADSPI_BK1_IO0 PF9 ------> QUADSPI_BK1_IO1 PB2 ------> QUADSPI_CLK - PB10 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9); - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_2|GPIO_PIN_10); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_2|GPIO_PIN_6); /* QUADSPI interrupt DeInit */ HAL_NVIC_DisableIRQ(QUADSPI_IRQn); diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/demo1.ioc b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/demo1.ioc index 0136dc1..5231cc8 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/demo1.ioc +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/CubeMX_Config/demo1.ioc @@ -6,8 +6,6 @@ CORTEX_M7.IPParameters=ART_ACCLERATOR_ENABLE,PREFETCH_ENABLE,CPU_ICache,CPU_DCac CORTEX_M7.PREFETCH_ENABLE=1 DMA2D.ColorMode=DMA2D_OUTPUT_RGB565 DMA2D.IPParameters=ColorMode -ETH.IPParameters=MediaInterface -ETH.MediaInterface=ETH_MEDIA_INTERFACE_MII FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_3 FMC.ExitSelfRefreshDelay1=7 FMC.IPParameters=CASLatency1,SDClockPeriod1,SDClockPeriod2,ReadPipeDelay1,ReadPipeDelay2,ReadBurst1,ReadBurst2,LoadToActiveDelay1,ExitSelfRefreshDelay1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,WriteRecoveryTime1,RPDelay1,RPDelay2,RCDDelay1 @@ -50,26 +48,23 @@ LTDC.WindowY1_L0=480 Mcu.Family=STM32F7 Mcu.IP0=CORTEX_M7 Mcu.IP1=CRC -Mcu.IP10=RTC -Mcu.IP11=SYS -Mcu.IP12=USART1 -Mcu.IP13=USART3 +Mcu.IP10=SYS +Mcu.IP11=USART1 +Mcu.IP12=USART3 Mcu.IP2=DMA2D -Mcu.IP3=ETH -Mcu.IP4=FMC -Mcu.IP5=FREERTOS -Mcu.IP6=LTDC -Mcu.IP7=NVIC -Mcu.IP8=QUADSPI -Mcu.IP9=RCC -Mcu.IPNb=14 +Mcu.IP3=FMC +Mcu.IP4=FREERTOS +Mcu.IP5=LTDC +Mcu.IP6=NVIC +Mcu.IP7=QUADSPI +Mcu.IP8=RCC +Mcu.IP9=RTC +Mcu.IPNb=13 Mcu.Name=STM32F767I(G-I)Tx Mcu.Package=LQFP176 Mcu.Pin0=PC14/OSC32_IN Mcu.Pin1=PC15/OSC32_OUT Mcu.Pin10=PF6 -Mcu.Pin100=VP_SYS_VS_tim6 -Mcu.Pin101=VP_STMicroelectronics.X-CUBE-TOUCHGFX_VS_GraphicsJjApplication_4.13.0 Mcu.Pin11=PF7 Mcu.Pin12=PF8 Mcu.Pin13=PF9 @@ -77,97 +72,83 @@ Mcu.Pin14=PF10 Mcu.Pin15=PH0/OSC_IN Mcu.Pin16=PH1/OSC_OUT Mcu.Pin17=PC0 -Mcu.Pin18=PC1 -Mcu.Pin19=PC2 +Mcu.Pin18=PA3 +Mcu.Pin19=PB0 Mcu.Pin2=PI9 -Mcu.Pin20=PC3 -Mcu.Pin21=PA0/WKUP -Mcu.Pin22=PA1 -Mcu.Pin23=PA2 -Mcu.Pin24=PH3 -Mcu.Pin25=PA3 -Mcu.Pin26=PA7 -Mcu.Pin27=PC4 -Mcu.Pin28=PC5 -Mcu.Pin29=PB0 +Mcu.Pin20=PB1 +Mcu.Pin21=PB2 +Mcu.Pin22=PF11 +Mcu.Pin23=PF12 +Mcu.Pin24=PF13 +Mcu.Pin25=PF14 +Mcu.Pin26=PF15 +Mcu.Pin27=PG0 +Mcu.Pin28=PG1 +Mcu.Pin29=PE7 Mcu.Pin3=PI10 -Mcu.Pin30=PB1 -Mcu.Pin31=PB2 -Mcu.Pin32=PF11 -Mcu.Pin33=PF12 -Mcu.Pin34=PF13 -Mcu.Pin35=PF14 -Mcu.Pin36=PF15 -Mcu.Pin37=PG0 -Mcu.Pin38=PG1 -Mcu.Pin39=PE7 +Mcu.Pin30=PE8 +Mcu.Pin31=PE9 +Mcu.Pin32=PE10 +Mcu.Pin33=PE11 +Mcu.Pin34=PE12 +Mcu.Pin35=PE13 +Mcu.Pin36=PE14 +Mcu.Pin37=PE15 +Mcu.Pin38=PH6 +Mcu.Pin39=PH7 Mcu.Pin4=PF0 -Mcu.Pin40=PE8 -Mcu.Pin41=PE9 -Mcu.Pin42=PE10 -Mcu.Pin43=PE11 -Mcu.Pin44=PE12 -Mcu.Pin45=PE13 -Mcu.Pin46=PE14 -Mcu.Pin47=PE15 -Mcu.Pin48=PB10 -Mcu.Pin49=PB11 +Mcu.Pin40=PH10 +Mcu.Pin41=PH11 +Mcu.Pin42=PH12 +Mcu.Pin43=PD8 +Mcu.Pin44=PD9 +Mcu.Pin45=PD10 +Mcu.Pin46=PD14 +Mcu.Pin47=PD15 +Mcu.Pin48=PG4 +Mcu.Pin49=PG5 Mcu.Pin5=PF1 -Mcu.Pin50=PH6 -Mcu.Pin51=PH7 -Mcu.Pin52=PH9 -Mcu.Pin53=PH10 -Mcu.Pin54=PH11 -Mcu.Pin55=PH12 -Mcu.Pin56=PB12 -Mcu.Pin57=PB13 -Mcu.Pin58=PD8 -Mcu.Pin59=PD9 +Mcu.Pin50=PG6 +Mcu.Pin51=PG7 +Mcu.Pin52=PG8 +Mcu.Pin53=PC7 +Mcu.Pin54=PA9 +Mcu.Pin55=PA10 +Mcu.Pin56=PA11 +Mcu.Pin57=PA12 +Mcu.Pin58=PA13 +Mcu.Pin59=PH13 Mcu.Pin6=PF2 -Mcu.Pin60=PD10 -Mcu.Pin61=PD14 -Mcu.Pin62=PD15 -Mcu.Pin63=PG4 -Mcu.Pin64=PG5 -Mcu.Pin65=PG6 -Mcu.Pin66=PG7 -Mcu.Pin67=PG8 -Mcu.Pin68=PC7 -Mcu.Pin69=PA8 +Mcu.Pin60=PH15 +Mcu.Pin61=PI0 +Mcu.Pin62=PI2 +Mcu.Pin63=PA14 +Mcu.Pin64=PC10 +Mcu.Pin65=PC11 +Mcu.Pin66=PD0 +Mcu.Pin67=PD1 +Mcu.Pin68=PD4 +Mcu.Pin69=PD7 Mcu.Pin7=PF3 -Mcu.Pin70=PA9 -Mcu.Pin71=PA10 -Mcu.Pin72=PA11 -Mcu.Pin73=PA12 -Mcu.Pin74=PA13 -Mcu.Pin75=PH13 -Mcu.Pin76=PH15 -Mcu.Pin77=PI0 -Mcu.Pin78=PI2 -Mcu.Pin79=PA14 +Mcu.Pin70=PG9 +Mcu.Pin71=PG10 +Mcu.Pin72=PG11 +Mcu.Pin73=PG15 +Mcu.Pin74=PB6 +Mcu.Pin75=PB8 +Mcu.Pin76=PB9 +Mcu.Pin77=PE0 +Mcu.Pin78=PE1 +Mcu.Pin79=PI4 Mcu.Pin8=PF4 -Mcu.Pin80=PC10 -Mcu.Pin81=PC11 -Mcu.Pin82=PD0 -Mcu.Pin83=PD1 -Mcu.Pin84=PD4 -Mcu.Pin85=PD7 -Mcu.Pin86=PG9 -Mcu.Pin87=PG10 -Mcu.Pin88=PG11 -Mcu.Pin89=PG15 +Mcu.Pin80=VP_CRC_VS_CRC +Mcu.Pin81=VP_DMA2D_VS_DMA2D +Mcu.Pin82=VP_FREERTOS_VS_CMSIS_V1 +Mcu.Pin83=VP_RTC_VS_RTC_Activate +Mcu.Pin84=VP_SYS_VS_tim6 +Mcu.Pin85=VP_STMicroelectronics.X-CUBE-TOUCHGFX_VS_GraphicsJjApplication_4.13.0 Mcu.Pin9=PF5 -Mcu.Pin90=PB8 -Mcu.Pin91=PB9 -Mcu.Pin92=PE0 -Mcu.Pin93=PE1 -Mcu.Pin94=PI4 -Mcu.Pin95=PI6 -Mcu.Pin96=VP_CRC_VS_CRC -Mcu.Pin97=VP_DMA2D_VS_DMA2D -Mcu.Pin98=VP_FREERTOS_VS_CMSIS_V1 -Mcu.Pin99=VP_RTC_VS_RTC_Activate -Mcu.PinsNb=102 +Mcu.PinsNb=86 Mcu.ThirdParty0=STMicroelectronics.X-CUBE-TOUCHGFX.4.13.0 Mcu.ThirdPartyNb=1 Mcu.UserConstants= @@ -191,10 +172,6 @@ NVIC.TIM6_DAC_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true NVIC.TimeBase=TIM6_DAC_IRQn NVIC.TimeBaseIP=TIM6 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -PA0/WKUP.Mode=MII -PA0/WKUP.Signal=ETH_CRS -PA1.Mode=MII -PA1.Signal=ETH_RX_CLK PA10.Locked=true PA10.Mode=Asynchronous PA10.Signal=USART1_RX @@ -208,54 +185,34 @@ PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA2.Mode=MII -PA2.Signal=ETH_MDIO PA3.Mode=RGB565 PA3.Signal=LTDC_B5 -PA7.Mode=MII -PA7.Signal=ETH_RX_DV -PA8.Mode=RGB565 -PA8.Signal=LTDC_R6 PA9.Locked=true PA9.Mode=Asynchronous PA9.Signal=USART1_TX -PB0.Mode=MII -PB0.Signal=ETH_RXD2 -PB1.Mode=MII -PB1.Signal=ETH_RXD3 -PB10.Mode=Single Bank 1 -PB10.Signal=QUADSPI_BK1_NCS -PB11.Mode=MII -PB11.Signal=ETH_TX_EN -PB12.Mode=MII -PB12.Signal=ETH_TXD0 -PB13.Mode=MII -PB13.Signal=ETH_TXD1 +PB0.Mode=RGB565 +PB0.Signal=LTDC_R3 +PB1.Mode=RGB565 +PB1.Signal=LTDC_R6 PB2.Mode=Single Bank 1 PB2.Signal=QUADSPI_CLK -PB8.Mode=MII -PB8.Signal=ETH_TXD3 +PB6.Mode=Single Bank 1 +PB6.Signal=QUADSPI_BK1_NCS +PB8.Mode=RGB565 +PB8.Signal=LTDC_B6 PB9.Mode=RGB565 PB9.Signal=LTDC_B7 PC0.Signal=FMC_SDNWE -PC1.Mode=MII -PC1.Signal=ETH_MDC +PC10.Locked=true PC10.Mode=Asynchronous PC10.Signal=USART3_TX +PC11.Locked=true PC11.Mode=Asynchronous PC11.Signal=USART3_RX PC14/OSC32_IN.Mode=LSE-External-Oscillator PC14/OSC32_IN.Signal=RCC_OSC32_IN PC15/OSC32_OUT.Mode=LSE-External-Oscillator PC15/OSC32_OUT.Signal=RCC_OSC32_OUT -PC2.Mode=MII -PC2.Signal=ETH_TXD2 -PC3.Mode=MII -PC3.Signal=ETH_TX_CLK -PC4.Mode=MII -PC4.Signal=ETH_RXD0 -PC5.Mode=MII -PC5.Signal=ETH_RXD1 PC7.Locked=true PC7.Mode=RGB565 PC7.Signal=LTDC_G6 @@ -264,7 +221,12 @@ PD1.Signal=FMC_D3_DA3 PD10.Signal=FMC_D15_DA15 PD14.Signal=FMC_D0_DA0 PD15.Signal=FMC_D1_DA1 +PD4.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label +PD4.GPIO_Label=DISP +PD4.GPIO_PuPd=GPIO_PULLUP +PD4.GPIO_Speed=GPIO_SPEED_FREQ_HIGH PD4.Locked=true +PD4.PinState=GPIO_PIN_SET PD4.Signal=GPIO_Output PD7.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label PD7.GPIO_Label=CTDL_BL @@ -354,14 +316,10 @@ PH13.Signal=LTDC_G2 PH15.Locked=true PH15.Mode=RGB565 PH15.Signal=LTDC_G4 -PH3.Mode=MII -PH3.Signal=ETH_COL PH6.Mode=SdramChipSelect2_1 PH6.Signal=FMC_SDNE1 PH7.Mode=SdramChipSelect2_1 PH7.Signal=FMC_SDCKE1 -PH9.Mode=RGB565 -PH9.Signal=LTDC_R3 PI0.Locked=true PI0.Mode=RGB565 PI0.Signal=LTDC_G5 @@ -372,8 +330,6 @@ PI2.Signal=LTDC_G7 PI4.Locked=true PI4.Mode=RGB565 PI4.Signal=LTDC_B4 -PI6.Mode=RGB565 -PI6.Signal=LTDC_B6 PI9.Mode=RGB565 PI9.Signal=LTDC_VSYNC PinOutPanel.RotationAngle=0 diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/Kconfig b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/Kconfig index 32829b2..6ed8d4c 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/Kconfig +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/board/Kconfig @@ -44,18 +44,12 @@ menu "Onboard Peripheral Drivers" select BSP_USING_SDRAM default n - config BSP_USING_ETH - bool "Enable Ethernet" - select RT_USING_LWIP - select PHY_USING_LAN8720A - default n - config BSP_USING_MPU6050 bool "Enable MPU6050 (i2c4)" select BSP_USING_I2C4 select PKG_USING_MPU6XXX default n - + config BSP_USING_POT bool "Enable potentiometer" select BSP_USING_ADC diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/project.uvoptx b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/project.uvoptx index 1aede04..89b4f5a 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/project.uvoptx +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/project.uvoptx @@ -380,41 +380,17 @@ 0 0 - - 2 - 16 - 1 - 0 - 0 - 0 - applications\gtxx_ccollect.c - gtxx_ccollect.c - 0 - 0 - - - 2 - 17 - 1 - 0 - 0 - 0 - applications\sht30_ccollect.c - sht30_ccollect.c - 0 - 0 - Drivers - 1 + 0 0 0 0 3 - 18 + 16 1 0 0 @@ -426,7 +402,7 @@ 3 - 19 + 17 1 0 0 @@ -438,19 +414,7 @@ 3 - 20 - 1 - 0 - 0 - 0 - board\ports\phy_reset.c - phy_reset.c - 0 - 0 - - - 3 - 21 + 18 1 0 0 @@ -462,7 +426,7 @@ 3 - 22 + 19 2 0 0 @@ -474,7 +438,7 @@ 3 - 23 + 20 1 0 0 @@ -486,7 +450,7 @@ 3 - 24 + 21 1 0 0 @@ -498,7 +462,7 @@ 3 - 25 + 22 1 0 0 @@ -510,7 +474,7 @@ 3 - 26 + 23 1 0 0 @@ -522,19 +486,7 @@ 3 - 27 - 1 - 0 - 0 - 0 - libraries\HAL_Drivers\drv_eth.c - drv_eth.c - 0 - 0 - - - 3 - 28 + 24 1 0 0 @@ -546,7 +498,7 @@ 3 - 29 + 25 1 0 0 @@ -558,7 +510,7 @@ 3 - 30 + 26 1 0 0 @@ -578,7 +530,7 @@ 0 4 - 31 + 27 1 0 0 @@ -590,7 +542,7 @@ 4 - 32 + 28 8 0 0 @@ -602,7 +554,7 @@ 4 - 33 + 29 8 0 0 @@ -614,7 +566,7 @@ 4 - 34 + 30 8 0 0 @@ -626,7 +578,7 @@ 4 - 35 + 31 8 0 0 @@ -638,7 +590,7 @@ 4 - 36 + 32 8 0 0 @@ -650,7 +602,7 @@ 4 - 37 + 33 8 0 0 @@ -662,7 +614,7 @@ 4 - 38 + 34 8 0 0 @@ -674,7 +626,7 @@ 4 - 39 + 35 1 0 0 @@ -686,7 +638,7 @@ 4 - 40 + 36 4 0 0 @@ -706,7 +658,7 @@ 0 5 - 41 + 37 8 0 0 @@ -718,7 +670,7 @@ 5 - 42 + 38 8 0 0 @@ -730,7 +682,7 @@ 5 - 43 + 39 8 0 0 @@ -742,7 +694,7 @@ 5 - 44 + 40 8 0 0 @@ -754,7 +706,7 @@ 5 - 45 + 41 8 0 0 @@ -766,7 +718,7 @@ 5 - 46 + 42 8 0 0 @@ -778,7 +730,7 @@ 5 - 47 + 43 8 0 0 @@ -790,7 +742,7 @@ 5 - 48 + 44 8 0 0 @@ -802,7 +754,7 @@ 5 - 49 + 45 8 0 0 @@ -814,7 +766,7 @@ 5 - 50 + 46 8 0 0 @@ -826,7 +778,7 @@ 5 - 51 + 47 8 0 0 @@ -838,7 +790,7 @@ 5 - 52 + 48 8 0 0 @@ -850,7 +802,7 @@ 5 - 53 + 49 8 0 0 @@ -862,7 +814,7 @@ 5 - 54 + 50 8 0 0 @@ -874,7 +826,7 @@ 5 - 55 + 51 8 0 0 @@ -886,7 +838,7 @@ 5 - 56 + 52 8 0 0 @@ -898,7 +850,7 @@ 5 - 57 + 53 8 0 0 @@ -910,7 +862,7 @@ 5 - 58 + 54 8 0 0 @@ -930,7 +882,7 @@ 0 6 - 59 + 55 8 0 0 @@ -942,7 +894,7 @@ 6 - 60 + 56 8 0 0 @@ -954,7 +906,7 @@ 6 - 61 + 57 8 0 0 @@ -966,7 +918,7 @@ 6 - 62 + 58 8 0 0 @@ -986,7 +938,7 @@ 0 7 - 63 + 59 1 0 0 @@ -998,7 +950,7 @@ 7 - 64 + 60 1 0 0 @@ -1010,7 +962,7 @@ 7 - 65 + 61 1 0 0 @@ -1022,7 +974,7 @@ 7 - 66 + 62 1 0 0 @@ -1042,7 +994,7 @@ 0 8 - 67 + 63 1 0 0 @@ -1062,7 +1014,7 @@ 0 9 - 68 + 64 1 0 0 @@ -1082,7 +1034,7 @@ 0 10 - 69 + 65 1 0 0 @@ -1102,7 +1054,7 @@ 0 11 - 70 + 66 1 0 0 @@ -1114,7 +1066,7 @@ 11 - 71 + 67 1 0 0 @@ -1126,7 +1078,7 @@ 11 - 72 + 68 1 0 0 @@ -1138,7 +1090,7 @@ 11 - 73 + 69 1 0 0 @@ -1150,7 +1102,7 @@ 11 - 74 + 70 1 0 0 @@ -1162,7 +1114,7 @@ 11 - 75 + 71 2 0 0 @@ -1182,7 +1134,7 @@ 0 12 - 76 + 72 8 0 0 @@ -1194,7 +1146,7 @@ 12 - 77 + 73 8 0 0 @@ -1206,7 +1158,7 @@ 12 - 78 + 74 8 0 0 @@ -1218,7 +1170,7 @@ 12 - 79 + 75 8 0 0 @@ -1230,7 +1182,7 @@ 12 - 80 + 76 1 0 0 @@ -1250,7 +1202,7 @@ 0 13 - 81 + 77 1 0 0 @@ -1262,7 +1214,7 @@ 13 - 82 + 78 1 0 0 @@ -1274,7 +1226,7 @@ 13 - 83 + 79 1 0 0 @@ -1286,7 +1238,7 @@ 13 - 84 + 80 1 0 0 @@ -1298,7 +1250,7 @@ 13 - 85 + 81 1 0 0 @@ -1310,7 +1262,7 @@ 13 - 86 + 82 1 0 0 @@ -1322,7 +1274,7 @@ 13 - 87 + 83 1 0 0 @@ -1342,7 +1294,7 @@ 0 14 - 88 + 84 1 0 0 @@ -1354,7 +1306,7 @@ 14 - 89 + 85 1 0 0 @@ -1366,7 +1318,7 @@ 14 - 90 + 86 1 0 0 @@ -1378,7 +1330,7 @@ 14 - 91 + 87 1 0 0 @@ -1390,7 +1342,7 @@ 14 - 92 + 88 1 0 0 @@ -1402,7 +1354,7 @@ 14 - 93 + 89 1 0 0 @@ -1414,7 +1366,7 @@ 14 - 94 + 90 1 0 0 @@ -1426,7 +1378,7 @@ 14 - 95 + 91 1 0 0 @@ -1438,7 +1390,7 @@ 14 - 96 + 92 1 0 0 @@ -1450,7 +1402,7 @@ 14 - 97 + 93 1 0 0 @@ -1462,7 +1414,7 @@ 14 - 98 + 94 1 0 0 @@ -1474,7 +1426,7 @@ 14 - 99 + 95 1 0 0 @@ -1486,7 +1438,7 @@ 14 - 100 + 96 1 0 0 @@ -1498,7 +1450,7 @@ 14 - 101 + 97 1 0 0 @@ -1510,7 +1462,7 @@ 14 - 102 + 98 1 0 0 @@ -1530,7 +1482,7 @@ 0 15 - 103 + 99 1 0 0 @@ -1550,7 +1502,7 @@ 0 16 - 104 + 100 1 0 0 @@ -1562,7 +1514,7 @@ 16 - 105 + 101 1 0 0 @@ -1574,7 +1526,7 @@ 16 - 106 + 102 1 0 0 @@ -1586,7 +1538,7 @@ 16 - 107 + 103 1 0 0 @@ -1606,7 +1558,7 @@ 0 17 - 108 + 104 1 0 0 @@ -1618,7 +1570,7 @@ 17 - 109 + 105 1 0 0 @@ -1630,7 +1582,7 @@ 17 - 110 + 106 1 0 0 @@ -1642,7 +1594,7 @@ 17 - 111 + 107 1 0 0 @@ -1654,7 +1606,7 @@ 17 - 112 + 108 1 0 0 @@ -1674,7 +1626,7 @@ 0 18 - 113 + 109 1 0 0 @@ -1686,7 +1638,7 @@ 18 - 114 + 110 1 0 0 @@ -1698,7 +1650,7 @@ 18 - 115 + 111 1 0 0 @@ -1710,7 +1662,7 @@ 18 - 116 + 112 1 0 0 @@ -1722,458 +1674,6 @@ - - lwIP - 1 - 0 - 0 - 0 - - 19 - 117 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\arch\sys_arch.c - sys_arch.c - 0 - 0 - - - 19 - 118 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\api\api_lib.c - api_lib.c - 0 - 0 - - - 19 - 119 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\api\api_msg.c - api_msg.c - 0 - 0 - - - 19 - 120 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\api\err.c - err.c - 0 - 0 - - - 19 - 121 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\api\netbuf.c - netbuf.c - 0 - 0 - - - 19 - 122 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\api\netdb.c - netdb.c - 0 - 0 - - - 19 - 123 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\api\netifapi.c - netifapi.c - 0 - 0 - - - 19 - 124 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\api\sockets.c - sockets.c - 0 - 0 - - - 19 - 125 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\api\tcpip.c - tcpip.c - 0 - 0 - - - 19 - 126 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\def.c - def.c - 0 - 0 - - - 19 - 127 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\dns.c - dns.c - 0 - 0 - - - 19 - 128 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\inet_chksum.c - inet_chksum.c - 0 - 0 - - - 19 - 129 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\init.c - init.c - 0 - 0 - - - 19 - 130 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\ip.c - ip.c - 0 - 0 - - - 19 - 131 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\memp.c - memp.c - 0 - 0 - - - 19 - 132 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\netif.c - netif.c - 0 - 0 - - - 19 - 133 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\pbuf.c - pbuf.c - 0 - 0 - - - 19 - 134 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\raw.c - raw.c - 0 - 0 - - - 19 - 135 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\stats.c - stats.c - 0 - 0 - - - 19 - 136 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\sys.c - sys.c - 0 - 0 - - - 19 - 137 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\tcp.c - tcp.c - 0 - 0 - - - 19 - 138 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\tcp_in.c - tcp_in.c - 0 - 0 - - - 19 - 139 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\tcp_out.c - tcp_out.c - 0 - 0 - - - 19 - 140 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\timeouts.c - timeouts.c - 0 - 0 - - - 19 - 141 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\udp.c - udp.c - 0 - 0 - - - 19 - 142 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\netif\ethernet.c - ethernet.c - 0 - 0 - - - 19 - 143 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\netif\ethernetif.c - ethernetif.c - 0 - 0 - - - 19 - 144 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\netif\lowpan6.c - lowpan6.c - 0 - 0 - - - 19 - 145 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - autoip.c - 0 - 0 - - - 19 - 146 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - dhcp.c - 0 - 0 - - - 19 - 147 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - etharp.c - 0 - 0 - - - 19 - 148 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - icmp.c - 0 - 0 - - - 19 - 149 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - igmp.c - 0 - 0 - - - 19 - 150 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - ip4.c - 0 - 0 - - - 19 - 151 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - ip4_addr.c - 0 - 0 - - - 19 - 152 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c - ip4_frag.c - 0 - 0 - - - 19 - 153 - 1 - 0 - 0 - 0 - rt-thread\components\net\lwip-2.0.2\src\apps\ping\ping.c - ping.c - 0 - 0 - - - netdev 0 @@ -2181,8 +1681,8 @@ 0 0 - 20 - 154 + 19 + 113 1 0 0 @@ -2193,8 +1693,8 @@ 0 - 20 - 155 + 19 + 114 1 0 0 @@ -2213,8 +1713,8 @@ 0 0 - 21 - 156 + 20 + 115 1 0 0 @@ -2225,8 +1725,8 @@ 0 - 21 - 157 + 20 + 116 1 0 0 @@ -2237,20 +1737,8 @@ 0 - 21 - 158 - 1 - 0 - 0 - 0 - rt-thread\components\net\sal_socket\impl\af_inet_lwip.c - af_inet_lwip.c - 0 - 0 - - - 21 - 159 + 20 + 117 1 0 0 @@ -2261,8 +1749,8 @@ 0 - 21 - 160 + 20 + 118 1 0 0 @@ -2273,8 +1761,8 @@ 0 - 21 - 161 + 20 + 119 1 0 0 @@ -2293,8 +1781,8 @@ 0 0 - 22 - 162 + 21 + 120 1 0 0 @@ -2305,8 +1793,8 @@ 0 - 22 - 163 + 21 + 121 1 0 0 @@ -2325,8 +1813,8 @@ 0 0 - 23 - 164 + 22 + 122 1 0 0 @@ -2337,8 +1825,8 @@ 0 - 23 - 165 + 22 + 123 1 0 0 @@ -2349,8 +1837,8 @@ 0 - 23 - 166 + 22 + 124 1 0 0 @@ -2361,8 +1849,8 @@ 0 - 23 - 167 + 22 + 125 1 0 0 @@ -2373,8 +1861,8 @@ 0 - 23 - 168 + 22 + 126 1 0 0 @@ -2385,8 +1873,8 @@ 0 - 23 - 169 + 22 + 127 1 0 0 @@ -2397,8 +1885,8 @@ 0 - 23 - 170 + 22 + 128 1 0 0 @@ -2409,8 +1897,8 @@ 0 - 23 - 171 + 22 + 129 1 0 0 @@ -2421,8 +1909,8 @@ 0 - 23 - 172 + 22 + 130 1 0 0 @@ -2433,8 +1921,8 @@ 0 - 23 - 173 + 22 + 131 1 0 0 @@ -2445,8 +1933,8 @@ 0 - 23 - 174 + 22 + 132 1 0 0 @@ -2457,8 +1945,8 @@ 0 - 23 - 175 + 22 + 133 1 0 0 @@ -2469,8 +1957,8 @@ 0 - 23 - 176 + 22 + 134 1 0 0 @@ -2481,8 +1969,8 @@ 0 - 23 - 177 + 22 + 135 1 0 0 @@ -2493,8 +1981,8 @@ 0 - 23 - 178 + 22 + 136 1 0 0 @@ -2505,8 +1993,8 @@ 0 - 23 - 179 + 22 + 137 1 0 0 @@ -2517,8 +2005,8 @@ 0 - 23 - 180 + 22 + 138 1 0 0 @@ -2529,8 +2017,8 @@ 0 - 23 - 181 + 22 + 139 1 0 0 @@ -2541,8 +2029,8 @@ 0 - 23 - 182 + 22 + 140 1 0 0 @@ -2553,8 +2041,8 @@ 0 - 23 - 183 + 22 + 141 1 0 0 @@ -2565,8 +2053,8 @@ 0 - 23 - 184 + 22 + 142 1 0 0 @@ -2577,8 +2065,8 @@ 0 - 23 - 185 + 22 + 143 1 0 0 @@ -2589,8 +2077,8 @@ 0 - 23 - 186 + 22 + 144 1 0 0 @@ -2601,8 +2089,8 @@ 0 - 23 - 187 + 22 + 145 1 0 0 @@ -2613,8 +2101,8 @@ 0 - 23 - 188 + 22 + 146 1 0 0 @@ -2625,8 +2113,8 @@ 0 - 23 - 189 + 22 + 147 1 0 0 @@ -2637,20 +2125,8 @@ 0 - 23 - 190 - 1 - 0 - 0 - 0 - libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c - stm32f7xx_hal_eth.c - 0 - 0 - - - 23 - 191 + 22 + 148 1 0 0 @@ -2661,8 +2137,8 @@ 0 - 23 - 192 + 22 + 149 1 0 0 @@ -2673,8 +2149,8 @@ 0 - 23 - 193 + 22 + 150 1 0 0 @@ -2685,8 +2161,8 @@ 0 - 23 - 194 + 22 + 151 1 0 0 @@ -2697,8 +2173,8 @@ 0 - 23 - 195 + 22 + 152 1 0 0 @@ -2709,8 +2185,8 @@ 0 - 23 - 196 + 22 + 153 1 0 0 @@ -2721,8 +2197,8 @@ 0 - 23 - 197 + 22 + 154 1 0 0 @@ -2733,8 +2209,8 @@ 0 - 23 - 198 + 22 + 155 1 0 0 diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/project.uvprojx b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/project.uvprojx index 12a55c9..160a954 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/project.uvprojx +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/project.uvprojx @@ -338,7 +338,7 @@ STM32F767xx, USE_HAL_DRIVER, RT_USING_ARM_LIBC - .;rt-thread\include;applications;.;board;board\CubeMX_Config\Inc;board\ports;libraries\HAL_Drivers;libraries\HAL_Drivers\config;board\CubeMX_Config\Src;board\CubeMX_Config\Middlewares\ST\touchgfx\framework\include;board\CubeMX_Config\Src\generated\fonts\include;board\CubeMX_Config\Src\generated\gui_generated\include;board\CubeMX_Config\Src\generated\images\include;board\CubeMX_Config\Src\generated\texts\include;board\CubeMX_Config\Src\gui\include;packages\at_device-latest\inc;packages\at_device-latest\class\esp8266;packages\gt9147-latest\inc;packages\netutils-latest\ntp;packages\sht3x-latest;rt-thread\libcpu\arm\common;rt-thread\libcpu\arm\cortex-m7;rt-thread\components\cplusplus;rt-thread\components\dfs\include;rt-thread\components\dfs\filesystems\devfs;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\spi;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\touch;rt-thread\components\drivers\include;rt-thread\components\finsh;rt-thread\components\libc\compilers\armlibc;rt-thread\components\libc\compilers\common;rt-thread\components\net\at\include;rt-thread\components\net\at\at_socket;rt-thread\components\net\lwip-2.0.2\src;rt-thread\components\net\lwip-2.0.2\src\include;rt-thread\components\net\lwip-2.0.2\src\include\ipv4;rt-thread\components\net\lwip-2.0.2\src\arch\include;rt-thread\components\net\lwip-2.0.2\src\include\netif;rt-thread\components\net\netdev\include;rt-thread\components\net\sal_socket\include;rt-thread\components\net\sal_socket\include\socket;rt-thread\components\net\sal_socket\impl;rt-thread\components\net\sal_socket\include\dfs_net;rt-thread\components\net\sal_socket\include\dfs_net\sys_select;rt-thread\components\net\sal_socket\include\socket\sys_socket;rt-thread\components\utilities\ulog;libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Inc;libraries\STM32F7xx_HAL\CMSIS\Device\ST\STM32F7xx\Include;libraries\STM32F7xx_HAL\CMSIS\Include + .;rt-thread\include;applications;.;board;board\CubeMX_Config\Inc;board\ports;libraries\HAL_Drivers;libraries\HAL_Drivers\config;board\CubeMX_Config\Src;board\CubeMX_Config\Middlewares\ST\touchgfx\framework\include;board\CubeMX_Config\Src\generated\fonts\include;board\CubeMX_Config\Src\generated\gui_generated\include;board\CubeMX_Config\Src\generated\images\include;board\CubeMX_Config\Src\generated\texts\include;board\CubeMX_Config\Src\gui\include;packages\at_device-latest\inc;packages\at_device-latest\class\esp8266;packages\gt9147-latest\inc;packages\netutils-latest\ntp;packages\sht3x-latest;rt-thread\libcpu\arm\common;rt-thread\libcpu\arm\cortex-m7;rt-thread\components\cplusplus;rt-thread\components\dfs\include;rt-thread\components\dfs\filesystems\devfs;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\spi;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\touch;rt-thread\components\drivers\include;rt-thread\components\finsh;rt-thread\components\libc\compilers\armlibc;rt-thread\components\libc\compilers\common;rt-thread\components\net\at\include;rt-thread\components\net\at\at_socket;rt-thread\components\net\netdev\include;rt-thread\components\net\sal_socket\include;rt-thread\components\net\sal_socket\include\socket;rt-thread\components\net\sal_socket\impl;rt-thread\components\net\sal_socket\include\dfs_net;rt-thread\components\net\sal_socket\include\dfs_net\sys_select;rt-thread\components\net\sal_socket\include\socket\sys_socket;rt-thread\components\utilities\ulog;libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Inc;libraries\STM32F7xx_HAL\CMSIS\Device\ST\STM32F7xx\Include;libraries\STM32F7xx_HAL\CMSIS\Include @@ -462,16 +462,6 @@ 1 applications\main.c - - gtxx_ccollect.c - 1 - applications\gtxx_ccollect.c - - - sht30_ccollect.c - 1 - applications\sht30_ccollect.c - @@ -487,11 +477,6 @@ 1 board\CubeMX_Config\Src\stm32f7xx_hal_msp.c - - phy_reset.c - 1 - board\ports\phy_reset.c - qspi_memorymapped.c 1 @@ -522,11 +507,6 @@ 1 libraries\HAL_Drivers\drv_soft_i2c.c - - drv_eth.c - 1 - libraries\HAL_Drivers\drv_eth.c - drv_sdram.c 1 @@ -927,7 +907,7 @@ - + @@ -1118,196 +1098,6 @@ - - lwIP - - - sys_arch.c - 1 - rt-thread\components\net\lwip-2.0.2\src\arch\sys_arch.c - - - api_lib.c - 1 - rt-thread\components\net\lwip-2.0.2\src\api\api_lib.c - - - api_msg.c - 1 - rt-thread\components\net\lwip-2.0.2\src\api\api_msg.c - - - err.c - 1 - rt-thread\components\net\lwip-2.0.2\src\api\err.c - - - netbuf.c - 1 - rt-thread\components\net\lwip-2.0.2\src\api\netbuf.c - - - netdb.c - 1 - rt-thread\components\net\lwip-2.0.2\src\api\netdb.c - - - netifapi.c - 1 - rt-thread\components\net\lwip-2.0.2\src\api\netifapi.c - - - sockets.c - 1 - rt-thread\components\net\lwip-2.0.2\src\api\sockets.c - - - tcpip.c - 1 - rt-thread\components\net\lwip-2.0.2\src\api\tcpip.c - - - def.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\def.c - - - dns.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\dns.c - - - inet_chksum.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\inet_chksum.c - - - init.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\init.c - - - ip.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\ip.c - - - memp.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\memp.c - - - netif.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\netif.c - - - pbuf.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\pbuf.c - - - raw.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\raw.c - - - stats.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\stats.c - - - sys.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\sys.c - - - tcp.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\tcp.c - - - tcp_in.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\tcp_in.c - - - tcp_out.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\tcp_out.c - - - timeouts.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\timeouts.c - - - udp.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\udp.c - - - ethernet.c - 1 - rt-thread\components\net\lwip-2.0.2\src\netif\ethernet.c - - - ethernetif.c - 1 - rt-thread\components\net\lwip-2.0.2\src\netif\ethernetif.c - - - lowpan6.c - 1 - rt-thread\components\net\lwip-2.0.2\src\netif\lowpan6.c - - - autoip.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - - - dhcp.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - - - etharp.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - - - icmp.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - - - igmp.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - - - ip4.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - - - ip4_addr.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - - - ip4_frag.c - 1 - rt-thread\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c - - - ping.c - 1 - rt-thread\components\net\lwip-2.0.2\src\apps\ping\ping.c - - - netdev @@ -1336,11 +1126,6 @@ 1 rt-thread\components\net\sal_socket\socket\net_netdb.c - - af_inet_lwip.c - 1 - rt-thread\components\net\sal_socket\impl\af_inet_lwip.c - af_inet_at.c 1 @@ -1506,11 +1291,6 @@ 1 libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_qspi.c - - stm32f7xx_hal_eth.c - 1 - libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c - stm32f7xx_hal_rtc.c 1 diff --git a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/rtconfig.h b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/rtconfig.h index 62e85d4..73ee05d 100644 --- a/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/rtconfig.h +++ b/demo/3_STM32F767_RTThread_TouchGFX/4_rtthread_TouchGFX_iot/stm32f767-fire-challenger/rtconfig.h @@ -90,7 +90,7 @@ #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL -#define RT_SERIAL_RB_BUFSZ 128 +#define RT_SERIAL_RB_BUFSZ 512 #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN @@ -117,7 +117,6 @@ /* protocol stack implement */ -#define SAL_USING_LWIP #define SAL_USING_AT #define SAL_USING_POSIX @@ -133,45 +132,6 @@ /* light weight TCP/IP stack */ -#define RT_USING_LWIP -#define RT_USING_LWIP202 -#define RT_LWIP_IGMP -#define RT_LWIP_ICMP -#define RT_LWIP_DNS -#define RT_LWIP_DHCP -#define IP_SOF_BROADCAST 1 -#define IP_SOF_BROADCAST_RECV 1 - -/* Static IPv4 Address */ - -#define RT_LWIP_IPADDR "192.168.1.30" -#define RT_LWIP_GWADDR "192.168.1.1" -#define RT_LWIP_MSKADDR "255.255.255.0" -#define RT_LWIP_UDP -#define RT_LWIP_TCP -#define RT_LWIP_RAW -#define RT_MEMP_NUM_NETCONN 8 -#define RT_LWIP_PBUF_NUM 16 -#define RT_LWIP_RAW_PCB_NUM 4 -#define RT_LWIP_UDP_PCB_NUM 4 -#define RT_LWIP_TCP_PCB_NUM 4 -#define RT_LWIP_TCP_SEG_NUM 40 -#define RT_LWIP_TCP_SND_BUF 8196 -#define RT_LWIP_TCP_WND 8196 -#define RT_LWIP_TCPTHREAD_PRIORITY 10 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_PRIORITY 12 -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 -#define LWIP_NETIF_STATUS_CALLBACK 1 -#define LWIP_NETIF_LINK_CALLBACK 1 -#define SO_REUSE 1 -#define LWIP_SO_RCVTIMEO 1 -#define LWIP_SO_SNDTIMEO 1 -#define LWIP_SO_RCVBUF 1 -#define LWIP_NETIF_LOOPBACK 0 -#define RT_LWIP_USING_PING /* AT commands */ @@ -180,7 +140,7 @@ #define AT_CLIENT_NUM_MAX 1 #define AT_USING_SOCKET #define AT_USING_CLI -#define AT_CMD_MAX_LEN 512 +#define AT_CMD_MAX_LEN 128 #define AT_SW_VERSION_NUM 0x10300 /* VBUS(Virtual Software BUS) */ @@ -227,8 +187,8 @@ #define AT_DEVICE_USING_ESP8266 #define AT_DEVICE_ESP8266_INIT_ASYN #define AT_DEVICE_ESP8266_SAMPLE -#define ESP8266_SAMPLE_WIFI_SSID "ChinaNet-ssssss" -#define ESP8266_SAMPLE_WIFI_PASSWORD "SQHWLK9394" +#define ESP8266_SAMPLE_WIFI_SSID "xgld1" +#define ESP8266_SAMPLE_WIFI_PASSWORD "xgld64627816" #define ESP8266_SAMPLE_CLIENT_NAME "uart3" #define ESP8266_SAMPLE_RECV_BUFF_LEN 512 #define PKG_USING_AT_DEVICE_LATEST_VERSION @@ -277,8 +237,7 @@ #define BSP_USING_USB_TO_USART #define BSP_USING_SDRAM #define BSP_USING_QSPI_MemoryMapped -#define BSP_USING_ETH -#define PHY_USING_LAN8720A + /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO