GitHub/qpc
1
0
Fork 0
mirror of https://github.com/QuantumLeaps/qpc.git synced 2025-01-28 07:03:10 +08:00
Code Issues Projects Releases Wiki Activity

7.2.0

Browse Source 
Update qf_port.c
This commit is contained in:
MMS 2022-12-20 17:02:45 -05:00
parent e032055963
commit 417c334876
482 changed files with 20793 additions and 12256 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
3rd_party

@ -1 +1 @@
Subproject commit cc0333938b9618b5a25394ebd81c8f235f5ff192
Subproject commit fa06969955bfa96cbdb5b9ff8b05b66f49fad890

20
doxygen/Doxyfile
View File

@ -7,7 +7,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = QP/C
PROJECT_NUMBER = 7.1.3
PROJECT_NUMBER = 7.2.0
PROJECT_BRIEF = "Real-Time Embedded Framework"
PROJECT_LOGO = ../../ql-doxygen/images/logo_ql.png
OUTPUT_DIRECTORY =
@ -149,6 +149,7 @@ INPUT = main.dox \
config.h \
../include \
../src \
../ports/sample \
../ports/lint-plus/std.lnt \
../ports/lint-plus/qpc.lnt \
../ports/lint-plus/options.lnt
@ -163,8 +164,7 @@ FILE_PATTERNS = *.dox \
*.asm \
*.lnt
RECURSIVE = YES
EXCLUDE = ../include/qs_dummy.h \
../include/quit.h
EXCLUDE = ../include/qs_dummy.h
EXCLUDE_SYMLINKS = NO
EXCLUDE_PATTERNS =
EXCLUDE_SYMBOLS = QP_IMPL
@ -285,11 +285,12 @@ ENABLE_PREPROCESSING = YES
MACRO_EXPANSION = NO
EXPAND_ONLY_PREDEF = NO
SEARCH_INCLUDES = YES
INCLUDE_PATH =
INCLUDE_FILE_PATTERNS =
INCLUDE_PATH = .
INCLUDE_FILE_PATTERNS = *.h
PREDEFINED = Q_SPY \
QP_IMPL \
Q_UTEST \
QP_IMPL \
Q_EVT_CTOR \
QF_MAX_ACTIVE=32 \
QF_MAX_TICK_RATE=2 \
QF_MAX_EPOOL=3 \
@ -299,11 +300,10 @@ PREDEFINED = Q_SPY \
QF_MPOOL_CTR_SIZE=2 \
QF_TIMEEVT_CTR_SIZE=4 \
QF_ACTIVE_STOP=0 \
QF_ON_CONTEXT_SW \
QS_TIME_SIZE=4 \
QF_EQUEUE_TYPE=QEQueue \
QF_OS_OBJECT_TYPE=void* \
QF_THREAD_TYPE=void* \
QK_ON_CONTEXT_SW \
QXK_ON_CONTEXT_SW
QF_THREAD_TYPE=void*
EXPAND_AS_DEFINED =
SKIP_FUNCTION_MACROS = YES
SKIP_FUNCTION_MACROS = NO

5
doxygen/api.dox
View File

@ -125,6 +125,7 @@ QS is a software tracing system that enables developers to monitor live event-dr
- QS_OBJ_ARR_DICTIONARY()
- QS_FUN_DICTIONARY()
- QS_USR_DICTIONARY()
- QS_ENUM_DICTIONARY()
@subsection api_qs_user QS Application-Specific Records
@ -134,9 +135,9 @@ QS is a software tracing system that enables developers to monitor live event-dr
- QS_U8() / QS_I8()
- QS_U16() / QS_I16()
- QS_U32() / QS_I32()
- QS_U32_HEX()
- QS_STR()
- QS_MEM()
- QS_ENUM()
@section api_qv QV (Cooperative Kernel)
@ -176,7 +177,7 @@ QK is a tiny **preemptive**, run-to-completion (RTC) kernel designed specificall
@section api_qxk QXK (Dual-Mode Kernel)
QXK is a small, preemptive, priority-based, dual-mode (run-to-completion/**blocking**) kernel that executes active objects like the @ref srs_qk "QK kernel", but can also execute traditional __blocking__ threads (extended threads). In this respect, QXK behaves exactly as a conventional __RTOS__ (Real-Time Operating System). QXK has been designed specifically for mixing event-driven active objects with traditional blocking code, such as commercial middleware (TCP/IP stacks, UDP stacks, embedded file systems, etc.) or legacy software.
QXK is a small, preemptive, priority-based, dual-mode (run-to-completion/<b>blocking</b>) kernel that executes active objects like the @ref srs_qk "QK kernel", but can also execute traditional __blocking__ threads (extended threads). In this respect, QXK behaves exactly as a conventional __RTOS__ (Real-Time Operating System). QXK has been designed specifically for mixing event-driven active objects with traditional blocking code, such as commercial middleware (TCP/IP stacks, UDP stacks, embedded file systems, etc.) or legacy software.
@subsection api_qxk_ctrl Kernel Initialization and Control

374
doxygen/config.h
View File

@ -1,241 +1,9 @@
/**
* @file
* @brief Various macros for configuring and porting QP/C
* @brief Various macros for configuring QP/C (typically used as
* command-line options)
*/
/*! The maximum number of active objects in the application.
*
* @description
* This macro *must* be defined in the QF port and should be in range
* of 1U..64U, inclusive. The value of this macro determines the maximum
* priority level of an active object in the system. Not all priority
* levels must be used, but the maximum priority cannot exceed
* #QF_MAX_ACTIVE.
*
* @note Once you choose a certain value of #QF_MAX_ACTIVE, you must
* consistently use the same value in building all the QP component libraries
* and your own application code. The consistency is guaranteed if you define
* this macro only once in the qf_port.h header file and henceforth include
* this header file in all builds.
*/
#define QF_MAX_ACTIVE 32U
/*! The maximum number of clock tick rates in the application.
*
* @description
* This macro can be defined in the QF ports and should be in range
* of 1U..15U, inclusive. The value of this macro determines the maximum
* number of clock tick rates for time events (::QTimeEvt).
*
* If the macro is not defined, the default value is 1U.
*
* @note Once you choose a certain value of #QF_MAX_TICK_RATE, you must
* consistently use the same value in building all the QP component libraries
* and your own application code. The consistency is guaranteed if you define
* this macro only once in the qf_port.h header file and henceforth include
* this header file in all builds.
*/
#define QF_MAX_TICK_RATE 1U
/*! The maximum number of event pools in the application.
*
* @description
* This macro can be defined in the QF ports and should be in range
* of 1U..255U, inclusive. The value of this macro determines the maximum
* event pools in the system. Not all event pools must be actually used,
* but the maximum number of pools cannot exceed #QF_MAX_EPOOL.
*
* If the macro is not defined, the default value is 3U. Defining the value
* below the maximum saves some memory, mostly for the subscriber-lists.
* @sa ::QSubscrList.
*
* @note Once you choose a certain value of #QF_MAX_EPOOL, you must
* consistently use the same value in building all the QP component libraries
* and your own application code. The consistency is guaranteed if you define
* this macro only once in the qf_port.h header file and henceforth include
* this header file in all builds.
*/
#define QF_MAX_EPOOL 3U
/*! The size (in bytes) of the event-size representation in the QF.
* Valid values: 1U, 2U, or 4U; default 2U
*
* @description
* This macro can be defined in the QF ports to configure the size
* of the event-size.
*
* @note Once you choose a certain value of #QF_EVENT_SIZ_SIZE, you must
* consistently use the same value in building all the QP component libraries
* and your own application code. The consistency is guaranteed if you define
* this macro only once in the qf_port.h header file and henceforth include
* this header file in all builds.
*/
#define QF_EVENT_SIZ_SIZE 2U
/*! The size (in bytes) of the ring-buffer counters used in the native QF
* event queue implementation. Valid values: 1U, 2U, or 4U; default 1U
*
* @description
* This macro can be defined in the QF ports to configure the ::QEQueueCtr
* type. If the macro is not defined, the default of 1 byte will be chosen in
* qequeue.h. The valid #QF_EQUEUE_CTR_SIZE values of 1U, 2U, or 4U, correspond
* to ::QEQueueCtr of uint8_t, uint16_t, and uint32_t, respectively. The
* ::QEQueueCtr data type determines the dynamic range of numerical values of
* ring-buffer counters inside event queues, or, in other words, the maximum
* number of events that the native QF event queue can manage.
* @sa ::QEQueue
*
* @note Once you choose a certain value of #QF_EQUEUE_CTR_SIZE, you must
* consistently use the same value in building all the QP component libraries
* and your own application code. The consistency is guaranteed if you define
* this macro only once in the qf_port.h header file and henceforth include
* this header file in all builds.
*/
#define QF_EQUEUE_CTR_SIZE 1U
/*! The size (in bytes) of the block-size representation in the native QF
* event pool. Valid values: 1U, 2U, or 4U; default #QF_EVENT_SIZ_SIZE.
*
* @description
* This macro can be defined in the QF ports to configure the ::QMPoolSize
* type. If the macro is not defined, the default of #QF_EVENT_SIZ_SIZE
* will be chosen in qmpool.h, because the memory pool is primarily used for
* implementing event pools.
*
* The valid #QF_MPOOL_SIZ_SIZE values of 1U, 2U, or 4U, correspond to
* ::QMPoolSize of uint8_t, uint16_t, and uint32_t, respectively. The
* ::QMPoolSize data type determines the dynamic range of block-sizes that
* the native ::QMPool can handle.
* @sa #QF_EVENT_SIZ_SIZE, ::QMPool
*
* @note Once you choose a certain value of #QF_MPOOL_SIZ_SIZE, you must
* consistently use the same value in building all the QP component libraries
* and your own application code. The consistency is guaranteed if you define
* this macro only once in the qf_port.h header file and henceforth include
* this header file in all builds.
*/
#define QF_MPOOL_SIZ_SIZE 2U
/*! The size (in bytes) of the block-counter representation in the
* native QF event pool. Valid values: 1U, 2U, or 4U; default 2U.
*
* @description
* This macro can be defined in the QF ports to configure the ::QMPoolCtr
* type. If the macro is not defined, the default of 2 bytes will be chosen
* in qmpool.h. The valid #QF_MPOOL_CTR_SIZE values of 1U, 2U, or 4U,
* correspond to ::QMPoolSize of uint8_t, uint16_t, and uint32_t, respectively.
* The ::QMPoolCtr data type determines the dynamic range of block-counters
* that the native ::QMPool can handle, or, in other words, the maximum number
* of blocks that the native QF event pool can manage.
* @sa ::QMPool
*
* @note Once you choose a certain value of #QF_MPOOL_CTR_SIZE, you must
* consistently use the same value in building all the QP component libraries
* and your own application code. The consistency is guaranteed if you define
* this macro only once in the qf_port.h header file and henceforth include
* this header file in all builds.
*/
#define QF_MPOOL_CTR_SIZE 2U
/*! The size (in bytes) of the time event-counter representation
* in the ::QTimeEvt struct. Valid values: 1U, 2U, or 4U; default 2U.
*
* @description
* This macro can be defined in the QF ports to configure the internal tick
* counters of Time Events. If the macro is not defined, the default of 4
* bytes will be chosen in qf.h. The valid #QF_TIMEEVT_CTR_SIZE values of 1,
* 2, or 4, correspond to tick counters of uint8_t, uint16_t, and uint32_t,
* respectively. The tick counter representation determines the dynamic range
* of time delays that a Time Event can handle.
* @sa ::QTimeEvt
*
* @note Once you choose a certain value of #QF_TIMEEVT_CTR_SIZE, you must
* consistently use the same value in building all the QP component libraries
* and your own application code. The consistency is guaranteed if you define
* this macro only once in the qf_port.h header file and henceforth include
* this header file in all builds.
*/
#define QF_TIMEEVT_CTR_SIZE 4U
/*! Define the interrupt disabling policy.
*
* @description
* This macro encapsulates platform-specific way of disabling interrupts
* from "C" for a given CPU and compiler.
*
* @note
* the #QF_INT_DISABLE macro should always be used in pair with the
* macro #QF_INT_ENABLE.
*/
#define QF_INT_DISABLE() intDisable()
/*! Define the interrupt enabling policy.
*
* @description
* This macro encapsulates platform-specific way of enabling interrupts
* from "C" for a given CPU and compiler.
*
* @note the #QF_INT_DISABLE macro should always be used in pair with the
* macro #QF_INT_ENABLE.
*/
#define QF_INT_ENABLE() intEnable()
void intDisable(void);
void intEnable(void);
/*! Define the type of the critical section status.
*
* @description
* Defining this macro configures the "saving and restoring critical section
* status" policy. Coversely, if this macro is not defined, the simple
* "unconditional critical section exit" is used.
*/
#define QF_CRIT_STAT_TYPE crit_stat_t
/*! Define the critical section entry policy.
*
* @description
* This macro enters a critical section (often by means of disabling
* interrupts). When the "saving and restoring critical section status"
* policy is used, the macro sets the @a status_ argument to the critical
* section status just before the entry. When the policy of "unconditional
* critical section exit" is used, the macro does not use the @a status_
* argument.
*
* @note the #QF_CRIT_ENTRY macro should always be used in pair with the
* macro #QF_CRIT_EXIT.
*/
#define QF_CRIT_ENTRY(stat_) ((stat_) = critEntry())
/*! Define the critical section exit policy.
/*
* @description
* This macro enters a critical section (often by means of disabling
* interrupts). When the "saving and restoring critical section status"
* policy is used, the macro restores the critical section status from the
* @a status_ argument. When the policy of "unconditional critical section
* exit" is used, the macro does not use the @a status argument and
* exits the critical section unconditionally (often by means of enabling
* interrupts).
*
* @note the #QF_CRIT_ENTRY macro should always be used in pair with the
* macro #QF_CRIT_EXIT.
*/
#define QF_CRIT_EXIT(stat_) critExit(stat_)
typedef unsigned int crit_stat_t;
crit_stat_t critEntry(void);
void critExit(crit_stat_t stat);
/*! Enable the QActive_stop() API in the QF port.
*
* @description
* Defining this macro enables the QActive_stop() API in a given port.
* This feature should be used with caution, as stopping and re-starting
* active objects **cleanly** can be tricky.
*/
#define QF_ACTIVE_STOP
/*! The preprocessor switch to disable checking assertions
*
* @description
@ -251,6 +19,15 @@ void critExit(crit_stat_t stat);
*/
#define Q_NASSERT
/*! Enable the QActive_stop() API in the QF port.
*
* @description
* Defining this macro enables the QActive_stop() API in a given port.
* This feature should be used with caution, as stopping and re-starting
* active objects **cleanly** can be tricky.
*/
#define QF_ACTIVE_STOP
/*! The preprocessor switch to activate the QS software tracing
* instrumentation in the code
*
@ -276,133 +53,10 @@ void critExit(crit_stat_t stat);
*/
#define Q_EVT_CTOR
/*! This macro defines the type of the thread handle used for AOs */
#define QF_THREAD_TYPE void*
/*! This macro defines the type of the event-queue used for AOs */
#define QF_EQUEUE_TYPE QEQueue
/*! This macro defines the type of the OS-Object used for blocking
* the native ::QEQueue when the queue is empty
*
* @description
* This macro is used when ::QEQueue is used as the event-queue for AOs
* but also the AO queue must *block* when the queue is empty.
* In that case, #QF_OS_OBJECT_TYPE specifies the blocking mechanism.
* For example, in the POSIX port, the blocking mechanism is a condition
* variable.
/*! This macro enables calling the context-switch callback
* QF_onContextSw() in all build-in kernels (QV, QK, QXK)
*/
#define QF_OS_OBJECT_TYPE pthread_cond_t
/*! Platform-dependent macro defining how QF should block the
* calling task when the QF native queue is empty
*
* @note
* This is just an example of QACTIVE_EQUEUE_WAIT_() for the QK-port
* of QF. QK never activates a task that has no events to process, so in
* this case the macro asserts that the queue is not empty. In other QF
* ports you need to define the macro appropriately for the underlying
* kernel/OS you're using.
*/
#define QACTIVE_EQUEUE_WAIT_(me_) \
(Q_ASSERT((me_)->eQueue.frontEvt != (QEvt *)0))
#if (QF_MAX_ACTIVE <= 8U)
#define QACTIVE_EQUEUE_SIGNAL_(me_) do { \
QPSet8_insert(&QF_readySet_, (me_)->prio); \
if (QF_intNest_ == 0U) { \
uint_fast8_t p = QK_schedPrio_(); \
if (p != 0U) { \
QK_sched_(p); \
} \
} \
} while (0)
#else
/*! Platform-dependent macro defining how QF should signal the
* active object task that an event has just arrived.
*
* @description
* The macro is necessary only when the native QF event queue is used.
* The signaling of task involves unblocking the task if it is blocked.
*
* @note QACTIVE_EQUEUE_SIGNAL_() is called from a critical section.
* It might leave the critical section internally, but must restore
* the critical section before exiting to the caller.
*
* @note This is just an example of QACTIVE_EQUEUE_SIGNAL_() for the
* QK-port of QF. In other QF ports you need to define the macro
* appropriately for the underlying kernel/OS you're using.
*/
#define QACTIVE_EQUEUE_SIGNAL_(me_) do { \
QPSet64_insert(&QF_readySet_, (me_)->prio); \
if (QF_intNest_ == 0U) { \
uint_fast8_t p = QK_schedPrio_(); \
if (p != 0U) { \
QK_sched_(p); \
} \
} \
} while (0)
#endif
/*! This macro defines the type of the event pool used in the QK kernel.
*
* @note This is a specific implementation for the QK-port of QF.
* In other QF ports you need to define the macro appropriately for
* the underlying kernel/OS you're using.
*/
#define QF_EPOOL_TYPE_ QMPool
/*! This macro enables calling the QK context-switch callback
* QK_onContextSw()
*/
#define QK_ON_CONTEXT_SW
/*! This macro enables calling the QXK context-switch callback
* QXK_onContextSw()
*/
#define QXK_ON_CONTEXT_SW
/*! Platform-dependent macro defining the event pool initialization
*
* @note
* This is an example implementation based on the native ::QMPool class.
* In other QF ports, the port might be using a memory pool from the
* underlying kernel/OS.
*/
#define QF_EPOOL_INIT_(p_, poolSto_, poolSize_, evtSize_) \
(QMPool_init(&(p_), (poolSto_), (poolSize_), (QMPoolSize)(evtSize_)))
/*! Platform-dependent macro defining how QF should obtain the
* event pool block-size
*
* @note
* This is a specific implementation for the built-in kernels.
* In other QF ports you need to define the macro appropriately for
* the underlying kernel/OS you're using.
*/
#define QF_EPOOL_EVENT_SIZE_(p_) ((uint32_t)(p_).blockSize)
/*! Platform-dependent macro defining how QF should obtain an event
* @a e_ from the event pool @a p_ with the free margin @a m_.
*
* @note
* This is an example implementation based on the native ::QMPool class.
* In other QF ports, the port might be using a memory pool from the
* underlying kernel/OS.
*/
#define QF_EPOOL_GET_(p_, e_, m_, qs_id_) \
((e_) = (QEvt *)QMPool_get(&(p_), (m_), (qs_id_)))
/*! Platform-dependent macro defining how QF should return an event
* @a e_ to the event pool @a p_
*
* @note
* This is an example implementation based on the native ::QMPool class.
* In other QF ports, the port might be using a memory pool from the
* underlying kernel/OS.
*/
#define QF_EPOOL_PUT_(p_, e_, qs_id_) \
(QMPool_put(&(p_), (e_), (qs_id_)))
#define QF_ON_CONTEXT_SW
/*! Macro defined only for the internal QP implementation. It should
* be not defined for the application-level code

14
doxygen/dir.dox
View File

@ -16,7 +16,7 @@ The QP&trade;/C <span class="img folder">src</span> directory needs to be added
*/
/*##########################################################################*/
/*! @dir src/qf
@brief Platform-independent implementation of the @ref qep and @ref qf components.
@brief Platform-independent implementation of the QEP and QF components.
@note
Typically, files in this directory need to be added to the application build, but some QP ports might not need all the files in this directory. For example, a QP port to a 3rd-party RTOS kernel might be using a message queue of the RTOS instead of the native QP event queue, in which case the file qf_actq.c would not be needed and should be excluded from the build.
@ -44,15 +44,5 @@ Files in this directory need to be included in the QP application build only if
*/
/*##########################################################################*/
/*! @dir src/qs
@brief Platform-independent implementation of the @ref qs component (software tracing).
*/
/*##########################################################################*/
/*! @dir test
@brief System-level tests of the QP/C framework itself.
@note
The `qpc/test/` directory is planned to contain a growing number of system-level tests, which are based on QUTest, but *without* the QP-stub. The tests take advantage of the new QUTest configuration, where the QP-stub is NOT included (because the actual QP framework is linked). This configuration is activated by defining macro `Q_UTEST=0`.
@attention
Many tests provided in the `qpc/test/` directory run only on embedded targets and cannot run on the host machine.
@brief Platform-independent implementation of the QS component (software tracing).
*/

9
doxygen/exa_native.dox
View File

@ -139,7 +139,8 @@ This example implements the @ref blinky "Blinky sample application" on the EK-TM
The Blinky example is located in the directory <span class="img folder">qpc/examples/arm-cm/blinky_ek-tm4c123gxl</span>, which is organized as follows:
@code{c}
<br>
@code{.c}
qpc/ // QP/C installation directory
+-examples/ // QP/C examples directory (application)
| +-arm-cm/ // QP/C examples for ARM Cortex-M
@ -275,7 +276,8 @@ This example implements the @ref dpp "Dining Philosophers Problem" sample applic
The DPP example is located in the directory <span class="img folder">qpc/examples/arm-cm/dpp_ek-tm4c123gxl</span>, which is organized as follows:
@code{c}
<br>
@code{.c}
qpc/ // QP/C installation directory
+-examples/ // QP/C examples directory (applications)
| +-arm-cm/ // QP/C examples for ARM Cortex-M
@ -372,7 +374,8 @@ The application also demonstrates <a href="https://www.state-machine.com/qtools/
The DPP example is located in the directory <span class="img folder">qpc/examples/arm-cm/dpp_efm32-slstk3401a</span> and includes versions for @ref srs_qv "cooperative QV kernel", the @ref srs_qk "preemptive QK kernel", and the @ref srs_qxk "preemptive dual mode QXK RTOS kernel" each provided for the ARM-KEIL, GNU-ARM, and IAR-ARM. The following annotated directory listing describes the contents of the example folder:
@code{c}
<br>
@code{.c}
qpc/ // QP/C installation directory
+-examples/ // QP/C examples directory (application)
| +-arm-cm/ // QP/C examples for ARM Cortex-M

30
doxygen/exa_os.dox
View File

@ -48,10 +48,11 @@ On Windows, the **make** utility and the GNU GCC toolchain (**MinGW**) are provi
@section exa_os-qv Single-Threaded and Multi-Threaded QP/C Ports
Each of the examples can be linked to either the single-threaded QP/C ports (@ref win32-qv or @ref posix-qv) or multi-threaded ports (@ref win32 or @ref posix). The choice is made in the `Makefiles`, by editing the line, which defines the `QP_PORT_DIR` symbol. For instance, the following lines select the @ref win32-qv port and leave the @ref win32 port commented-out:
@code
<br>
@verbatim
QP_PORT_DIR := $(QPC)/ports/win32-qv
#QP_PORT_DIR := $(QPC)/ports/win32
@endcode
@endverbatim
To reverse the selection, you need to move the comment `#` character.
@ -72,15 +73,16 @@ The `Makefiles` for the examples generally support the following three build con
@subsection exa_os-dbg Debug Configuration
This is the default build configuration, with full debugging information and minimal optimization. To build this configuration, type:
@code
<br>
@verbatim
make
@endcode
@endverbatim
To clean this build, type
@code
@verbatim
make clean
@endcode
@endverbatim
The object files and the executable is located in the <span class="img folder">build</span> sub-directory.
@ -90,15 +92,15 @@ The object files and the executable is located in the <span class="img folder">b
This configuration is built with no debugging information and high optimization. Single-stepping and debugging might be difficult due
to the lack of debugging information and optimized code. To build this configuration, type:
@code
@verbatim
make CONF=rel
@endcode
@endverbatim
To clean this build, type
@code
@verbatim
make CONF=rel clean
@endcode
@endverbatim
The object files and the executable is located in the <span class="img folder">build_rel</span> directory.
@ -106,15 +108,15 @@ The object files and the executable is located in the <span class="img folder">b
@subsection exa_os-spy Spy Configuration
This configuration is built with the QP's Q-SPY trace functionality. The QP/Spy output is performed by a TCP/IP socket and requires launching the QSPY host application with the -t option. To build this configuration, type:
@code
@verbatim
make CONF=spy
@endcode
@endverbatim
To clean this build, type
@code
@verbatim
make CONF=spy clean
@endcode
@endverbatim
The object files and the executable are located in the <span class="img folder">build_spy</span> sub-directory.

6
doxygen/exa_rtos.dox
View File

@ -425,7 +425,7 @@ The "Blinky" example blinks an on-board LED once per second. The blinking is don
[3] west build -b <board>
[3a] west build -b nucleo_h743zi
[3b] west build -b nucleo_l053r8
~~~
...
[4] west flush
@endverbatim
@ -508,7 +508,7 @@ DPP example with multiple active objects.
[3] west build -b <board>
[3a] west build -b nucleo_h743zi
[3b] west build -b nucleo_l053r8
~~~
...
[4] west flush
@endverbatim
@ -604,7 +604,7 @@ qspy -c /dev/ttyACM0
@endverbatim
@subsection @section zephyr_dpp-qs-output QSPY Output Example
@subsection zephyr_dpp-qs-output QSPY Output Example
After resetting the board, you should see output similar to the following:
@verbatim
########## Trg-RST QP-Ver=701,Build=220810_150847

147
doxygen/gen/metrics.txt
View File

@ -2,7 +2,7 @@
================================================
NLOC CCN token PARAM length location
------------------------------------------------
3 1 16 1 3 QHsm_state@409-411@..\include\qep.h
3 1 16 1 3 QHsm_state@410-412@..\include\qep.h
3 1 15 1 3 QEQueue_getNFree@306-308@..\include\qequeue.h
3 1 15 1 3 QEQueue_getNMin@323-325@..\include\qequeue.h
3 1 21 1 3 QEQueue_isEmpty@342-344@..\include\qequeue.h
@ -13,41 +13,40 @@
11 3 105 2 14 QPSet_insert@286-299@..\include\qf.h
12 3 117 2 15 QPSet_remove@302-316@..\include\qf.h
6 3 56 1 9 QPSet_findMax@319-327@..\include\qf.h
3 1 27 1 3 QActive_getPrio@782-784@..\include\qf.h
6 1 20 2 6 QF_psInit@1412-1417@..\include\qf.h
6 1 20 2 6 QF_psInit@1405-1410@..\include\qf.h
3 1 20 1 3 QEvt_refCtr_inc_@180-182@..\include\qf_pkg.h
3 1 20 1 3 QEvt_refCtr_dec_@189-191@..\include\qf_pkg.h
14 3 67 1 14 QS_rxPut@863-876@..\include\qs.h
14 3 67 1 14 QS_rxPut@892-905@..\include\qs.h
7 1 33 3 7 QHsm_reservedEvt_@90-96@..\src\qf\qep_hsm.c
18 3 101 2 24 QHsm_isIn@103-126@..\src\qf\qep_hsm.c
22 4 125 2 31 QHsm_childState@129-159@..\src\qf\qep_hsm.c
12 2 57 2 14 QHsm_ctor@162-175@..\src\qf\qep_hsm.c
7 1 29 2 7 QHsm_top@178-184@..\src\qf\qep_hsm.c
51 8 360 3 77 QHsm_init_@187-263@..\src\qf\qep_hsm.c
101 15 631 3 154 QHsm_dispatch_@266-419@..\src\qf\qep_hsm.c
3 1 16 1 3 QHsm_getStateHandler_@423-425@..\src\qf\qep_hsm.c
91 15 480 3 132 QHsm_tran_@429-560@..\src\qf\qep_hsm.c
14 3 79 3 17 QHsm_state_entry_@563-579@..\src\qf\qep_hsm.c
20 3 96 3 23 QHsm_state_exit_@582-604@..\src\qf\qep_hsm.c
55 10 386 3 82 QHsm_init_@187-268@..\src\qf\qep_hsm.c
101 15 631 3 154 QHsm_dispatch_@271-424@..\src\qf\qep_hsm.c
3 1 16 1 3 QHsm_getStateHandler_@428-430@..\src\qf\qep_hsm.c
91 15 480 3 132 QHsm_tran_@434-565@..\src\qf\qep_hsm.c
14 3 79 3 17 QHsm_state_entry_@568-584@..\src\qf\qep_hsm.c
20 3 96 3 23 QHsm_state_exit_@587-609@..\src\qf\qep_hsm.c
15 3 69 2 16 QMsm_isInState@81-96@..\src\qf\qep_msm.c
3 1 17 1 3 QMsm_stateObj@99-101@..\src\qf\qep_msm.c
22 4 97 2 29 QMsm_childStateObj@104-132@..\src\qf\qep_msm.c
12 2 60 2 15 QMsm_ctor@135-149@..\src\qf\qep_msm.c
27 4 202 3 45 QMsm_init_@152-196@..\src\qf\qep_msm.c
117 19 728 3 168 QMsm_dispatch_@199-366@..\src\qf\qep_msm.c
3 1 18 1 3 QMsm_getStateHandler_@370-372@..\src\qf\qep_msm.c
55 9 317 3 68 QMsm_execTatbl_@376-443@..\src\qf\qep_msm.c
24 4 132 4 32 QMsm_exitToTranSource_@446-477@..\src\qf\qep_msm.c
45 6 243 3 54 QMsm_enterHistory_@480-533@..\src\qf\qep_msm.c
82 14 431 4 120 QActive_post_@70-189@..\src\qf\qf_actq.c
44 7 266 2 66 QActive_postLIFO_@194-259@..\src\qf\qf_actq.c
34 3 233 1 44 QActive_get_@264-307@..\src\qf\qf_actq.c
10 2 60 1 11 QF_getQueueMin@313-323@..\src\qf\qf_actq.c
16 2 79 2 20 QTicker_ctor@342-361@..\src\qf\qf_actq.c
10 1 45 3 11 QTicker_init_@364-374@..\src\qf\qf_actq.c
17 2 92 3 20 QTicker_dispatch_@377-396@..\src\qf\qf_actq.c
30 2 156 4 37 QTicker_post_@399-435@..\src\qf\qf_actq.c
8 1 30 2 9 QTicker_postLIFO_@438-446@..\src\qf\qf_actq.c
31 7 153 2 38 QMsm_childStateObj@104-141@..\src\qf\qep_msm.c
12 2 60 2 15 QMsm_ctor@144-158@..\src\qf\qep_msm.c
27 4 202 3 45 QMsm_init_@161-205@..\src\qf\qep_msm.c
118 19 740 3 169 QMsm_dispatch_@208-376@..\src\qf\qep_msm.c
3 1 18 1 3 QMsm_getStateHandler_@380-382@..\src\qf\qep_msm.c
55 9 317 3 70 QMsm_execTatbl_@386-455@..\src\qf\qep_msm.c
24 4 132 4 33 QMsm_exitToTranSource_@458-490@..\src\qf\qep_msm.c
45 6 243 3 56 QMsm_enterHistory_@493-548@..\src\qf\qep_msm.c
82 14 431 4 122 QActive_post_@70-191@..\src\qf\qf_actq.c
44 7 266 2 66 QActive_postLIFO_@196-261@..\src\qf\qf_actq.c
34 3 233 1 44 QActive_get_@266-309@..\src\qf\qf_actq.c
10 2 60 1 11 QF_getQueueMin@315-325@..\src\qf\qf_actq.c
16 2 79 2 20 QTicker_ctor@344-363@..\src\qf\qf_actq.c
10 1 45 3 11 QTicker_init_@366-376@..\src\qf\qf_actq.c
16 2 90 3 18 QTicker_dispatch_@379-396@..\src\qf\qf_actq.c
30 2 156 4 39 QTicker_post_@399-437@..\src\qf\qf_actq.c
8 1 30 2 9 QTicker_postLIFO_@440-448@..\src\qf\qf_actq.c
15 1 84 3 17 QActive_defer@65-81@..\src\qf\qf_defer.c
34 3 169 2 54 QActive_recall@86-139@..\src\qf\qf_defer.c
13 3 68 2 15 QActive_flushDeferred@144-158@..\src\qf\qf_defer.c
@ -56,25 +55,25 @@
9 3 59 1 12 QF_getPoolMin@119-130@..\src\qf\qf_dyn.c
39 7 234 3 57 QF_newX_@133-189@..\src\qf\qf_dyn.c
30 4 188 1 46 QF_gc@192-237@..\src\qf\qf_dyn.c
20 2 99 2 28 QF_newRef_@240-267@..\src\qf\qf_dyn.c
11 2 67 1 15 QF_deleteRef_@270-284@..\src\qf\qf_dyn.c
20 3 99 2 30 QF_newRef_@240-269@..\src\qf\qf_dyn.c
11 2 67 1 15 QF_deleteRef_@272-286@..\src\qf\qf_dyn.c
32 5 233 4 50 QMPool_init@67-116@..\src\qf\qf_mem.c
45 5 241 3 72 QMPool_get@119-190@..\src\qf\qf_mem.c
19 3 117 3 26 QMPool_put@193-218@..\src\qf\qf_mem.c
45 5 241 3 74 QMPool_get@119-192@..\src\qf\qf_mem.c
19 3 117 3 28 QMPool_put@195-222@..\src\qf\qf_mem.c
8 1 35 2 13 QActive_psInit@73-85@..\src\qf\qf_ps.c
43 6 232 3 73 QActive_publish_@90-162@..\src\qf\qf_ps.c
18 5 111 2 24 QActive_subscribe@167-190@..\src\qf\qf_ps.c
18 5 111 2 27 QActive_unsubscribe@195-221@..\src\qf\qf_ps.c
19 5 130 1 24 QActive_unsubscribeAll@226-249@..\src\qf\qf_ps.c
43 6 232 3 75 QActive_publish_@90-164@..\src\qf\qf_ps.c
18 5 111 2 24 QActive_subscribe@169-192@..\src\qf\qf_ps.c
18 5 111 2 27 QActive_unsubscribe@197-223@..\src\qf\qf_ps.c
19 5 130 1 24 QActive_unsubscribeAll@228-251@..\src\qf\qf_ps.c
10 2 46 2 10 QF_bzero@85-94@..\src\qf\qf_qact.c
16 2 72 2 23 QActive_ctor@101-123@..\src\qf\qf_qact.c
28 10 225 1 47 QActive_register_@128-174@..\src\qf\qf_qact.c
10 3 79 1 15 QActive_unregister_@179-193@..\src\qf\qf_qact.c
24 6 143 1 29 QF_LOG2@201-229@..\src\qf\qf_qact.c
14 2 84 3 14 QEQueue_init@67-80@..\src\qf\qf_qeq.c
57 8 301 4 76 QEQueue_post@83-158@..\src\qf\qf_qeq.c
36 5 199 3 46 QEQueue_postLIFO@161-206@..\src\qf\qf_qeq.c
38 4 219 2 48 QEQueue_get@209-256@..\src\qf\qf_qeq.c
57 8 301 4 78 QEQueue_post@83-160@..\src\qf\qf_qeq.c
36 5 199 3 48 QEQueue_postLIFO@163-210@..\src\qf\qf_qeq.c
38 4 219 2 50 QEQueue_get@213-262@..\src\qf\qf_qeq.c
16 2 79 2 35 QMActive_ctor@74-108@..\src\qf\qf_qmact.c
15 2 96 4 32 QTimeEvt_ctorX@78-109@..\src\qf\qf_time.c
33 8 225 3 59 QTimeEvt_armX@112-170@..\src\qf\qf_time.c
@ -82,31 +81,31 @@
36 8 230 2 64 QTimeEvt_rearm@216-279@..\src\qf\qf_time.c
5 1 36 1 5 QTimeEvt_wasDisarmed@282-286@..\src\qf\qf_time.c
7 1 30 1 8 QTimeEvt_currCtr@289-296@..\src\qf\qf_time.c
69 7 380 2 110 QTimeEvt_tick_@299-408@..\src\qf\qf_time.c
14 3 75 1 16 QTimeEvt_noActive@411-426@..\src\qf\qf_time.c
69 7 380 2 112 QTimeEvt_tick_@299-410@..\src\qf\qf_time.c
14 3 75 1 16 QTimeEvt_noActive@413-428@..\src\qf\qf_time.c
21 2 112 1 31 QK_schedLock@74-104@..\src\qk\qk.c
20 4 118 1 33 QK_schedUnlock@107-139@..\src\qk\qk.c
11 3 101 1 23 QF_init@144-166@..\src\qk\qk.c
3 1 10 1 4 QF_stop@169-172@..\src\qk\qk.c
15 4 61 1 25 QF_run@175-199@..\src\qk\qk.c
25 3 156 7 34 QActive_start_@206-239@..\src\qk\qk.c
19 4 78 1 24 QK_sched_@244-267@..\src\qk\qk.c
65 17 384 1 112 QK_activate_@270-381@..\src\qk\qk.c
18 6 76 1 33 QF_run@175-207@..\src\qk\qk.c
25 3 156 7 34 QActive_start_@214-247@..\src\qk\qk.c
19 4 78 1 24 QK_sched_@252-275@..\src\qk\qk.c
65 17 378 1 112 QK_activate_@278-389@..\src\qk\qk.c
7 3 52 1 13 QF_init@73-85@..\src\qv\qv.c
3 1 10 1 4 QF_stop@88-91@..\src\qv\qv.c
39 10 197 1 77 QF_run@94-170@..\src\qv\qv.c
18 1 124 7 25 QActive_start_@177-201@..\src\qv\qv.c
46 15 251 1 97 QF_run@94-190@..\src\qv\qv.c
18 1 124 7 25 QActive_start_@197-221@..\src\qv\qv.c
23 3 131 1 34 QXK_schedLock@71-104@..\src\qxk\qxk.c
20 4 118 1 33 QXK_schedUnlock@107-139@..\src\qxk\qxk.c
11 3 101 1 23 QF_init@144-166@..\src\qxk\qxk.c
3 1 10 1 4 QF_stop@169-172@..\src\qxk\qxk.c
18 4 92 1 30 QF_run@175-204@..\src\qxk\qxk.c
29 5 178 7 42 QActive_start_@211-252@..\src\qxk\qxk.c
42 8 220 1 53 QXK_sched_@260-312@..\src\qxk\qxk.c
59 16 383 1 98 QXK_activate_@315-412@..\src\qxk\qxk.c
12 2 72 1 18 QXK_current@415-432@..\src\qxk\qxk.c
23 7 132 1 34 QXK_contextSw@436-469@..\src\qxk\qxk.c
13 2 104 1 23 QXK_threadExit_@476-498@..\src\qxk\qxk.c
12 3 110 1 24 QF_init@144-167@..\src\qxk\qxk.c
3 1 10 1 4 QF_stop@170-173@..\src\qxk\qxk.c
20 6 98 1 35 QF_run@176-210@..\src\qxk\qxk.c
29 5 178 7 42 QActive_start_@217-258@..\src\qxk\qxk.c
42 8 220 1 53 QXK_sched_@266-318@..\src\qxk\qxk.c
59 16 377 1 98 QXK_activate_@321-418@..\src\qxk\qxk.c
12 2 72 1 18 QXK_current@421-438@..\src\qxk\qxk.c
19 5 105 1 26 QXK_contextSw@442-467@..\src\qxk\qxk.c
13 2 104 1 23 QXK_threadExit_@474-496@..\src\qxk\qxk.c
10 2 64 2 13 QXMutex_init@74-86@..\src\qxk\qxk_mutex.c
81 11 724 2 138 QXMutex_lock@89-226@..\src\qxk\qxk_mutex.c
59 9 502 1 97 QXMutex_tryLock@229-325@..\src\qxk\qxk_mutex.c
@ -122,12 +121,12 @@
10 1 39 3 11 QXThread_init_@247-257@..\src\qxk\qxk_xthr.c
10 1 39 3 11 QXThread_dispatch_@260-270@..\src\qxk\qxk_xthr.c
31 7 216 7 52 QXThread_start_@273-324@..\src\qxk\qxk_xthr.c
100 15 527 4 138 QXThread_post_@327-464@..\src\qxk\qxk_xthr.c
8 1 30 2 9 QXThread_postLIFO_@467-475@..\src\qxk\qxk_xthr.c
5 1 49 1 7 QXThread_block_@478-484@..\src\qxk\qxk_xthr.c
8 3 56 1 8 QXThread_unblock_@487-494@..\src\qxk\qxk_xthr.c
20 3 157 3 39 QXThread_teArm_@497-535@..\src\qxk\qxk_xthr.c
11 2 46 1 13 QXThread_teDisarm_@538-550@..\src\qxk\qxk_xthr.c
100 15 527 4 140 QXThread_post_@327-466@..\src\qxk\qxk_xthr.c
8 1 30 2 9 QXThread_postLIFO_@469-477@..\src\qxk\qxk_xthr.c
5 1 49 1 7 QXThread_block_@480-486@..\src\qxk\qxk_xthr.c
8 3 56 1 8 QXThread_unblock_@489-496@..\src\qxk\qxk_xthr.c
20 3 157 3 39 QXThread_teArm_@499-537@..\src\qxk\qxk_xthr.c
11 2 46 1 13 QXThread_teDisarm_@540-552@..\src\qxk\qxk_xthr.c
33 file analyzed.
==============================================================
NLOC Avg.NLOC AvgCCN Avg.token function_cnt file
@ -135,33 +134,33 @@ NLOC Avg.NLOC AvgCCN Avg.token function_cnt file
6 0.0 0.0 0.0 0 ..\include\qassert.h
133 3.0 1.0 16.0 1 ..\include\qep.h
33 3.0 1.0 17.0 3 ..\include\qequeue.h
226 6.6 2.4 60.1 9 ..\include\qf.h
226 7.0 2.6 64.2 8 ..\include\qf.h
15 3.0 1.0 20.0 2 ..\include\qf_pkg.h
19 0.0 0.0 0.0 0 ..\include\qk.h
16 0.0 0.0 0.0 0 ..\include\qk.h
25 0.0 0.0 0.0 0 ..\include\qmpool.h
8 0.0 0.0 0.0 0 ..\include\qpc.h
356 14.0 3.0 67.0 1 ..\include\qs.h
7 0.0 0.0 0.0 0 ..\include\qpc.h
361 14.0 3.0 67.0 1 ..\include\qs.h
3 0.0 0.0 0.0 0 ..\include\qstamp.c
2 0.0 0.0 0.0 0 ..\include\qstamp.h
0 0.0 0.0 0.0 0 ..\include\qs_dummy.h
19 0.0 0.0 0.0 0 ..\include\qs_pkg.h
7 0.0 0.0 0.0 0 ..\include\qv.h
96 0.0 0.0 0.0 0 ..\include\qxk.h
359 31.5 5.1 182.5 11 ..\src\qf\qep_hsm.c
336 32.3 5.3 188.3 10 ..\src\qf\qep_msm.c
93 0.0 0.0 0.0 0 ..\include\qxk.h
363 31.8 5.3 184.8 11 ..\src\qf\qep_hsm.c
346 33.3 5.6 195.1 10 ..\src\qf\qep_msm.c
2 0.0 0.0 0.0 0 ..\src\qf\qf_act.c
258 27.9 3.8 154.7 9 ..\src\qf\qf_actq.c
257 27.8 3.8 154.4 9 ..\src\qf\qf_actq.c
69 20.7 2.3 107.0 3 ..\src\qf\qf_defer.c
138 18.4 3.1 111.4 7 ..\src\qf\qf_dyn.c
138 18.4 3.3 111.4 7 ..\src\qf\qf_dyn.c
103 32.0 4.3 197.0 3 ..\src\qf\qf_mem.c
115 21.2 4.4 123.8 5 ..\src\qf\qf_ps.c
96 17.6 4.6 113.0 5 ..\src\qf\qf_qact.c
152 36.2 4.8 200.8 4 ..\src\qf\qf_qeq.c
18 16.0 2.0 79.0 1 ..\src\qf\qf_qmact.c
218 26.2 4.1 155.6 8 ..\src\qf\qf_time.c
187 22.4 4.8 127.5 8 ..\src\qk\qk.c
74 16.8 3.8 95.8 4 ..\src\qv\qv.c
261 23.0 5.0 140.1 11 ..\src\qxk\qxk.c
190 22.8 5.0 128.6 8 ..\src\qk\qk.c
81 18.5 5.0 109.2 4 ..\src\qv\qv.c
260 22.9 5.0 138.5 11 ..\src\qxk\qxk.c
235 57.0 8.5 490.0 4 ..\src\qxk\qxk_mutex.c
143 34.0 4.5 213.5 4 ..\src\qxk\qxk_sema.c
325 24.4 3.8 156.0 13 ..\src\qxk\qxk_xthr.c
@ -171,5 +170,5 @@ No thresholds exceeded (cyclomatic_complexity > 20 or length > 500 or nloc > 100
==========================================================================================
Total nloc Avg.NLOC AvgCCN Avg.token Fun Cnt Warning cnt Fun Rt nloc Rt
------------------------------------------------------------------------------------------
4037 24.2 4.2 149.1 126 0 0.00 0.00
4057 24.5 4.3 151.2 125 0 0.00 0.00
@endcode

17
doxygen/gs.dox
View File

@ -8,11 +8,12 @@ The YouTube Video <a class="extern" target="_blank" href="https://youtu.be/O7ER6
@image html gs-video.jpg
@image latex gs-video.jpg width=4.5in
@caption{Video: Getting Started with QP&trade; Real-Time Embedded Framework}
@caption{[Video: Getting Started with QP&trade; Real-Time Embedded Framework](https://youtu.be/O7ER6_VqIH0)}
<br>
@note
@htmlonly
<a href="modules.html" title="QP Cert-Pack"><img src="cert-pack.png" style="float:right; margin:0 20px 20px 0;"></img></a>
<a href="cert.html" title="QP Cert-Pack"><img src="img/cert-pack.png" style="float:right; margin:0 20px 20px 0;"></img></a>
@endhtmlonly
Information about the QP/C functionality, architecture, design, and other aspects is provided in the [Certification Package](modules.html):
- @ref srs &mdash; QP/C functionality
@ -35,7 +36,8 @@ The most recommended way of obtaining QP&trade;/C&trade; is by downloading the @
@image html qp-bundle.png
@image latex qp-bundle.png width=1.5in
@caption{QP-bundle Downloads}
@caption{@webref{#Downloads, QP-bundle&trade; downloads}}
<br>
@note
@htmlonly
@ -243,10 +245,11 @@ While the system clock tick is very useful, it also has the unfortunate side eff
@image html exa_low-power_tick.png
@image latex exa_low-power_tick.png width=6.0in
@image latex exa_low-power_tick.png width=5.5in
@caption{Additional power dissipation caused by the system clock tick}
@subsection arm-cm_low_power_tickless The "Tickless Mode"
Some real-time kernels use the low-power optimization called the "tickless mode" (a.k.a. "tick supression" or "dynamic tick"). In this mode, instead of indiscriminately making the clock tick fire with a fixed period, the kernel adjusts the clock ticks *dynamically*, as needed. Specifically, after each clock tick the kernel re-calculates the time for the next clock tick and then sets the clock tick interrupt for the earliest timeout it has to wait for. So for example, if the shortest wait the kernel has to attend to is 300 milliseconds into the future, then the clock interrupt will be set for 300 milliseconds.
This approach maximizes the amount of time the processor can remain asleep, but requires the kernel to perform the additional work to calculate the dynamic tick intervals and to program them into the hardware. This additional bookkeeping adds complexity to the kernel, is often non-deterministic and, most importantly, extends the time CPU spends in the high-power active mode and thus eliminates some of the power gains the "tickless mode" was supposed to bring.
@ -255,6 +258,7 @@ Also, the "tickless mode" requires a more capable hardware timer that must be ab
@subsection arm-cm_low_power_multiple Multiple Tick Rates
For the reasons just mentioned, the QP&trade; Real-Time Embedded Frameworks don't provide the "tickless mode". Instead, the QP&trade; frameworks support **multiple clock tick rates**, which can be turned on and off, as needed. The QP&trade; frameworks also provide methods for finding out *when* a given clock tick rate is not used, which allows the idle callback inside the application to shut down the given clock tick rate and also to decide which sleep mode to use for the CPU and the peripherals.
The support for multiple static clock tick rates is much *simpler* than the "dynamic tick", and essentially does not increase the complexity of the kernel (because the same code for the single tick rate can handle other tick rates the same way). Also, multiple static tick rates require much simpler hardware timers, which can be clocked specifically to the desired frequency and don't need particularly wide dynamic range. For example, 16-bit timers or even 8-bit timers are completely adequate.
@ -265,6 +269,7 @@ Yet the *multiple clock rates* can deliver similar low-power operation for the s
@section arm-cm_low_power_app The Low-Power Example Application
The low-power example is located in QP/C and QP/C++ distributions, in the directory with the following structure:
<br>
@code{.c}
qpc|qpcpp/ // QP/C/C++ installation directory
+-examples/ // QP/C/C++ examples directory (application)
@ -318,6 +323,7 @@ Actually, the **Red-LED** is also turned off for very brief moments, but this is
The behavior just described is designed for the slow human interaction with the application. However, for more precise measurements with a logic analyzer, it is more convenient to speed up the application by factor of 100. This speed up can be achieved by editing the `bsp.h` header file:
<br>
@code{.c}
/* The following ticks-per-second constants determine the speed of the app.
* The default (#if 1) is the SLOW speed for humans to see the blinking.
@ -369,6 +375,7 @@ The versions of this low-power example for the **QK** and **QV** kernels use two
@subsection arm-cm_low_power_xt Extended Thread (QXK)
The version of this low-power example for the **QXK** kernel uses one active object **Blinky0** (with the state machine shown above), but instead of the Blinky1 active object, the QXK version uses an eXtended thread (::QXThread) called **XBlinky1**, with the code shown below:
<br>
@code{.c}
#include "qpc.h"
#include "low_power.h"
@ -422,6 +429,7 @@ The version of this low-power example for the **QXK** kernel uses one active obj
@subsection arm-cm_low_power_idle The Idle Callback (QK/QXK)
The most important functionality in this low-power example is implemented in the **idle callback** located in the BSP (Board Support Package). The idle callback QK_onIdle() for the preemptive QK kernel and the idle callback QXK_onIdle() for the QXK kernel are almost identical and are explained in this section.
<br>
@code{.c}
[0] void QXK_onIdle(void) {
@ -486,6 +494,7 @@ The QF_noTimeEvtsActiveX() function is designed to be called from a critical sec
@subsection arm-cm_low_power_idle-qv The Idle Callback (QV)
The idle callback QV_onIdle() for the cooperative QV kernel is slightly different, because it is called with interrupts **disabled**. The following listing shows the complete QV_onIdle() callback, with the most important points explained in the section below:
<br>
@code{.c}
[0] void QV_onIdle(void) { /* NOTE: called with interrupts DISABLED */

62
doxygen/history.dox
View File

@ -1,4 +1,4 @@
/*! @page history Design History File
/*! @page history Design History File (DHF)
@image html qcp_banner.jpg
@image latex qcp_banner.jpg width=6.5in
@ -6,11 +6,63 @@
@remark
This document is part of the @webref{products/qp#CERT,QP Certification Pack}, which has been specifically designed to aid companies in **safety certification** of their software based on the QP real-time embedded frameworks.
@section qpc_7_2_0 Version 7.2.0, 2023-01-06
__QP/C Source Code:__
- Added "enumeration dictionaries" for QS software tracing (see QS_ENUM_DICTIONARY())
- Introduced common callback `QF_onContextSw()` used in all built-in kernels (QV, QK, QXK). This callback is enabled by the macro #QF_ON_CONTEXT_SW.
- Removed callback `QK_onContextSW()` and macro QK_ON_CONTEXT_SW and replaced with `QF_onContextSw()`/#QF_ON_CONTEXT_SW.
- Removed callback `QXK_onContextSW()` and macro QXK_ON_CONTEXT_SW and replaced with `QF_onContextSw()`/#QF_ON_CONTEXT_SW.
- Added callback `QF_onContextSW()` and macro #QF_ON_CONTEXT_SW to the QV kernel.
- added configuration macro #QS_CTR_SIZE to determine the size of the type ::QSCtr (see also [feature#195](https://sourceforge.net/p/qpc/feature-requests/195))
- Removed backwards-compatibility with QP 5.4.0 or older. This includes removing workarounds for `QFsm`, `QFsm_ctor()`, `Q_IGNORED()`.
- Modified QMsm_childStateObj() implementation to correctly handle submachine states (see also [bug#316](https://sourceforge.net/p/qpc/bugs/316))
- Added automatic generation of the QS function dictionary for the QHsm_top() state handler function. This happens only once on the first call to QHSM_INIT().
@note
It is no longer necessary to generate QS function dictionary for QHsm_top() in the application (although it is still allowed, but wasteful).
__Ports:__
- `ports/arm-cm` added setup of the FPU (if configured) to all build-in kernels (QV, QK, QXK) and toolchains (ARMCLANG, GNU-ARM, IAR).
- `ports/arm-cm` all ports now clear the FPCA bit in the CONTROL register (if FPU configured) right before starting the interrupts. That potentially saves the stack space (MSP) for the automatically reserved FPU context.
@note
This change means that the applications no longer need to setup the FPU, which was done typically in the BSP.
- `ports/posix` added configuration macro #QS_CTR_SIZE 4U, to allow QS trace buffers > 64KB (see also [feature#195](https://sourceforge.net/p/qpc/feature-requests/195))
- `ports/win32` added configuration macro #QS_CTR_SIZE 4U, to allow QS trace buffers > 64KB (see also [feature#195](https://sourceforge.net/p/qpc/feature-requests/195))
- `ports/esp-idf` fixed compilation error caused by obsolete macro `QF_PTR_RANGE_()`
- `ports/sample` added a sample QP/C port for reference and documentation of all available configuration options.
- `zephyr` updated `qf_port.h` to include `<zephyr/kernel.h>` rather than `<zephyr/zephyr.h>` (see also [bug#321](https://sourceforge.net/p/qpc/bugs/321))
__Examples:__
- examples for QV: added callback `QF_onContextSw()`
- exampels for QK, QXK: replaced callbacks `QK_onContextSw()/QXK_onContextSw()` with `QF_onContextSw()`
- `examples/arm-cm` removed setting up the FPU from the BSPs (the FPU is now setup in the ports).
- `examples/arm-cm` added setting up the MPU (Memory Protection Unit) to catch [NULL-pointer dereferencing](https://www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu) and other incorrect memory access.
__Testing:__
- changed the QUTest assertion handler Q_onAssert() to reset the target rather than wait for user commands. This allows proper assertion handling even inside exception handlers, where the target really cannot handle interrupts (which were needed for reception of commands). This change matches the updated policy of **assertion failures** in [QUTest 7.2.0](https://www.state-machine.com/qtools/history.html#qtools_7_2_0).
- examples for QUTest (`examples/qutest` and `test` directories): adjusted makefiels to invoke the `qutest.py` utility with the new [command-line parameters](https://www.state-machine.com/qtools/qutest_use.html#qutest_command).
- modified the test fixtures to use "enum dictionaries" for commands
- added example `examples/qutest/start_seq` that demonstrates testing of start sequences.
@section qpc_7_1_3 Version 7.1.3, 2022-11-18
__Bug Fixes:__
- This release fixes [bug#317](https://sourceforge.net/p/qpc/bugs/317) in QK kernel
- [bug#315 QSignal defined incorrectly when #Q_SIGNAL_SIZE==4U](https://sourceforge.net/p/qpc/bugs/315)
- [bug#316 Using History with Submachines does not work](https://sourceforge.net/p/qpc/bugs/316)
- [bug#321 zephyr port build error](https://sourceforge.net/p/qpc/bugs/321)
- [bug#325 QSpy shows Sig=NULL if #Q_EVT_CTOR is used](https://sourceforge.net/p/qpc/bugs/325)
__Feature Requests:__
- [feature#195 allow > 64K QS trace buffer on target](https://sourceforge.net/p/qpc/feature-requests/195). This is configurable by setting the macro #QS_CTR_SIZE.
@section qpc_7_1_3 Version 7.1.3, 2022-11-18
__Bug Fixes:__
- [bug#317 QK works incorrectly in QP/C/C++ 7.1.2](https://sourceforge.net/p/qpc/bugs/317)
__Source__
- The file `qstamp.c` has been copied from the `include/` folder to `src/qs/`. This makes it easier to build SPY configuration. (The file `qstamp.c` has been left in the `include/` folder for backwards compatibility).
@ -164,7 +216,7 @@ __Modified QP/C ports:__
- removed unused `ARM_ARCH` symbol from Makefiles for GNU-ARM
- fixed the following bugs in QXK port to ARM Cortex-M
+ [bug#305 Floating-point context corruption in QXK](https://sourceforge.net/p/qpc/bugs/305)
+ [bug#306 QXK_ON_CONTEXT_SW option is not compatible with soft-float](https://sourceforge.net/p/qpc/bugs/306)
+ [bug#306 #QF_ON_CONTEXT_SW option is not compatible with soft-float](https://sourceforge.net/p/qpc/bugs/306)
__Removed QP/C ports:__
- removed QP/C port to PIC24/dsPIC with XC16 (not compatible with C99)
@ -882,7 +934,7 @@ Also, this release adds assertions to the QXK code, which ensure that any availa
Also, this release adds protection in the IRQ priorities initialization in QK/QV/QXK for ARM Cortex-M3/M4/M7, so that the number of IRQs is extracted from bits 0-2 of the ICTR register (INTLINESNUM).
Finally, this release consistently changes all example projects (for all toolchains) to use the **src/** directory for QP/C source code, instead of the **source/** directory. The source/ directory is now truly obsolete, but is still provided in this release for backwards compatibility with user projects.
Finally, this release consistently changes all example projects (for all toolchains) to use the **src** directory for QP/C source code, instead of the **source** directory. The source/ directory is now truly obsolete, but is still provided in this release for backwards compatibility with user projects.
@section qpc_5_9_5 Version 5.9.5, 2017-07-20

BIN
doxygen/images/qk_asynch.png
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 12 KiB

BIN
doxygen/images/qk_synch.png
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 10 KiB

6
doxygen/main.dox
View File

@ -8,7 +8,7 @@
<a target="_blank" href="https://github.com/QuantumLeaps/qpc" title="QP/C on GitHub"><img class="right" src="img/logo_github.png"></a>
@endif
@image{inline} latex logo_github.png width=1in
To check what's new in QP&trade;/C, please see @ref history "QP/C Revision History". You can also get the latest **QP&trade;/C code**, with the recent enhancements and bug fixes, from the <a class="extern" target="_blank" href="https://github.com/QuantumLeaps/qpc"><strong>GitHub QP&trade;/C repository</strong></a>.
To check what's new in QP&trade;/C, please see @ref history "Design History File". You can also get the latest **QP&trade;/C code**, with the recent enhancements and bug fixes, from the <a class="extern" target="_blank" href="https://github.com/QuantumLeaps/qpc"><strong>GitHub QP&trade;/C repository</strong></a>.
<div style="clear:both"></div>
@ -21,7 +21,7 @@ The main objectives of the QP/C RTEF are:
- to provide a modern, event-driven model of concurrency based on the best practices of concurrent programming collectively known as the @webref{active-object, Active Object (Actor) model of computation}, which is inherently *safer* than the traditional "shared-state concurrency, mutual-exclusion, and blocking" approach based on a conventional Real-Time Operating System (RTOS);
- to provide an efficient, @ref tr "bidirectionally traceable" implementation of @webref{fsm#HSM, Hierarchical State Machines} for specifying the internal behavior of Active Objects;
- to provide an efficient, @ref cert_tr "bidirectionally traceable" implementation of @webref{fsm#HSM, Hierarchical State Machines} for specifying the internal behavior of Active Objects;
- to provide a *higher-level of abstraction* closer to the problem domain than the "naked" RTOS threads;
@ -73,7 +73,7 @@ QP/C can also work with many traditional @ref exa_rtos "Real-Time Operating Syst
@subsection over_trace Traceability
QP&trade;/C offers unprecedented, bidirectional @ref tr "traceability" among all work artifacts, which gives teams full visibility from requirements through architecture, design, source code, tests, and back again.
QP&trade;/C offers unprecedented, bidirectional @ref cert_tr "traceability" among all work artifacts, which gives teams full visibility from requirements through architecture, design, source code, tests, and back again.
@subsection over_popular Popularity &amp; Maturity

12
doxygen/modules-unused.dox
View File

@ -229,7 +229,9 @@ The TLS implementations vary, but many systems, including QXK, implement TLS by
Typical usage of TLS in QXK is illustrated in the example <span class="img folder">qpc/examples/arm-cm/dpp_efm32-slstk3401a/qxk/</span>, <span class="img file_c">test.c</span>, and consists:
- define the TLS structure
@code{c}
<br>
@code{.c}
typedef struct {
uint32_t foo;
uint8_t bar[10];
@ -237,7 +239,9 @@ typedef struct {
@endcode
- allocate the TLS storage for all participating threads (extended or basic threads)
@code{c}
<br>
@code{.c}
static TLS_test l_tls1;
static TLS_test l_tls2;
@endcode
@ -256,7 +260,9 @@ static void Thread2_run(QXThread * const me) {
@endcode
- access the TLS from your code:
@code{c}
<br>
@code{.c}
void lib_fun(uint32_t x) {
QXK_TLS(TLS_test *)->foo = x;
}

64
doxygen/ports_arm-cm.dox
View File

@ -10,6 +10,7 @@ To focus the discussion, this section references the **GNU-ARM toolchain**, the
@section arm-cm_files Directories and Files
The QP ports to ARM Cortex-M are available in the standard QP distribution. Specifically, the ARM Cortex-M ports are placed in the following directories:
<br>
@code{.c}
qpc/ports/arm-cm // QP/C ports to ARM Cortex-M
+---qk // QP/C ports to QK preemptive kernel
@ -226,7 +227,7 @@ The QEP header file for the ARM Cortex-M port is located in <span class="img fil
@anchor arm-cm_qv_qep_port-code
@caption{Listing: The qep_port.h header file for ARM Cortex-M}
@code{c}
@code{.c}
#include <stdint.h> /* Exact-width types. WG14/N843 C99 Standard */
#include <stdbool.h> /* Boolean type. WG14/N843 C99 Standard */
#include "qep.h" /* QEP platform-independent public interface */
@ -439,7 +440,7 @@ The QV implementation file for the ARM Cortex-M port is located in <span class="
@anchor arm-cm_qv_port_c-code
@caption{Listing: The qv_port.c header file for ARM Cortex-M}
@code{c}
@code{.c}
#include "qf_port.h"
[1] #if (__ARM_ARCH != 6) /* NOT Cortex-M0/M0+/M1 ? */
@ -501,7 +502,7 @@ The following listing shows an example of the SysTick_Handler() ISR (from the DP
@anchor arm-cm_qv-isr-code
@caption{Listing: An ISR header for QV}
@code{c}
@code{.c}
void SysTick_Handler(void) __attribute__((__interrupt__));
void SysTick_Handler(void) {
~ ~ ~
@ -524,8 +525,11 @@ If you use ARMv7M or higher CPU and your application uses the hardware FPU, it s
@note
The FPU must be enabled before executing any floating point instruction. An attempt to execute a floating point instruction will fault if the FPU is not enabled.
Depending on whether or not you use the FPU in your ISRs, the QV port allows you to configure the FPU in various ways, as described in the following sub-sections.
@note
If the FPU is configured in the project, the QV kernel initializes the FPU to use the automatic state preservation and the lazy stacking feature as follows:
@verbatim
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
@endverbatim
@subsection arm-cm_qv-fpu_noisr FPU NOT used in the ISRs
@ -535,25 +539,12 @@ If you use the FPU only at the thread-level (inside active objects) and none of
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
@endverbatim
With this setting, the Cortex-M4F processor handles the ISRs in the exact-same way as Cortex-M0-M3, that is, only the standard interrupt frame with R0-R3,R12,LR,PC,xPSR is used. This scheme is the fastest and incurs no additional CPU cycles to save and restore the FPU registers.
With this setting, the processor uses only the standard 8-register interrupt stack frame with R0-R3,R12,LR,PC,xPSR. This scheme is the fastest and incurs no additional CPU cycles to save and restore the FPU registers.
@note
@attention
This FPU setting will lead to FPU errors, if any of the ISRs indeed starts to use the FPU
@subsection arm-cm_qv-fpu_isr FPU used in the ISRs
If you use the FPU both at the thread-level (inside active objects) and in any of your ISRs as well, you should setup the FPU to use the automatic state preservation and the lazy stacking feature as follows:
@verbatim
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
@endverbatim
This will enable the lazy stacking feature of the Cortex-M4F/M7 processor [@ref ARM-AN298]. The the "automatic state saving" and "lazy stacking" are enabled by default, so you typically don't need to change these settings.
@note
As described in the ARM Application Note "Cortex-M4(F) Lazy Stacking and Context Switching" [@ref ARM-AN298], the FPU automatic state saving requires more stack plus additional CPU time to save the FPU registers, but only when the FPU is actually used.
@section arm-cm_qv-idle QV Idle Processing Customization in QV_onIdle()
When no events are available, the non-preemptive QV kernel invokes the platform-specific callback function QV_onIdle(), which you can use to save CPU power, or perform any other "idle" processing (such as Quantum Spy software trace output).
@ -565,7 +556,7 @@ Because QV_onIdle() must enable interrupts internally, the signature of the func
@anchor arm-cm_qv_onidle-code
@caption{Listing: QV_onIdle() for ARM Cortex-M}
@code{c}
@code{.c}
[1] void QV_onIdle(void) { /* entered with interrupts DISABLED, see NOTE01 */
~ ~ ~
[2] #if defined NDEBUG
@ -1125,33 +1116,11 @@ If you have the Cortex-M4F CPU and your application uses the hardware FPU, it sh
@endverbatim
@note
The FPU must be enabled before executing any floating point instruction. An attempt to execute a floating point instruction will fault if the FPU is not enabled.
Depending on wheter or not you use the FPU in your ISRs, the "Vanilla" QP port allows you to configure the FPU in various ways, as described in the following sub-sections.
@subsection arm-cm_qk-fpu_1thread FPU used in ONE thread only and not in any ISR
If you use the FPU only at a single thread (active object) and none of your ISRs use the FPU, you can setup the FPU not to use the automatic state preservation and not to use the lazy stacking feature as follows:
If the FPU is configured in the project, the QK kernel initializes the FPU to use the automatic state preservation and the lazy stacking feature as follows:
@verbatim
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
@endverbatim
With this setting, the Cortex-M4F processor handles the ISRs in the exact-same way as Cortex-M0-M3, that is, only the standard interrupt frame with R0-R3,R12,LR,PC,xPSR is used. This scheme is the fastest and incurs no additional CPU cycles to save and restore the FPU registers.
@note
This FPU setting will lead to FPU errors, if more than one thread or any of the ISRs indeed start to use the FPU
@subsection arm-cm_qk-fpu_nthreadd FPU used in more than one thread only or the ISR
If you use the FPU in more than one of the threads (active objects) or in any of your ISRs, you should setup the FPU to use the automatic state preservation and the lazy stacking feature as follows:
@verbatim
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
@endverbatim
This is actually the default setting of the hardware FPU and is recommended for the QK port, because it is safer in view of code evolution. Future changes to the application can easily introduce FPU use in multiple active objects, which would be unsafe if the FPU context was not preserved automatically.
@note
As described in the ARM Application Note "Cortex-M4(F) Lazy Stacking and Context Switching" [@ref ARM-AN298], the FPU automatic state saving requires more stack plus additional CPU time to save the FPU registers, but only when the FPU is actually used.
@ -1163,7 +1132,7 @@ The THUMB-2 instruction set used exclusively in ARM Cortex-M provides a special
@anchor arm-cm_qk_onidle-code
@caption{Listing: QV_onIdle() for ARM Cortex-M}
@code{c}
@code{.c}
[1] void QK_onIdle(void) {
~ ~ ~
@ -1189,7 +1158,8 @@ The `bsp.c` file included in the <span class="img folder">examples/arm-cm/dpp_ek
The technique described in this section will allow you to trigger an interrupt at any machine instruction and observe the preemption it causes. The interrupt used for the testing purposes is the GPIOA interrupt (INTID == 0). The ISR for this interrupt is shown below:
@code{c}
<br>
@code{.c}
void GPIOPortA_IRQHandler(void) {
QK_ISR_ENTRY(); /* inform QK about entering an ISR */
QACTIVE_POST(AO_Table, Q_NEW(QEvt, MAX_PUB_SIG), /* for testing... */

56
doxygen/ports_rtos.dox
View File

@ -93,6 +93,7 @@ The provided examples show how to write regular "kernel-aware" ISRs as well as "
Here is an example of a regular "kernel-aware" ISR (note the use of the `FromISR` suffix in the QP APIs):
<br>
@code{.c}
/* NOTE: only the "FromISR" API variants are allowed in the ISRs! */
void GPIOPortA_IRQHandler(void) {
@ -111,6 +112,7 @@ void GPIOPortA_IRQHandler(void) {
Here is an example of a "kernel-unaware" ISR (See also the FreeRTOS documentation for [configMAX_SYSCALL_INTERRUPT_PRIORITY](https://www.freertos.org/a00110.html#kernel_priority) ):
<br>
@code{.c}
/*
* ISR for receiving bytes from the QSPY Back-End
@ -134,6 +136,7 @@ void UART0_IRQHandler(void) {
@subsection freertos_hook Writing FreeRTOS Hooks Running in ISR Context
FreeRTOS provides "hooks" that are user functions that execute in the ISR context (e.g., `vApplicationTickHook()`). Such ISR-level functions are closely related to ISRs and should also use exclusively only the "FromISR" APIs. Here is an example of the `vApplicationTickHook()`:
<br>
@code{.c}
/* NOTE: only the "FromISR" API variants are allowed in vApplicationTickHook */
void vApplicationTickHook(void) {
@ -151,6 +154,7 @@ void vApplicationTickHook(void) {
@subsection freertos_ao Starting Active Objects in QP/FreeRTOS
As mentioned in the @ref freertos_about "FreeRTOS port summary", the QP port to FreeRTOS uses the [static memory allocation of FreeRTOS](https://freertos.org/Static_Vs_Dynamic_Memory_Allocation.html). This means that all memory for an active object, including the private queue buffer and the private **stack** for the the associated FreeRTOS task must be allocated by the user. Here is an example code that starts an active object:
<br>
@code{.c}
int main() {
. . .
@ -227,6 +231,7 @@ However, this port can also be used as a library, in which case you need to buil
@subsection uc-os2_build QP Source Files Needed in this QP Port
Whether you use this QP port as source files or as a library, it is important to note that not all QP source files should be included. Here is the list of QP source files needed:
<br>
@code{.c}
qpc/
+-src/
@ -307,34 +312,35 @@ The Zephyr message queue currently supports only the FIFO policy and does NOT su
@subsection zephyr_build QP Source Files Needed in this QP Port
It is important to note that **NOT** all QP source files should be included. Here is the list of QP source files needed:
@verbatim
<br>
@code{.c}
qpc/
+-src/
| | +-qf/
| | | +-qep_hsm.c
| | | +-qep_msm.c
| | | +-qf_act.c
| | | +-qf_actq.c - NOT included (implemented in Zephyr)
| | | +-qf_defer.c
| | | +-qf_dyn.c
| | | +-qf_mem.c
| | | +-qf_ps.c
| | | +-qf_qeq.c
| | | +-qf_qmact.c
| | | +-qf_time.c
| |
| | +-qs/
| | | +-qs.c - included only in the Spy build configuration
| | | +-qs_fp.c - included only in the Spy build configuration
+--src/
| +--qf/
| | qep_hsm.c
| | qep_msm.c
| | qf_act.c
| | qf_actq.c // NOT included (implemented in Zephyr)
| | qf_defer.c
| | qf_dyn.c
| | qf_mem.c
| | qf_ps.c
| | qf_qeq.c
| | qf_qmact.c
| | qf_time.c
| |
| +--qs/
| | qs.c // included only in the Spy build configuration
| | qs_fp.c // included only in the Spy build configuration
|
+-ports
| +-zephyr
| | +-qep_port.h
| | +-qf_port.h
| | +-qf_port.c - implementation of the Zephyr port
| | +-qs_port.h
+--ports/
| +--zephyr
| | qep_port.h
| | qf_port.h
| | qf_port.c // implementation of the Zephyr port
| | qs_port.h
|
@endverbatim
@endcode
@note
Specifically, the QP source files qf_actq.c must **NOT** be included in the build, because this functionality is taken from Zephyr.

10
doxygen/snippets/qxk_oncontextsw.c → doxygen/snippets/qf_oncontextsw.c
View File

@ -1,17 +1,17 @@
#ifdef QXK_ON_CONTEXT_SW
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QXK_onContextSw(QActive *prev, QActive *next) {
void QF_onContextSw(QActive *prev, QActive *next) {
(void)prev;
if (next != (QActive *)0) { /* next is not the QXK idle thread? */
if (next != (QActive *)0) { /* next is not the idle thread? */
_impure_ptr = next->thread; /* switch to next TLS */
}
/* If you use QS software tracing, use the _NOCRIT() begin/end */
QS_BEGIN_NOCRIT(ON_CONTEXT_SW, 0U)
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U)
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QXK_ON_CONTEXT_SW */
#endif /* QF_ON_CONTEXT_SW */

17
doxygen/snippets/qk_oncontextsw.c
View File

@ -1,17 +0,0 @@
#ifdef QK_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QK_onContextSw(QActive *prev, QActive *next) {
if (next != (QActive *)0) { /* next is not the QK idle loop? */
_impure_ptr = next->thread; /* switch to next TLS */
}
/* If you use QS software tracing, use the _NOCRIT() begin/end */
QS_BEGIN_NOCRIT(CONTEXT_SW, QS_AP_ID + 1)
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QK_ON_CONTEXT_SW */

26
examples/arm-cm/blinky_efm32-slstk3401a/qk/bsp.c
View File

@ -74,31 +74,7 @@ void BSP_init(void) {
*/
SystemCoreClockUpdate();
/* configure the FPU usage by choosing one of the options... */
#if 1
/* OPTION 1:
* Use the automatic FPU state preservation and the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in more than one task or
* in any ISRs. This setting is the safest and recommended, but requires
* extra stack space and CPU cycles.
*/
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
#else
/* OPTION 2:
* Do NOT to use the automatic FPU state preservation and
* do NOT to use the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in ONE task only and not
* in any ISR. This setting is very efficient, but if more than one task
* (or ISR) start using the FPU, this can lead to corruption of the
* FPU registers. This option should be used with CAUTION.
*/
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos)
| (1U << FPU_FPCCR_LSPEN_Pos));
#endif
/* NOTE The VFP (hardware Floating Point) unit is configured by QK-port */
/* enable clock for to the peripherals used by this application... */
CMU_ClockEnable(cmuClock_HFPER, true);

12
examples/arm-cm/blinky_efm32-slstk3401a/qv/bsp.c
View File

@ -73,17 +73,7 @@ void BSP_init(void) {
*/
SystemCoreClockUpdate();
/* configure the FPU usage by choosing one of the options...
*
* Do NOT to use the automatic FPU state preservation and
* do NOT to use the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used only by active objects
* and NOT in any ISR. This setting is very efficient, but if any ISRs
* start using the FPU, this can lead to corruption of the FPU registers.
*/
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
/* NOTE The VFP (hardware Floating Point) unit is configured by QV-port */
/* enable clock for to the peripherals used by this application... */
CMU_ClockEnable(cmuClock_HFPER, true);

216
examples/arm-cm/blinky_ek-tm4c123gxl/qk/bsp.c
View File

@ -1,7 +1,7 @@
/*****************************************************************************
* Product: "Blinky" example, EK-TM4C123GXL board, preemptive QK kernel
* Last updated for version 6.9.1
* Last updated on 2020-09-22
* Last updated for version 7.2.0
* Last updated on 2022-12-17
*
* Q u a n t u m L e a P s
* ------------------------
@ -68,67 +68,168 @@ void SysTick_Handler(void) {
/* BSP functions ===========================================================*/
/* MPU setup for TM4C123GXL MCU */
static void TM4C123GXL_MPU_setup(void) {
/* The following MPU configuration contains the general TM4C memory map.
*
* Please note that the actual TM4C MCUs provide much less Flash and SRAM
* than the maximums configured here. This means that actual MCUs have
* unmapped memory regions (e.g., beyond the actual SRAM). Attempts to
* access these regions causes the HardFault exception, which is the
* desired behavior.
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #1: SRAM: base=0x2000'0000, size=512M=2^(28+1) */
0x20000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 1U), /* region #1 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
/* region #3: (not configured) */
{ MPU_RBAR_VALID_Msk | (MPU_RBAR_REGION_Msk & 2U), 0U },
{ /* region #3: Peripherals: base=0x4000'0000, size=512M=2^(28+1) */
0x40000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 3U), /* region #3 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #4: Priv. Periph: base=0xE000'0000, size=512M=2^(28+1) */
0xE0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 4U), /* region #4 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #5: Ext RAM: base=0x6000'0000, size=1G=2^(29+1) */
0x60000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 5U), /* region #5 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #6: Ext Dev: base=0xA000'0000, size=1G=2^(29+1) */
0xA0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 6U), /* region #6 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=256B */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(7U << MPU_RASR_SIZE_Pos) /* 2^(7+1)=256B region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_ENABLE_Msk; /* enable the MPU */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
TM4C123GXL_MPU_setup();
/* NOTE: SystemInit() already called from the startup code
* but SystemCoreClock needs to be updated
*/
SystemCoreClockUpdate();
/* configure the FPU usage by choosing one of the options... */
#if 1
/* OPTION 1:
* Use the automatic FPU state preservation and the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in more than one task or
* in any ISRs. This setting is the safest and recommended, but requires
* extra stack space and CPU cycles.
*/
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
#else
/* OPTION 2:
* Do NOT to use the automatic FPU state preservation and
* do NOT to use the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in ONE task only and not
* in any ISR. This setting is very efficient, but if more than one task
* (or ISR) start using the FPU, this can lead to corruption of the
* FPU registers. This option should be used with CAUTION.
*/
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos)
| (1U << FPU_FPCCR_LSPEN_Pos));
#endif
/* NOTE: The VFP (hardware Floating Point) unit is configured by QK */
/* enable clock for to the peripherals used by this application... */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */
__ISB();
__DSB();
/* configure the LEDs and push buttons */
GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE);/* set direction: output */
GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); /* digital enable */
GPIOF->DATA_Bits[LED_RED] = 0U; /* turn the LED off */
GPIOF->DATA_Bits[LED_GREEN] = 0U; /* turn the LED off */
GPIOF->DATA_Bits[LED_BLUE] = 0U; /* turn the LED off */
/* configure LEDs (digital output) */
GPIOF_AHB->DIR |= (LED_RED | LED_BLUE | LED_GREEN);
GPIOF_AHB->DEN |= (LED_RED | LED_BLUE | LED_GREEN);
GPIOF_AHB->DATA_Bits[LED_RED | LED_BLUE | LED_GREEN] = 0U;
/* configure the Buttons */
GPIOF->DIR &= ~(BTN_SW1 | BTN_SW2); /* set direction: input */
ROM_GPIOPadConfigSet(GPIOF_BASE, (BTN_SW1 | BTN_SW2),
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
}
/*..........................................................................*/
void BSP_ledOff(void) {
GPIOF->DATA_Bits[LED_GREEN] = 0U;
/* configure switches... */
/* unlock access to the SW2 pin because it is PROTECTED */
GPIOF_AHB->LOCK = 0x4C4F434BU; /* unlock GPIOCR register for SW2 */
/* commit the write (cast const away) */
*(uint32_t volatile *)&GPIOF_AHB->CR = 0x01U;
GPIOF_AHB->DIR &= ~(BTN_SW1 | BTN_SW2); /* input */
GPIOF_AHB->DEN |= (BTN_SW1 | BTN_SW2); /* digital enable */
GPIOF_AHB->PUR |= (BTN_SW1 | BTN_SW2); /* pull-up resistor enable */
*(uint32_t volatile *)&GPIOF_AHB->CR = 0x00U;
GPIOF_AHB->LOCK = 0x0; /* lock GPIOCR register for SW2 */
}
/*..........................................................................*/
void BSP_ledOn(void) {
/* exercise the FPU with some floating point computations */
GPIOF_AHB->DATA_Bits[LED_RED] = 0xFFU;
}
/*..........................................................................*/
void BSP_ledOff(void) {
/* exercise the FPU with some floating point computations */
float volatile x = 3.1415926F;
x = x + 2.7182818F;
GPIOF->DATA_Bits[LED_GREEN] = 0xFFU;
GPIOF_AHB->DATA_Bits[LED_RED] = 0x00U;
}
/* QF callbacks ============================================================*/
void QF_onStartup(void) {
/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */
@ -152,17 +253,23 @@ void QF_onStartup(void) {
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QF_onContextSw(QActive *prev, QActive *next) {
}
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QK_onIdle(void) {
/* toggle LED2 on and then off, see NOTE01 */
/* toggle the User LED on and then off, see NOTE2 */
QF_INT_DISABLE();
GPIOF->DATA_Bits[LED_BLUE] = 0xFFU;
GPIOF->DATA_Bits[LED_BLUE] = 0x00U;
GPIOF_AHB->DATA_Bits[LED_BLUE] = 0xFFU; /* turn the Blue LED on */
GPIOF_AHB->DATA_Bits[LED_BLUE] = 0U; /* turn the Blue LED off */
QF_INT_ENABLE();
#ifdef NDEBUG
/* Put the CPU and peripherals to the low-power mode.
* you might need to customize the clock management for your application,
* see the datasheet for your particular Cortex-M3 MCU.
* see the datasheet for your particular Cortex-M MCU.
*/
__WFI(); /* Wait-For-Interrupt */
#endif
@ -179,7 +286,7 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
NVIC_SystemReset();
}
/*****************************************************************************
/*============================================================================
* NOTE1:
* The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
* ISR priority that is disabled by the QF framework. The value is suitable
@ -187,18 +294,19 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
*
* Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e.,
* with the numerical values of priorities equal or higher than
* QF_AWARE_ISR_CMSIS_PRI) are allowed to call any QF services. These ISRs
* are "QF-aware".
* QF_AWARE_ISR_CMSIS_PRI) are allowed to call the QXK_ISR_ENTRY/QXK_ISR_EXIT
* macros or any other QF/QXK services. These ISRs are "QF-aware".
*
* Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority
* level (i.e., with the numerical values of priorities less than
* QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel.
* Such "QF-unaware" ISRs cannot call any QF services. The only mechanism
* Such "QF-unaware" ISRs cannot call any QF/QXK services. In particular they
* can NOT call the macros QXK_ISR_ENTRY/QXK_ISR_ENTRY. The only mechanism
* by which a "QF-unaware" ISR can communicate with the QF framework is by
* triggering a "QF-aware" ISR, which can post/publish events.
*
* NOTE2:
* One of the LEDs is used to visualize the idle loop activity. The brightness
* The User LED is used to visualize the idle loop activity. The brightness
* of the LED is proportional to the frequency of invcations of the idle loop.
* Please note that the LED is toggled with interrupts locked, so no interrupt
* execution time contributes to the brightness of the User LED.

198
examples/arm-cm/blinky_ek-tm4c123gxl/qv/bsp.c
View File

@ -1,7 +1,7 @@
/*****************************************************************************
* Product: "Blinky" on EK-TM4C123GXL board, cooperative Vanilla kernel
* Last updated for version 6.9.1
* Last updated on 2020-09-23
* Last updated for version 7.2.0
* Last updated on 2022-12-17
*
* Q u a n t u m L e a P s
* ------------------------
@ -66,53 +66,168 @@ void SysTick_Handler(void) {
}
/* BSP functions ===========================================================*/
/* MPU setup for TM4C123GXL MCU */
static void TM4C123GXL_MPU_setup(void) {
/* The following MPU configuration contains the general TM4C memory map.
*
* Please note that the actual TM4C MCUs provide much less Flash and SRAM
* than the maximums configured here. This means that actual MCUs have
* unmapped memory regions (e.g., beyond the actual SRAM). Attempts to
* access these regions causes the HardFault exception, which is the
* desired behavior.
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #1: SRAM: base=0x2000'0000, size=512M=2^(28+1) */
0x20000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 1U), /* region #1 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
/* region #3: (not configured) */
{ MPU_RBAR_VALID_Msk | (MPU_RBAR_REGION_Msk & 2U), 0U },
{ /* region #3: Peripherals: base=0x4000'0000, size=512M=2^(28+1) */
0x40000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 3U), /* region #3 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #4: Priv. Periph: base=0xE000'0000, size=512M=2^(28+1) */
0xE0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 4U), /* region #4 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #5: Ext RAM: base=0x6000'0000, size=1G=2^(29+1) */
0x60000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 5U), /* region #5 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #6: Ext Dev: base=0xA000'0000, size=1G=2^(29+1) */
0xA0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 6U), /* region #6 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=256B */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(7U << MPU_RASR_SIZE_Pos) /* 2^(7+1)=256B region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_ENABLE_Msk; /* enable the MPU */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
TM4C123GXL_MPU_setup();
/* NOTE: SystemInit() already called from the startup code
* but SystemCoreClock needs to be updated
*/
SystemCoreClockUpdate();
/* configure the FPU usage by choosing one of the options...
*
* Do NOT to use the automatic FPU state preservation and
* do NOT to use the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used only by active objects
* and NOT in any ISR. This setting is very efficient, but if any ISRs
* start using the FPU, this can lead to corruption of the FPU registers.
*/
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
/* NOTE: The VFP (hardware Floating Point) unit is configured by QV */
/* enable clock for to the peripherals used by this application... */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */
__ISB();
__DSB();
/* configure the LEDs and push buttons */
GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE);/* set direction: output */
GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); /* digital enable */
GPIOF->DATA_Bits[LED_RED] = 0U; /* turn the LED off */
GPIOF->DATA_Bits[LED_GREEN] = 0U; /* turn the LED off */
GPIOF->DATA_Bits[LED_BLUE] = 0U; /* turn the LED off */
/* configure LEDs (digital output) */
GPIOF_AHB->DIR |= (LED_RED | LED_BLUE | LED_GREEN);
GPIOF_AHB->DEN |= (LED_RED | LED_BLUE | LED_GREEN);
GPIOF_AHB->DATA_Bits[LED_RED | LED_BLUE | LED_GREEN] = 0U;
/* configure the Buttons */
GPIOF->DIR &= ~(BTN_SW1 | BTN_SW2); /* set direction: input */
ROM_GPIOPadConfigSet(GPIOF_BASE, (BTN_SW1 | BTN_SW2),
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
}
/*..........................................................................*/
void BSP_ledOff(void) {
GPIOF->DATA_Bits[LED_GREEN] = 0U;
/* configure switches... */
/* unlock access to the SW2 pin because it is PROTECTED */
GPIOF_AHB->LOCK = 0x4C4F434BU; /* unlock GPIOCR register for SW2 */
/* commit the write (cast const away) */
*(uint32_t volatile *)&GPIOF_AHB->CR = 0x01U;
GPIOF_AHB->DIR &= ~(BTN_SW1 | BTN_SW2); /* input */
GPIOF_AHB->DEN |= (BTN_SW1 | BTN_SW2); /* digital enable */
GPIOF_AHB->PUR |= (BTN_SW1 | BTN_SW2); /* pull-up resistor enable */
*(uint32_t volatile *)&GPIOF_AHB->CR = 0x00U;
GPIOF_AHB->LOCK = 0x0; /* lock GPIOCR register for SW2 */
}
/*..........................................................................*/
void BSP_ledOn(void) {
/* exercise the FPU with some floating point computations */
GPIOF_AHB->DATA_Bits[LED_RED] = 0xFFU;
}
/*..........................................................................*/
void BSP_ledOff(void) {
/* exercise the FPU with some floating point computations */
float volatile x = 3.1415926F;
x = x + 2.7182818F;
GPIOF->DATA_Bits[LED_GREEN] = 0xFFU;
GPIOF_AHB->DATA_Bits[LED_RED] = 0x00U;
}
/* QF callbacks ============================================================*/
void QF_onStartup(void) {
/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */
@ -136,10 +251,16 @@ void QF_onStartup(void) {
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QF_onContextSw(QActive *prev, QActive *next) {
}
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QV_onIdle(void) { /* CATION: called with interrupts DISABLED, NOTE2 */
/* toggle LED2 on and then off, see NOTE3 */
GPIOF->DATA_Bits[LED_BLUE] = 0xFFU;
GPIOF->DATA_Bits[LED_BLUE] = 0x00U;
/* toggle the User LED on and then off, see NOTE2 */
GPIOF_AHB->DATA_Bits[LED_BLUE] = 0xFFU; /* turn the Blue LED on */
GPIOF_AHB->DATA_Bits[LED_BLUE] = 0U; /* turn the Blue LED off */
#ifdef NDEBUG
/* Put the CPU and peripherals to the low-power mode.
@ -163,7 +284,7 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
NVIC_SystemReset();
}
/*****************************************************************************
/*============================================================================
* NOTE1:
* The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
* ISR priority that is disabled by the QF framework. The value is suitable
@ -171,13 +292,14 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
*
* Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e.,
* with the numerical values of priorities equal or higher than
* QF_AWARE_ISR_CMSIS_PRI) are allowed to call any QF services. These ISRs
* are "QF-aware".
* QF_AWARE_ISR_CMSIS_PRI) are allowed to call the QXK_ISR_ENTRY/QXK_ISR_EXIT
* macros or any other QF/QXK services. These ISRs are "QF-aware".
*
* Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority
* level (i.e., with the numerical values of priorities less than
* QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel.
* Such "QF-unaware" ISRs cannot call any QF services. The only mechanism
* Such "QF-unaware" ISRs cannot call any QF/QXK services. In particular they
* can NOT call the macros QXK_ISR_ENTRY/QXK_ISR_ENTRY. The only mechanism
* by which a "QF-unaware" ISR can communicate with the QF framework is by
* triggering a "QF-aware" ISR, which can post/publish events.
*

2
examples/arm-cm/dpp_efm32-slstk3401a/dpp.h
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::dpp.h}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later

2
examples/arm-cm/dpp_efm32-slstk3401a/dpp.qm
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<model version="5.2.1" links="1">
<model version="5.2.4" links="1">
<documentation>Dining Philosopher Problem example</documentation>
<!--${qpc}-->
<framework name="qpc"/>

6
examples/arm-cm/dpp_efm32-slstk3401a/philo.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::philo.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -68,8 +68,8 @@ static QState Philo_eating(Philo * const me, QEvt const * const e);
/* Global objects ----------------------------------------------------------*/
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

71
examples/arm-cm/dpp_efm32-slstk3401a/qk/armclang/dpp-qk.uvoptx
View File

@ -140,7 +140,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=1913,720,2363,1277,1)(1007=1124,641,1311,916,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
<Name>(1010=1913,720,2363,1277,0)(1007=1124,641,1311,916,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=2701,333,3178,648,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -153,12 +153,77 @@
<Name>-U0E2006F4 -O4622 -S4 -FO61</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>377</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>6704</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\bsp.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qk\../bsp.c\377</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>413</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>446</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\..\..\..\..\3rd_party\efm32pg1b\arm\startup_efm32pg1b.s</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qk\../../../../../3rd_party/efm32pg1b/arm/startup_efm32pg1b.s\413</Expression>
</Bp>
<Bp>
<Number>2</Number>
<Type>0</Type>
<LineNumber>216</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>376</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\..\..\..\..\3rd_party\efm32pg1b\arm\startup_efm32pg1b.s</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qk\../../../../../3rd_party/efm32pg1b/arm/startup_efm32pg1b.s\216</Expression>
</Bp>
<Bp>
<Number>3</Number>
<Type>0</Type>
<LineNumber>228</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>382</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\..\..\..\..\3rd_party\efm32pg1b\arm\startup_efm32pg1b.s</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qk\../../../../../3rd_party/efm32pg1b/arm/startup_efm32pg1b.s\228</Expression>
</Bp>
</Breakpoint>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<SubType>2</SubType>
<ItemText>0x20000200</ItemText>
<ItemText>0x20000B70</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>

2
examples/arm-cm/dpp_efm32-slstk3401a/qk/armclang/dpp-qk.uvprojx
View File

@ -183,7 +183,7 @@
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsVP>1</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>

198
examples/arm-cm/dpp_efm32-slstk3401a/qk/bsp.c
View File

@ -1,7 +1,7 @@
/*****************************************************************************
* Product: DPP example, EFM32-SLSTK3401A board, preemptive QK kernel
* Last updated for version 6.9.3
* Last updated on 2021-03-03
* Last updated for version 7.2.0
* Last updated on 2022-12-17
*
* Q u a n t u m L e a P s
* ------------------------
@ -79,32 +79,22 @@ static uint32_t l_rnd; /* random seed */
/*..........................................................................*/
void SysTick_Handler(void) {
/* state of the button debouncing, see below */
static struct ButtonsDebouncing {
uint32_t depressed;
uint32_t previous;
} buttons = { 0U, 0U };
uint32_t current;
uint32_t tmp;
QK_ISR_ENTRY(); /* inform QK about entering an ISR */
#ifdef Q_SPY
{
tmp = SysTick->CTRL; /* clear SysTick_CTRL_COUNTFLAG */
QS_tickTime_ += QS_tickPeriod_; /* account for the clock rollover */
}
#endif
QTIMEEVT_TICK_X(0U, &l_SysTick_Handler); /* process time events for rate 0 */
QTIMEEVT_TICK_X(0U, &l_SysTick_Handler); /* process time-evts for rate 0 */
//QACTIVE_POST(the_Ticker0, 0, &l_SysTick_Handler); /* post to Ticker0 */
/* Perform the debouncing of buttons. The algorithm for debouncing
* adapted from the book "Embedded Systems Dictionary" by Jack Ganssle
* and Michael Barr, page 71.
*/
current = ~GPIO->P[PB_PORT].DIN; /* read PB0 and BP1 */
tmp = buttons.depressed; /* save the debounced depressed buttons */
/* state of the button debouncing, see below */
static struct ButtonsDebouncing {
uint32_t depressed;
uint32_t previous;
} buttons = { 0U, 0U };
uint32_t current = ~GPIO->P[PB_PORT].DIN; /* read PB0 and BP1 */
uint32_t tmp = buttons.depressed; /* the debounced depressed buttons */
buttons.depressed |= (buttons.previous & current); /* set depressed */
buttons.depressed &= (buttons.previous | current); /* clear released */
buttons.previous = current; /* update the history */
@ -120,6 +110,13 @@ void SysTick_Handler(void) {
}
}
#ifdef Q_SPY
{
tmp = SysTick->CTRL; /* clear SysTick_CTRL_COUNTFLAG */
QS_tickTime_ += QS_tickPeriod_; /* account for the clock rollover */
}
#endif
QK_ISR_EXIT(); /* inform QK about exiting an ISR */
}
/*..........................................................................*/
@ -153,36 +150,131 @@ void USART0_RX_IRQHandler(void) {}
/* BSP functions ===========================================================*/
/* MPU setup for EFM32PG1B200F256GM48 MCU */
static void EFM32PG182_MPU_setup(void) {
/* The following MPU configuration contains the general EFM32PG1 memory
* map described in the EFM32PG1 Data Sheet Figure 3.2. EFM32PG1 Memory Map
*
* Please note that the actual STM32 MCUs provide much less Flash and SRAM
* than the maximums configured here. This means that actual MCUs have
* unmapped memory regions (e.g., beyond the actual SRAM). Attempts to
* access these regions causes the HardFault exception, which is the
* desired behavior.
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #1: SRAM: base=0x2000'0000, size=512M=2^(28+1) */
0x20000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 1U), /* region #1 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
/* region #3: (not configured) */
{ MPU_RBAR_VALID_Msk | (MPU_RBAR_REGION_Msk & 2U), 0U },
{ /* region #3: Peripherals: base=0x4000'0000, size=512M=2^(28+1) */
0x40000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 3U), /* region #3 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #4: Priv. Periph: base=0xE000'0000, size=512M=2^(28+1) */
0xE0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 4U), /* region #4 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #5: Ext RAM: base=0x6000'0000, size=1G=2^(29+1) */
0x60000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 5U), /* region #5 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #6: Ext Dev: base=0xA000'0000, size=1G=2^(29+1) */
0xA0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 6U), /* region #6 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=256B, NOTE0 */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(7U << MPU_RASR_SIZE_Pos) /* 2^(7+1)=256B region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_ENABLE_Msk; /* enable the MPU */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
EFM32PG182_MPU_setup();
/* NOTE: SystemInit() already called from the startup code
* but SystemCoreClock needs to be updated
*/
SystemCoreClockUpdate();
/* configure the FPU usage by choosing one of the options... */
#if 1
/* OPTION 1:
* Use the automatic FPU state preservation and the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in more than one task or
* in any ISRs. This setting is the safest and recommended, but requires
* extra stack space and CPU cycles.
*/
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
#else
/* OPTION 2:
* Do NOT to use the automatic FPU state preservation and
* do NOT to use the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in ONE task only and not
* in any ISR. This setting is very efficient, but if more than one task
* (or ISR) start using the FPU, this can lead to corruption of the
* FPU registers. This option should be used with CAUTION.
*/
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
#endif
/* NOTE: The VFP (hardware Floating Point) unit is configured by QK-port */
/* enable clock for to the peripherals used by this application... */
CMU_ClockEnable(cmuClock_HFPER, true);
@ -292,7 +384,7 @@ void QF_onStartup(void) {
/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */
SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);
/* assing all priority bits for preemption-prio. and none to sub-prio. */
/* assign all priority bits for preemption-prio. and none to sub-prio. */
NVIC_SetPriorityGrouping(0U);
/* set priorities of ALL ISRs used in the system, see NOTE1
@ -358,8 +450,8 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
#ifndef NDEBUG
/* light up both LEDs */
GPIO->P[LED_PORT].DOUT |= ((1U << LED0_PIN) | (1U << LED1_PIN));
/* for debugging, hang on in an endless loop until PB1 is pressed... */
while ((GPIO->P[PB_PORT].DIN & (1U << PB1_PIN)) != 0) {
/* for debugging, hang on in an endless loop... */
for (;;) {
}
#endif
@ -473,7 +565,7 @@ void QS_onCommand(uint8_t cmdId,
(void)param1;
(void)param2;
(void)param3;
QS_BEGIN_ID(COMMAND_STAT, 0U) /* application-specific record begin */
QS_BEGIN_ID(COMMAND_STAT, 0U) /* app-specific record */
QS_U8(2, cmdId);
QS_U32(8, param1);
QS_U32(8, param2);
@ -491,7 +583,15 @@ void QS_onCommand(uint8_t cmdId,
#endif /* Q_SPY */
/*--------------------------------------------------------------------------*/
/*****************************************************************************
/*============================================================================
* NOTE0:
* The MPU protection against NULL-pointer dereferencing sets up a no-access
* MPU region #7 around the NULL address (0x0). This works even though the
* Vector Table also resides at address 0x0. However, the *size* of the
* no-access region should not exceed the size of the Vector Table. In this
* case, the size is set to 2**(7+1)==256 bytes, which does not contain any
* data that the CPU would legitimately read with the LDR instruction.
*
* NOTE1:
* The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
* ISR priority that is disabled by the QF framework. The value is suitable

201
examples/arm-cm/dpp_efm32-slstk3401a/qv/bsp.c
View File

@ -1,7 +1,7 @@
/*****************************************************************************
* Product: DPP example, EFM32-SLSTK3401A board, cooperative QV kernel
* Last updated for version 6.9.3
* Last updated on 2021-03-03
* Last updated for version 7.2.0
* Last updated on 2022-12-17
*
* Q u a n t u m L e a P s
* ------------------------
@ -79,30 +79,20 @@ static uint32_t l_rnd; /* random seed */
/*..........................................................................*/
void SysTick_Handler(void) {
/* state of the button debouncing, see below */
static struct ButtonsDebouncing {
uint32_t depressed;
uint32_t previous;
} buttons = { 0U, 0U };
uint32_t current;
uint32_t tmp;
#ifdef Q_SPY
{
tmp = SysTick->CTRL; /* clear SysTick_CTRL_COUNTFLAG */
QS_tickTime_ += QS_tickPeriod_; /* account for the clock rollover */
}
#endif
//QTIMEEVT_TICK_X(0U, &l_SysTick_Handler); /* process time events for rate 0 */
QACTIVE_POST(the_Ticker0, 0, &l_SysTick_Handler); /* post to Ticker0 */
QTIMEEVT_TICK_X(0U, &l_SysTick_Handler); /* process time-evts for rate 0 */
//QACTIVE_POST(the_Ticker0, 0, &l_SysTick_Handler); /* post to Ticker0 */
/* Perform the debouncing of buttons. The algorithm for debouncing
* adapted from the book "Embedded Systems Dictionary" by Jack Ganssle
* and Michael Barr, page 71.
*/
current = ~GPIO->P[PB_PORT].DIN; /* read PB0 and BP1 */
tmp = buttons.depressed; /* save the debounced depressed buttons */
/* state of the button debouncing, see below */
static struct ButtonsDebouncing {
uint32_t depressed;
uint32_t previous;
} buttons = { 0U, 0U };
uint32_t current = ~GPIO->P[PB_PORT].DIN; /* read PB0 and BP1 */
uint32_t tmp = buttons.depressed; /* the debounced depressed buttons */
buttons.depressed |= (buttons.previous & current); /* set depressed */
buttons.depressed &= (buttons.previous | current); /* clear released */
buttons.previous = current; /* update the history */
@ -117,6 +107,13 @@ void SysTick_Handler(void) {
QACTIVE_PUBLISH(&serveEvt, &l_SysTick_Handler);
}
}
#ifdef Q_SPY
{
tmp = SysTick->CTRL; /* clear SysTick_CTRL_COUNTFLAG */
QS_tickTime_ += QS_tickPeriod_; /* account for the clock rollover */
}
#endif
QV_ARM_ERRATUM_838869();
}
/*..........................................................................*/
@ -144,37 +141,133 @@ void USART0_RX_IRQHandler(void) {
void USART0_RX_IRQHandler(void) {}
#endif
/* BSP functions ===========================================================*/
/* MPU setup for EFM32PG1B200F256GM48 MCU */
static void EFM32PG182_MPU_setup(void) {
/* The following MPU configuration contains the general EFM32PG1 memory
* map described in the EFM32PG1 Data Sheet Figure 3.2. EFM32PG1 Memory Map
*
* Please note that the actual STM32 MCUs provide much less Flash and SRAM
* than the maximums configured here. This means that actual MCUs have
* unmapped memory regions (e.g., beyond the actual SRAM). Attempts to
* access these regions causes the HardFault exception, which is the
* desired behavior.
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #1: SRAM: base=0x2000'0000, size=512M=2^(28+1) */
0x20000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 1U), /* region #1 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
/* region #3: (not configured) */
{ MPU_RBAR_VALID_Msk | (MPU_RBAR_REGION_Msk & 2U), 0U },
{ /* region #3: Peripherals: base=0x4000'0000, size=512M=2^(28+1) */
0x40000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 3U), /* region #3 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #4: Priv. Periph: base=0xE000'0000, size=512M=2^(28+1) */
0xE0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 4U), /* region #4 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #5: Ext RAM: base=0x6000'0000, size=1G=2^(29+1) */
0x60000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 5U), /* region #5 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #6: Ext Dev: base=0xA000'0000, size=1G=2^(29+1) */
0xA0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 6U), /* region #6 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=256B, NOTE0 */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(7U << MPU_RASR_SIZE_Pos) /* 2^(7+1)=256B region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_ENABLE_Msk; /* enable the MPU */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
EFM32PG182_MPU_setup();
/* NOTE: SystemInit() already called from the startup code
* but SystemCoreClock needs to be updated
*/
SystemCoreClockUpdate();
/* configure the FPU usage by choosing one of the options... */
#if 1
/* OPTION 1:
* Use the automatic FPU state preservation and the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in more than one task or
* in any ISRs. This setting is the safest and recommended, but requires
* extra stack space and CPU cycles.
*/
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
#else
/* OPTION 2:
* Do NOT to use the automatic FPU state preservation and
* do NOT to use the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in ONE task only and not
* in any ISR. This setting is very efficient, but if more than one task
* (or ISR) start using the FPU, this can lead to corruption of the
* FPU registers. This option should be used with CAUTION.
*/
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
#endif
/* NOTE The VFP (hardware Floating Point) unit is configured by QV-port */
/* enable clock for to the peripherals used by this application... */
CMU_ClockEnable(cmuClock_HFPER, true);
@ -192,7 +285,7 @@ void BSP_init(void) {
GPIO_PinModeSet(PB_PORT, PB0_PIN, gpioModeInputPull, 1);
GPIO_PinModeSet(PB_PORT, PB1_PIN, gpioModeInputPull, 1);
//...
/*... */
BSP_randomSeed(1234U);
if (QS_INIT((void *)0) == 0) { /* initialize the QS software tracing */
@ -231,7 +324,7 @@ void BSP_displayPhilStat(uint8_t n, char const *stat) {
QS_BEGIN_ID(PHILO_STAT, AO_Philo[n]->prio) /* app-specific record */
QS_U8(1, n); /* Philosopher number */
QS_STR(stat); /* Philosopher status */
QS_END()
QS_END() /* application-specific record end */
}
/*..........................................................................*/
void BSP_displayPaused(uint8_t paused) {
@ -267,7 +360,7 @@ void BSP_terminate(int16_t result) {
(void)result;
}
/*..........................................................................*/
/* QF callbacks ============================================================*/
void QF_onStartup(void) {
/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */
SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);
@ -434,7 +527,7 @@ void QS_onFlush(void) {
/* while TXE not empty */
while ((l_USART0->STATUS & USART_STATUS_TXBL) == 0U) {
}
l_USART0->TXDATA = (b & 0xFFU); /* put into the DR register */
l_USART0->TXDATA = (b & 0xFFU); /* put into the DR register */
QF_INT_DISABLE();
}
QF_INT_ENABLE();
@ -472,7 +565,15 @@ void QS_onCommand(uint8_t cmdId,
#endif /* Q_SPY */
/*--------------------------------------------------------------------------*/
/*****************************************************************************
/*============================================================================
* NOTE0:
* The MPU protection against NULL-pointer dereferencing sets up a no-access
* MPU region #7 around the NULL address (0x0). This works even though the
* Vector Table also resides at address 0x0. However, the *size* of the
* no-access region should not exceed the size of the Vector Table. In this
* case, the size is set to 2**(7+1)==256 bytes, which does not contain any
* data that the CPU would legitimately read with the LDR instruction.
*
* NOTE1:
* The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
* ISR priority that is disabled by the QF framework. The value is suitable

2
examples/arm-cm/dpp_efm32-slstk3401a/qxk/armclang/dpp-qxk.uvprojx
View File

@ -1677,7 +1677,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>Q_SPY QXK_ON_CONTEXT_SW QXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler QXK_USE_IRQ_NUM=25
<Define>Q_SPY QF_ON_CONTEXT_SW QXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler QXK_USE_IRQ_NUM=25
</Define>
<Undefine></Undefine>
<IncludePath>..\..;..\..\..\..\..\include;..\..\..\..\..\ports\arm-cm\qxk\armclang;..\..\..\..\..\3rd_party\CMSIS\Include;..\..\..\..\..\3rd_party\efm32pg1b</IncludePath>

14
examples/arm-cm/dpp_efm32-slstk3401a/qxk/bsp.c
View File

@ -1,7 +1,7 @@
/*****************************************************************************
* Product: DPP example, EFM32-SLSTK3401A board, preemptive QXK kernel
* Last updated for version 7.1.0
* Last updated on 2022-08-28
* Last updated for version 7.2.0
* Last updated on 2022-12-22
*
* Q u a n t u m L e a P s
* ------------------------
@ -206,8 +206,6 @@ void BSP_init(void) {
QS_USR_DICTIONARY(CONTEXT_SW);
QS_USR_DICTIONARY(COMMAND_STAT);
QS_FUN_DICTIONARY(&QHsm_top);
/* setup the QS filters... */
QS_GLB_FILTER(QS_ALL_RECORDS); /* all records */
QS_GLB_FILTER(-QS_QF_TICK); /* exclude the clock tick */
@ -310,9 +308,9 @@ void QF_onStartup(void) {
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QXK_ON_CONTEXT_SW
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QXK_onContextSw(QActive *prev, QActive *next) {
void QF_onContextSw(QActive *prev, QActive *next) {
(void)prev;
if (next != (QActive *)0) {
//_impure_ptr = next->thread; /* switch to next TLS */
@ -322,7 +320,7 @@ void QXK_onContextSw(QActive *prev, QActive *next) {
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QXK_ON_CONTEXT_SW */
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QXK_onIdle(void) {
float volatile x;
@ -334,7 +332,7 @@ void QXK_onIdle(void) {
GPIO->P[LED_PORT].DOUT &= ~(1U << LED1_PIN);
QF_INT_ENABLE();
*/
/* Some flating point code is to exercise the VFP... */
/* Some floating point code is to exercise the VFP... */
x = 1.73205F;
x = x * 1.73205F;

6
examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile
View File

@ -1,7 +1,7 @@
##############################################################################
# Product: Makefile for QP/C on EMF32-SLSTK3401A, QXK kernel, GNU-ARM
# Last Updated for Version: 7.0.2
# Date of the Last Update: 2022-08-18
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-13
#
# Q u a n t u m L e a P s
# ------------------------
@ -142,7 +142,7 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
-DQXK_ON_CONTEXT_SW \
-DQF_ON_CONTEXT_SW \
-DQXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler \
-DQXK_USE_IRQ_NUM=25

8
examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-nassert
View File

@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C on EMF32-SLSTK3401A, QXK kernel, GNU-ARM
# Last Updated for Version: 7.1.0
# Date of the Last Update: 2022-08-28
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-13
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
# Copyright (C) 2005-2022 Quantum Leaps, LLC. All rights reserved.
# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@ -142,7 +142,7 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
-DQXK_ON_CONTEXT_SW \
-DQF_ON_CONTEXT_SW \
-DQXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler \
-DQXK_USE_IRQ_NUM=25 \
-DQ_NASSERT

2
examples/arm-cm/dpp_efm32-slstk3401a/qxk/iar/dpp-qxk.ewp
View File

@ -217,7 +217,7 @@
<state>EFM32PG1B200F256GM48</state>
<state>QXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler</state>
<state>QXK_USE_IRQ_NUM=25</state>
<state>QXK_ON_CONTEXT_SW=1</state>
<state>QF_ON_CONTEXT_SW</state>
</option>
<option>
<name>CCPreprocFile</name>

6
examples/arm-cm/dpp_efm32-slstk3401a/table.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::table.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -65,8 +65,8 @@ static QState Table_paused(Table * const me, QEvt const * const e);
/* Global-scope objects ----------------------------------------------------*/
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

2
examples/arm-cm/dpp_ek-tm4c123gxl/dpp.h
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::dpp.h}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later

2
examples/arm-cm/dpp_ek-tm4c123gxl/dpp.qm
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<model version="5.2.2" links="1">
<model version="5.2.4" links="1">
<documentation>Dining Philosopher Problem example</documentation>
<!--${qpc}-->
<framework name="qpc"/>

6
examples/arm-cm/dpp_ek-tm4c123gxl/philo.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::philo.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -68,8 +68,8 @@ static inline uint8_t PHILO_ID(Philo * const me) {
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

43
examples/arm-cm/dpp_ek-tm4c123gxl/qk/armclang/dpp-qk.uvoptx
View File

@ -117,6 +117,10 @@
<pMon>BIN\lmidk-agdi.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
@ -130,7 +134,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=2637,758,3114,1073,1)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -140,10 +144,43 @@
<SetRegEntry>
<Number>0</Number>
<Key>lmidk-agdi</Key>
<Name>-U0E2006F4 -O4878 -S5 -FO29</Name>
<Name>-U0E10259B -O4686 -S5 -FO29</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>392</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>1698</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\bsp.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qk\../bsp.c\392</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>681</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>1270</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\..\..\..\..\3rd_party\ek-tm4c123gxl\arm\startup_TM4C123GH6PM.s</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qk\../../../../../3rd_party/ek-tm4c123gxl/arm/startup_TM4C123GH6PM.s\681</Expression>
</Bp>
</Breakpoint>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>

2
examples/arm-cm/dpp_ek-tm4c123gxl/qk/armclang/dpp-qk.uvprojx
View File

@ -1597,7 +1597,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>Q_SPY,QK_ON_CONTEXT_SW,TARGET_IS_TM4C123_RB1</Define>
<Define>Q_SPY,QF_ON_CONTEXT_SW,TARGET_IS_TM4C123_RB1</Define>
<Undefine></Undefine>
<IncludePath>..\..;..\..\..\..\..\include;..\..\..\..\..\ports\arm-cm\qk\armclang;..\..\..\..\..\3rd_party\CMSIS\Include;..\..\..\..\..\3rd_party\ek-tm4c123gxl</IncludePath>
</VariousControls>

203
examples/arm-cm/dpp_ek-tm4c123gxl/qk/bsp.c
View File

@ -1,7 +1,7 @@
/*****************************************************************************
* Product: DPP example, EK-TM4C123GXL board, preemptive QK kernel
* Last updated for version 7.1.3
* Last updated on 2022-10-18
* Last updated for version 7.2.0
* Last updated on 2022-12-17
*
* Q u a n t u m L e a P s
* ------------------------
@ -94,8 +94,7 @@ void SysTick_Handler(void) {
uint32_t depressed;
uint32_t previous;
} buttons = { 0U, 0U };
uint32_t current = ~GPIOF->DATA_Bits[BTN_SW1 | BTN_SW2]; /* read SW1&SW2 */
uint32_t current = ~GPIOF_AHB->DATA_Bits[BTN_SW1 | BTN_SW2]; /* read SW1&SW2 */
uint32_t tmp = buttons.depressed; /* save debounced depressed buttons */
buttons.depressed |= (buttons.previous & current); /* set depressed */
buttons.depressed &= (buttons.previous | current); /* clear released */
@ -111,6 +110,11 @@ void SysTick_Handler(void) {
QACTIVE_PUBLISH(&serveEvt, &l_SysTick_Handler);
}
}
if ((tmp & BTN_SW2) != 0U) { /* debounced SW2 state changed? */
/* TEST: of MPU */
uint32_t volatile foo = *(uint32_t volatile *)0x204U; // legal
*(uint32_t volatile *)0x204U = foo; // illegal
}
QK_ISR_EXIT(); /* inform QK about exiting an ISR */
}
@ -145,54 +149,155 @@ void UART0_IRQHandler(void) {
void UART0_IRQHandler(void) {}
#endif
/* BSP functions ===========================================================*/
/* MPU setup for TM4C123GXL MCU */
static void TM4C123GXL_MPU_setup(void) {
/* The following MPU configuration contains the general TM4C memory map.
*
* Please note that the actual TM4C MCUs provide much less Flash and SRAM
* than the maximums configured here. This means that actual MCUs have
* unmapped memory regions (e.g., beyond the actual SRAM). Attempts to
* access these regions causes the HardFault exception, which is the
* desired behavior.
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #1: SRAM: base=0x2000'0000, size=512M=2^(28+1) */
0x20000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 1U), /* region #1 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
/* region #3: (not configured) */
{ MPU_RBAR_VALID_Msk | (MPU_RBAR_REGION_Msk & 2U), 0U },
{ /* region #3: Peripherals: base=0x4000'0000, size=512M=2^(28+1) */
0x40000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 3U), /* region #3 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #4: Priv. Periph: base=0xE000'0000, size=512M=2^(28+1) */
0xE0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 4U), /* region #4 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #5: Ext RAM: base=0x6000'0000, size=1G=2^(29+1) */
0x60000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 5U), /* region #5 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #6: Ext Dev: base=0xA000'0000, size=1G=2^(29+1) */
0xA0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 6U), /* region #6 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=256B */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(7U << MPU_RASR_SIZE_Pos) /* 2^(7+1)=256B region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_ENABLE_Msk; /* enable the MPU */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
TM4C123GXL_MPU_setup();
/* NOTE: SystemInit() already called from the startup code
* but SystemCoreClock needs to be updated
*/
SystemCoreClockUpdate();
/* NOTE: The VFP (hardware Floating Point) unit
* by choosing one of the options...
*/
#if 1
/* OPTION 1:
* Use the automatic FPU state preservation and the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in more than one task or
* in any ISRs. This setting is the safest and recommended, but requires
* extra stack space and CPU cycles.
*/
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
#else
/* OPTION 2:
* Do NOT to use the automatic FPU state preservation and
* do NOT to use the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in ONE task only and not
* in any ISR. This setting is very efficient, but if more than one task
* (or ISR) start using the FPU, this can lead to corruption of the
* FPU registers. This option should be used with CAUTION.
*/
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
#endif
/* NOTE: The VFP (hardware Floating Point) unit is configured by QK */
/* enable clock for to the peripherals used by this application... */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */
__ISB();
__DSB();
/* configure the LEDs and push buttons */
GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE); /* set as output */
GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); /* digital enable */
GPIOF->DATA_Bits[LED_RED] = 0U; /* turn the LED off */
GPIOF->DATA_Bits[LED_GREEN] = 0U; /* turn the LED off */
GPIOF->DATA_Bits[LED_BLUE] = 0U; /* turn the LED off */
/* configure LEDs (digital output) */
GPIOF_AHB->DIR |= (LED_RED | LED_BLUE | LED_GREEN);
GPIOF_AHB->DEN |= (LED_RED | LED_BLUE | LED_GREEN);
GPIOF_AHB->DATA_Bits[LED_RED | LED_BLUE | LED_GREEN] = 0U;
/* configure the User Switches */
GPIOF->DIR &= ~(BTN_SW1 | BTN_SW2); /* set direction: input */
ROM_GPIOPadConfigSet(GPIOF_BASE, (BTN_SW1 | BTN_SW2),
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
/* configure switches... */
/* unlock access to the SW2 pin because it is PROTECTED */
GPIOF_AHB->LOCK = 0x4C4F434BU; /* unlock GPIOCR register for SW2 */
/* commit the write (cast const away) */
*(uint32_t volatile *)&GPIOF_AHB->CR = 0x01U;
GPIOF_AHB->DIR &= ~(BTN_SW1 | BTN_SW2); /* input */
GPIOF_AHB->DEN |= (BTN_SW1 | BTN_SW2); /* digital enable */
GPIOF_AHB->PUR |= (BTN_SW1 | BTN_SW2); /* pull-up resistor enable */
*(uint32_t volatile *)&GPIOF_AHB->CR = 0x00U;
GPIOF_AHB->LOCK = 0x0; /* lock GPIOCR register for SW2 */
/* seed the random number generator */
BSP_randomSeed(1234U);
@ -213,7 +318,7 @@ void BSP_init(void) {
}
/*..........................................................................*/
void BSP_displayPhilStat(uint8_t n, char const *stat) {
GPIOF->DATA_Bits[LED_GREEN] = ((stat[0] == 'e') ? LED_GREEN : 0U);
GPIOF_AHB->DATA_Bits[LED_GREEN] = ((stat[0] == 'e') ? LED_GREEN : 0U);
QS_BEGIN_ID(PHILO_STAT, AO_Philo[n]->prio) /* app-specific record */
QS_U8(1, n); /* Philosopher number */
@ -222,7 +327,7 @@ void BSP_displayPhilStat(uint8_t n, char const *stat) {
}
/*..........................................................................*/
void BSP_displayPaused(uint8_t paused) {
GPIOF->DATA_Bits[LED_BLUE] = ((paused != 0U) ? LED_BLUE : 0U);
GPIOF_AHB->DATA_Bits[LED_BLUE] = ((paused != 0U) ? LED_BLUE : 0U);
QS_BEGIN_ID(PAUSED_STAT, 0U) /* app-specific record */
QS_U8(1, paused); /* Paused status */
@ -283,21 +388,21 @@ void QF_onStartup(void) {
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QK_ON_CONTEXT_SW
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QK_onContextSw(QActive *prev, QActive *next) {
void QF_onContextSw(QActive *prev, QActive *next) {
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U) /* no critical section! */
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QK_ON_CONTEXT_SW */
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QK_onIdle(void) {
/* toggle the User LED on and then off, see NOTE2 */
QF_INT_DISABLE();
GPIOF->DATA_Bits[LED_BLUE] = 0xFFU; /* turn the Blue LED on */
GPIOF->DATA_Bits[LED_BLUE] = 0U; /* turn the Blue LED off */
GPIOF_AHB->DATA_Bits[LED_BLUE] = 0xFFU; /* turn the Blue LED on */
GPIOF_AHB->DATA_Bits[LED_BLUE] = 0U; /* turn the Blue LED off */
QF_INT_ENABLE();
#ifdef Q_SPY
@ -335,7 +440,7 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
#ifndef NDEBUG
/* light up all LEDs */
GPIOF->DATA_Bits[LED_GREEN | LED_RED | LED_BLUE] = 0xFFU;
GPIOF_AHB->DATA_Bits[LED_GREEN | LED_RED | LED_BLUE] = 0xFFU;
/* for debugging, hang on in an endless loop... */
for (;;) {
}

25
examples/arm-cm/dpp_ek-tm4c123gxl/qk/gnu_with-stack-prot/bsp_stack-prot.c
View File

@ -162,30 +162,7 @@ void BSP_init(void) {
*/
SystemCoreClockUpdate();
/* configure the FPU usage by choosing one of the options... */
#if 1
/* OPTION 1:
* Use the automatic FPU state preservation and the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in more than one task or
* in any ISRs. This setting is the safest and recommended, but requires
* extra stack space and CPU cycles.
*/
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
#else
/* OPTION 2:
* Do NOT to use the automatic FPU state preservation and
* do NOT to use the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in ONE task only and not
* in any ISR. This setting is very efficient, but if more than one task
* (or ISR) start using the FPU, this can lead to corruption of the
* FPU registers. This option should be used with CAUTION.
*/
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
#endif
/* NOTE The VFP (hardware Floating Point) unit is configured by QK-port */
/* enable clock for to the peripherals used by this application... */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */

203
examples/arm-cm/dpp_ek-tm4c123gxl/qv/bsp.c
View File

@ -1,7 +1,7 @@
/*****************************************************************************
* Product: DPP example, EK-TM4C123GXL board, cooperative QV kernel
* Last updated for version 7.1.3
* Last updated on 2022-10-18
* Last updated for version 7.2.0
* Last updated on 2022-12-17
*
* Q u a n t u m L e a P s
* ------------------------
@ -92,8 +92,7 @@ void SysTick_Handler(void) {
uint32_t depressed;
uint32_t previous;
} buttons = { 0U, 0U };
uint32_t current = ~GPIOF->DATA_Bits[BTN_SW1 | BTN_SW2]; /* read SW1 & SW2 */
uint32_t current = ~GPIOF_AHB->DATA_Bits[BTN_SW1 | BTN_SW2]; /* read SW1&SW2 */
uint32_t tmp = buttons.depressed; /* save debounced depressed buttons */
buttons.depressed |= (buttons.previous & current); /* set depressed */
buttons.depressed &= (buttons.previous | current); /* clear released */
@ -109,6 +108,11 @@ void SysTick_Handler(void) {
QACTIVE_PUBLISH(&serveEvt, &l_SysTick_Handler);
}
}
if ((tmp & BTN_SW2) != 0U) { /* debounced SW2 state changed? */
/* TEST: of MPU */
uint32_t volatile foo = *(uint32_t volatile *)0x204U; // legal
*(uint32_t volatile *)0x204U = foo; // illegal
}
}
/*..........................................................................*/
void GPIOPortA_IRQHandler(void) {
@ -137,53 +141,157 @@ void UART0_IRQHandler(void) {
void UART0_IRQHandler(void) {}
#endif
/* BSP functions ===========================================================*/
/* MPU setup for TM4C123GXL MCU */
static void TM4C123GXL_MPU_setup(void) {
/* The following MPU configuration contains the general TM4C memory map.
*
* Please note that the actual TM4C MCUs provide much less Flash and SRAM
* than the maximums configured here. This means that actual MCUs have
* unmapped memory regions (e.g., beyond the actual SRAM). Attempts to
* access these regions causes the HardFault exception, which is the
* desired behavior.
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #1: SRAM: base=0x2000'0000, size=512M=2^(28+1) */
0x20000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 1U), /* region #1 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
/* region #3: (not configured) */
{ MPU_RBAR_VALID_Msk | (MPU_RBAR_REGION_Msk & 2U), 0U },
{ /* region #3: Peripherals: base=0x4000'0000, size=512M=2^(28+1) */
0x40000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 3U), /* region #3 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #4: Priv. Periph: base=0xE000'0000, size=512M=2^(28+1) */
0xE0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 4U), /* region #4 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #5: Ext RAM: base=0x6000'0000, size=1G=2^(29+1) */
0x60000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 5U), /* region #5 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #6: Ext Dev: base=0xA000'0000, size=1G=2^(29+1) */
0xA0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 6U), /* region #6 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=256B */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(7U << MPU_RASR_SIZE_Pos) /* 2^(7+1)=256B region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_ENABLE_Msk; /* enable the MPU */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
TM4C123GXL_MPU_setup();
/* NOTE: SystemInit() already called from the startup code
* but SystemCoreClock needs to be updated
*/
SystemCoreClockUpdate();
/* configure the FPU usage by choosing one of the options... */
#if 1
/* OPTION 1:
* Use the automatic FPU state preservation and the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in more than one task or
* in any ISRs. This setting is the safest and recommended, but requires
* extra stack space and CPU cycles.
*/
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
#else
/* OPTION 2:
* Do NOT to use the automatic FPU state preservation and
* do NOT to use the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in ONE task only and not
* in any ISR. This setting is very efficient, but if more than one task
* (or ISR) start using the FPU, this can lead to corruption of the
* FPU registers. This option should be used with CAUTION.
*/
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
#endif
/* NOTE: The VFP (hardware Floating Point) unit is configured by QV */
/* enable clock for to the peripherals used by this application... */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */
__ISB();
__DSB();
/* configure the LEDs and push buttons */
GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE); /* set as output */
GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); /* digital enable */
GPIOF->DATA_Bits[LED_RED] = 0U; /* turn the LED off */
GPIOF->DATA_Bits[LED_GREEN] = 0U; /* turn the LED off */
GPIOF->DATA_Bits[LED_BLUE] = 0U; /* turn the LED off */
/* configure LEDs (digital output) */
GPIOF_AHB->DIR |= (LED_RED | LED_BLUE | LED_GREEN);
GPIOF_AHB->DEN |= (LED_RED | LED_BLUE | LED_GREEN);
GPIOF_AHB->DATA_Bits[LED_RED | LED_BLUE | LED_GREEN] = 0U;
/* configure the User Switches */
GPIOF->DIR &= ~(BTN_SW1 | BTN_SW2); /* set direction: input */
ROM_GPIOPadConfigSet(GPIOF_BASE, (BTN_SW1 | BTN_SW2),
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
/* configure switches... */
/* unlock access to the SW2 pin because it is PROTECTED */
GPIOF_AHB->LOCK = 0x4C4F434BU; /* unlock GPIOCR register for SW2 */
/* commit the write (cast const away) */
*(uint32_t volatile *)&GPIOF_AHB->CR = 0x01U;
GPIOF_AHB->DIR &= ~(BTN_SW1 | BTN_SW2); /* input */
GPIOF_AHB->DEN |= (BTN_SW1 | BTN_SW2); /* digital enable */
GPIOF_AHB->PUR |= (BTN_SW1 | BTN_SW2); /* pull-up resistor enable */
*(uint32_t volatile *)&GPIOF_AHB->CR = 0x00U;
GPIOF_AHB->LOCK = 0x0; /* lock GPIOCR register for SW2 */
/* seed the random number generator */
BSP_randomSeed(1234U);
/* initialize the QS software tracing... */
@ -202,7 +310,7 @@ void BSP_init(void) {
}
/*..........................................................................*/
void BSP_displayPhilStat(uint8_t n, char const *stat) {
GPIOF->DATA_Bits[LED_GREEN] = ((stat[0] == 'e') ? LED_GREEN : 0U);
GPIOF_AHB->DATA_Bits[LED_GREEN] = ((stat[0] == 'e') ? LED_GREEN : 0U);
QS_BEGIN_ID(PHILO_STAT, AO_Philo[n]->prio) /* app-specific record */
QS_U8(1, n); /* Philosopher number */
@ -211,7 +319,7 @@ void BSP_displayPhilStat(uint8_t n, char const *stat) {
}
/*..........................................................................*/
void BSP_displayPaused(uint8_t paused) {
GPIOF->DATA_Bits[LED_BLUE] = ((paused != 0U) ? LED_BLUE : 0U);
GPIOF_AHB->DATA_Bits[LED_BLUE] = ((paused != 0U) ? LED_BLUE : 0U);
QS_BEGIN_ID(PAUSED_STAT, 0U) /* app-specific record */
QS_U8(1, paused); /* Paused status */
@ -271,8 +379,8 @@ void QF_onCleanup(void) {
/*..........................................................................*/
void QV_onIdle(void) { /* called with interrupts disabled, see NOTE2 */
/* toggle the User LED on and then off, see NOTE3 */
GPIOF->DATA_Bits[LED_BLUE] = LED_BLUE; /* turn the Blue LED on */
GPIOF->DATA_Bits[LED_BLUE] = 0U; /* turn the Blue LED off */
GPIOF_AHB->DATA_Bits[LED_BLUE] = 0xFFU; /* turn the Blue LED on */
GPIOF_AHB->DATA_Bits[LED_BLUE] = 0U; /* turn the Blue LED off */
#ifdef Q_SPY
QF_INT_ENABLE();
@ -312,7 +420,7 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
#ifndef NDEBUG
/* light up all LEDs */
GPIOF->DATA_Bits[LED_GREEN | LED_RED | LED_BLUE] = 0xFFU;
GPIOF_AHB->DATA_Bits[LED_GREEN | LED_RED | LED_BLUE] = 0xFFU;
/* for debugging, hang on in an endless loop... */
for (;;) {
}
@ -327,9 +435,8 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
uint8_t QS_onStartup(void const *arg) {
Q_UNUSED_PAR(arg);
static uint8_t qsTxBuf[2*1024]; /* buffer for QS transmit channel */
static uint8_t qsRxBuf[100]; /* buffer for QS receive channel */
uint32_t tmp;
static uint8_t qsTxBuf[2*1024]; /* buffer for QS-TX channel */
static uint8_t qsRxBuf[100]; /* buffer for QS-RX channel */
QS_initBuf (qsTxBuf, sizeof(qsTxBuf));
QS_rxInitBuf(qsRxBuf, sizeof(qsRxBuf));
@ -339,7 +446,7 @@ uint8_t QS_onStartup(void const *arg) {
SYSCTL->RCGCGPIO |= (1U << 0); /* enable Run mode for GPIOA */
/* configure UART0 pins for UART operation */
tmp = (1U << 0) | (1U << 1);
uint32_t tmp = (1U << 0) | (1U << 1);
GPIOA->DIR &= ~tmp;
GPIOA->SLR &= ~tmp;
GPIOA->ODR &= ~tmp;

36
examples/arm-cm/dpp_ek-tm4c123gxl/qxk/armclang/dpp-qxk.uvoptx
View File

@ -120,7 +120,6 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÈ`² vÛ\!¼ìV</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -148,7 +147,40 @@
<Name>-U0E2006F4 -O4623 -S4 -FO61</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>333</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>1210</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\..\..\..\..\3rd_party\ek-tm4c123gxl\arm\startup_TM4C123GH6PM.s</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qxk\../../../../../3rd_party/ek-tm4c123gxl/arm/startup_TM4C123GH6PM.s\333</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>321</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>1204</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\..\..\..\..\3rd_party\ek-tm4c123gxl\arm\startup_TM4C123GH6PM.s</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qxk\../../../../../3rd_party/ek-tm4c123gxl/arm/startup_TM4C123GH6PM.s\321</Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>

4
examples/arm-cm/dpp_ek-tm4c123gxl/qxk/armclang/dpp-qxk.uvprojx
View File

@ -332,7 +332,7 @@
<v6LangP>3</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<v6Lto>0</v6Lto>
<v6Lto>1</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
@ -1637,7 +1637,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>Q_SPY,QXK_ON_CONTEXT_SW,TARGET_IS_TM4C123_RB1</Define>
<Define>Q_SPY,QF_ON_CONTEXT_SW,TARGET_IS_TM4C123_RB1</Define>
<Undefine></Undefine>
<IncludePath>..\..;..\..\..\..\..\include;..\..\..\..\..\ports\arm-cm\qxk\armclang;..\..\..\..\..\3rd_party\CMSIS\Include;..\..\..\..\..\3rd_party\ek-tm4c123gxl</IncludePath>
</VariousControls>

225
examples/arm-cm/dpp_ek-tm4c123gxl/qxk/bsp.c
View File

@ -1,7 +1,7 @@
/*****************************************************************************
* Product: DPP example, EK-TM4C123GXL board, dual-mode QXK kernel
* Last updated for version 7.1.3
* Last updated on 2022-10-18
* Last updated for version 7.2.0
* Last updated on 2022-12-17
*
* Q u a n t u m L e a P s
* ------------------------
@ -94,8 +94,7 @@ void SysTick_Handler(void) {
uint32_t depressed;
uint32_t previous;
} buttons = { 0U, 0U };
uint32_t current = ~GPIOF->DATA_Bits[BTN_SW1 | BTN_SW2]; /* read SW1 & SW2 */
uint32_t current = ~GPIOF_AHB->DATA_Bits[BTN_SW1 | BTN_SW2]; /* read SW1&SW2 */
uint32_t tmp = buttons.depressed; /* save debounced depressed buttons */
buttons.depressed |= (buttons.previous & current); /* set depressed */
buttons.depressed &= (buttons.previous | current); /* clear released */
@ -111,6 +110,11 @@ void SysTick_Handler(void) {
QACTIVE_PUBLISH(&serveEvt, &l_SysTick_Handler);
}
}
if ((tmp & BTN_SW2) != 0U) { /* debounced SW2 state changed? */
/* TEST: of MPU */
uint32_t volatile foo = *(uint32_t volatile *)0x204U; // legal
*(uint32_t volatile *)0x204U = foo; // illegal
}
QXK_ISR_EXIT(); /* inform QXK about exiting an ISR */
}
@ -145,55 +149,157 @@ void UART0_IRQHandler(void) {
void UART0_IRQHandler(void) {}
#endif
/* BSP functions ===========================================================*/
/* MPU setup for TM4C123GXL MCU */
static void TM4C123GXL_MPU_setup(void) {
/* The following MPU configuration contains the general TM4C memory map.
*
* Please note that the actual TM4C MCUs provide much less Flash and SRAM
* than the maximums configured here. This means that actual MCUs have
* unmapped memory regions (e.g., beyond the actual SRAM). Attempts to
* access these regions causes the HardFault exception, which is the
* desired behavior.
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #1: SRAM: base=0x2000'0000, size=512M=2^(28+1) */
0x20000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 1U), /* region #1 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
/* region #3: (not configured) */
{ MPU_RBAR_VALID_Msk | (MPU_RBAR_REGION_Msk & 2U), 0U },
{ /* region #3: Peripherals: base=0x4000'0000, size=512M=2^(28+1) */
0x40000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 3U), /* region #3 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #4: Priv. Periph: base=0xE000'0000, size=512M=2^(28+1) */
0xE0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 4U), /* region #4 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #5: Ext RAM: base=0x6000'0000, size=1G=2^(29+1) */
0x60000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 5U), /* region #5 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #6: Ext Dev: base=0xA000'0000, size=1G=2^(29+1) */
0xA0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 6U), /* region #6 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=256B */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(7U << MPU_RASR_SIZE_Pos) /* 2^(7+1)=256B region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_ENABLE_Msk; /* enable the MPU */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
TM4C123GXL_MPU_setup();
/* NOTE: SystemInit() already called from the startup code
* but SystemCoreClock needs to be updated
*/
SystemCoreClockUpdate();
/* NOTE: The VFP (hardware Floating Point) unit
* by choosing one of the options...
*/
#if 1
/* OPTION 1:
* Use the automatic FPU state preservation and the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in more than one task or
* in any ISRs. This setting is the safest and recommended, but requires
* extra stack space and CPU cycles.
*/
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
#else
/* OPTION 2:
* Do NOT to use the automatic FPU state preservation and
* do NOT to use the FPU lazy stacking.
*
* NOTE:
* Use the following setting when FPU is used in ONE task only and not
* in any ISR. This setting is very efficient, but if more than one task
* (or ISR) start using the FPU, this can lead to corruption of the
* FPU registers. This option should be used with CAUTION.
*/
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
#endif
/* NOTE: The VFP (hardware Floating Point) unit is configured by QXK */
/* enable clock for to the peripherals used by this application... */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */
__ISB();
__DSB();
/* configure the LEDs and push buttons */
GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE); /* set as output */
GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); /* digital enable */
GPIOF->DATA_Bits[LED_RED] = 0U; /* turn the LED off */
GPIOF->DATA_Bits[LED_GREEN] = 0U; /* turn the LED off */
GPIOF->DATA_Bits[LED_BLUE] = 0U; /* turn the LED off */
/* configure LEDs (digital output) */
GPIOF_AHB->DIR |= (LED_RED | LED_BLUE | LED_GREEN);
GPIOF_AHB->DEN |= (LED_RED | LED_BLUE | LED_GREEN);
GPIOF_AHB->DATA_Bits[LED_RED | LED_BLUE | LED_GREEN] = 0U;
/* configure the User Switches */
GPIOF->DIR &= ~(BTN_SW1 | BTN_SW2); /* set direction: input */
ROM_GPIOPadConfigSet(GPIOF_BASE, (BTN_SW1 | BTN_SW2),
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
/* configure switches... */
/* unlock access to the SW2 pin because it is PROTECTED */
GPIOF_AHB->LOCK = 0x4C4F434BU; /* unlock GPIOCR register for SW2 */
/* commit the write (cast const away) */
*(uint32_t volatile *)&GPIOF_AHB->CR = 0x01U;
GPIOF_AHB->DIR &= ~(BTN_SW1 | BTN_SW2); /* input */
GPIOF_AHB->DEN |= (BTN_SW1 | BTN_SW2); /* digital enable */
GPIOF_AHB->PUR |= (BTN_SW1 | BTN_SW2); /* pull-up resistor enable */
*(uint32_t volatile *)&GPIOF_AHB->CR = 0x00U;
GPIOF_AHB->LOCK = 0x0; /* lock GPIOCR register for SW2 */
/* seed the random number generator */
BSP_randomSeed(1234U);
/* initialize the QS software tracing... */
@ -212,7 +318,7 @@ void BSP_init(void) {
}
/*..........................................................................*/
void BSP_displayPhilStat(uint8_t n, char const *stat) {
GPIOF->DATA_Bits[LED_GREEN] = ((stat[0] == 'e') ? LED_GREEN : 0U);
GPIOF_AHB->DATA_Bits[LED_GREEN] = ((stat[0] == 'e') ? LED_GREEN : 0U);
QS_BEGIN_ID(PHILO_STAT, AO_Philo[n]->prio) /* app-specific record */
QS_U8(1, n); /* Philosopher number */
@ -221,15 +327,7 @@ void BSP_displayPhilStat(uint8_t n, char const *stat) {
}
/*..........................................................................*/
void BSP_displayPaused(uint8_t paused) {
GPIOF->DATA_Bits[LED_BLUE] = ((paused != 0U) ? LED_BLUE : 0U);
if (paused != 0U) {
/* for testing the extended threads... */
QXThread_delayCancel(XT_Test2); /* make sure Test2 is not delayed */
static QEvt const pauseEvt = { PAUSE_SIG, 0U, 0U};
QACTIVE_POST_X(&XT_Test2->super, &pauseEvt, 1U, (void *)0);
}
GPIOF_AHB->DATA_Bits[LED_BLUE] = ((paused != 0U) ? LED_BLUE : 0U);
QS_BEGIN_ID(PAUSED_STAT, 0U) /* app-specific record */
QS_U8(1, paused); /* Paused status */
@ -259,11 +357,11 @@ void BSP_randomSeed(uint32_t seed) {
}
/*..........................................................................*/
void BSP_ledOn(void) {
GPIOF->DATA_Bits[LED_RED] = 0xFFU;
GPIOF_AHB->DATA_Bits[LED_RED] = 0xFFU;
}
/*..........................................................................*/
void BSP_ledOff(void) {
GPIOF->DATA_Bits[LED_RED] = 0x00U;
GPIOF_AHB->DATA_Bits[LED_RED] = 0x00U;
}
/*..........................................................................*/
void BSP_terminate(int16_t result) {
@ -300,9 +398,9 @@ void QF_onStartup(void) {
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QXK_ON_CONTEXT_SW
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QXK_onContextSw(QActive *prev, QActive *next) {
void QF_onContextSw(QActive *prev, QActive *next) {
if (next != (QActive *)0) {
//_impure_ptr = next->thread; /* switch to next TLS */
}
@ -311,13 +409,13 @@ void QXK_onContextSw(QActive *prev, QActive *next) {
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QXK_ON_CONTEXT_SW */
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QXK_onIdle(void) {
/* toggle the User LED on and then off, see NOTE2 */
QF_INT_DISABLE();
GPIOF->DATA_Bits[LED_BLUE] = 0xFFU; /* turn the Blue LED on */
GPIOF->DATA_Bits[LED_BLUE] = 0U; /* turn the Blue LED off */
GPIOF_AHB->DATA_Bits[LED_BLUE] = 0xFFU; /* turn the Blue LED on */
GPIOF_AHB->DATA_Bits[LED_BLUE] = 0U; /* turn the Blue LED off */
QF_INT_ENABLE();
/* Some flating point code is to exercise the VFP... */
@ -342,7 +440,7 @@ void QXK_onIdle(void) {
#elif defined NDEBUG
/* Put the CPU and peripherals to the low-power mode.
* you might need to customize the clock management for your application,
* see the datasheet for your particular Cortex-M3 MCU.
* see the datasheet for your particular Cortex-M MCU.
*/
__WFI(); /* Wait-For-Interrupt */
#endif
@ -359,7 +457,7 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
#ifndef NDEBUG
/* light up all LEDs */
GPIOF->DATA_Bits[LED_GREEN | LED_RED | LED_BLUE] = 0xFFU;
GPIOF_AHB->DATA_Bits[LED_GREEN | LED_RED | LED_BLUE] = 0xFFU;
/* for debugging, hang on in an endless loop... */
for (;;) {
}
@ -374,9 +472,8 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
uint8_t QS_onStartup(void const *arg) {
Q_UNUSED_PAR(arg);
static uint8_t qsTxBuf[2*1024]; /* buffer for QS transmit channel */
static uint8_t qsRxBuf[100]; /* buffer for QS receive channel */
uint32_t tmp;
static uint8_t qsTxBuf[2*1024]; /* buffer for QS-TX channel */
static uint8_t qsRxBuf[100]; /* buffer for QS-RX channel */
QS_initBuf (qsTxBuf, sizeof(qsTxBuf));
QS_rxInitBuf(qsRxBuf, sizeof(qsRxBuf));
@ -386,7 +483,7 @@ uint8_t QS_onStartup(void const *arg) {
SYSCTL->RCGCGPIO |= (1U << 0); /* enable Run mode for GPIOA */
/* configure UART0 pins for UART operation */
tmp = (1U << 0) | (1U << 1);
uint32_t tmp = (1U << 0) | (1U << 1);
GPIOA->DIR &= ~tmp;
GPIOA->SLR &= ~tmp;
GPIOA->ODR &= ~tmp;

320
examples/arm-cm/dpp_ek-tm4c123gxl/qxk/iar/dpp-qxk.ewp
View File

@ -11,9 +11,13 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>31</version>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>BrowseInfoPath</name>
<state>Debug\BrowseInfo</state>
</option>
<option>
<name>ExePath</name>
<state>dbg</state>
@ -66,15 +70,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>8.40.2.22864</state>
</option>
<option>
<name>GeneralEnableMisra</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraVerbose</name>
<state>0</state>
<state>9.10.2.39304</state>
</option>
<option>
<name>OGChipSelectEditMenu</name>
@ -96,27 +92,13 @@
<name>GenStdoutInterface</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>GeneralMisraVer</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>27</version>
<version>30</version>
<state>39</state>
</option>
<option>
@ -133,7 +115,7 @@
</option>
<option>
<name>CoreVariant</name>
<version>27</version>
<version>30</version>
<state>39</state>
</option>
<option>
@ -156,7 +138,7 @@
</option>
<option>
<name>GFPUCoreSlave2</name>
<version>27</version>
<version>30</version>
<state>39</state>
</option>
<option>
@ -209,13 +191,21 @@
<version>0</version>
<state>0</state>
</option>
<option>
<name>OGAarch64Abi</name>
<state>0</state>
</option>
<option>
<name>OG_32_64Device</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>ICCARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>35</version>
<version>37</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -343,10 +333,6 @@
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CompilerMisraOverride</name>
<state>0</state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..</state>
@ -381,16 +367,6 @@
<name>CCOptLevelSlave</name>
<state>0</state>
</option>
<option>
<name>CompilerMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>CompilerMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>CCPosIndRopi</name>
<state>0</state>
@ -472,13 +448,17 @@
<name>OICompilerExtraOption</name>
<state>1</state>
</option>
<option>
<name>CCStackProtection</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>AARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>10</version>
<version>11</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -634,6 +614,10 @@
<name>AsmNoLiteralPool</name>
<state>0</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
</data>
</settings>
<settings>
@ -673,13 +657,9 @@
<extensions></extensions>
<cmdline></cmdline>
<hasPrio>0</hasPrio>
<buildSequence>inputOutputBased</buildSequence>
</data>
</settings>
<settings>
<name>BICOMP</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
@ -692,17 +672,13 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>23</version>
<version>25</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>IlinkLibIOConfig</name>
<state>1</state>
</option>
<option>
<name>XLinkMisraHandler</name>
<state>0</state>
</option>
<option>
<name>IlinkInputFileSlave</name>
<state>0</state>
@ -1006,7 +982,7 @@
</option>
<option>
<name>IlinkTrustzoneImportLibraryOut</name>
<state>###Unitialized###</state>
<state>dpp-qxk_import_lib.o</state>
</option>
<option>
<name>OILinkExtraOption</name>
@ -1028,6 +1004,26 @@
<name>IlinkRawBinaryAlign2</name>
<state></state>
</option>
<option>
<name>IlinkLogCrtRoutineSelection</name>
<state>0</state>
</option>
<option>
<name>IlinkLogFragmentInfo</name>
<state>0</state>
</option>
<option>
<name>IlinkLogInlining</name>
<state>0</state>
</option>
<option>
<name>IlinkLogMerging</name>
<state>0</state>
</option>
<option>
<name>IlinkDemangle</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -1051,11 +1047,6 @@
</option>
</data>
</settings>
<settings>
<name>BILINK</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>Coder</name>
<archiveVersion>0</archiveVersion>
@ -1072,9 +1063,13 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>31</version>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>BrowseInfoPath</name>
<state>Release\BrowseInfo</state>
</option>
<option>
<name>ExePath</name>
<state>rel</state>
@ -1129,14 +1124,6 @@
<name>OGLastSavedByProductVersion</name>
<state>8.40.2.22864</state>
</option>
<option>
<name>GeneralEnableMisra</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraVerbose</name>
<state>0</state>
</option>
<option>
<name>OGChipSelectEditMenu</name>
<state>TM4C123GH6PM TexasInstruments TM4C123GH6PM</state>
@ -1157,27 +1144,13 @@
<name>GenStdoutInterface</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>GeneralMisraVer</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>27</version>
<version>30</version>
<state>39</state>
</option>
<option>
@ -1194,7 +1167,7 @@
</option>
<option>
<name>CoreVariant</name>
<version>27</version>
<version>30</version>
<state>39</state>
</option>
<option>
@ -1217,7 +1190,7 @@
</option>
<option>
<name>GFPUCoreSlave2</name>
<version>27</version>
<version>30</version>
<state>39</state>
</option>
<option>
@ -1270,13 +1243,21 @@
<version>0</version>
<state>0</state>
</option>
<option>
<name>OGAarch64Abi</name>
<state>0</state>
</option>
<option>
<name>OG_32_64Device</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>ICCARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>35</version>
<version>37</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -1404,10 +1385,6 @@
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CompilerMisraOverride</name>
<state>0</state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..</state>
@ -1442,16 +1419,6 @@
<name>CCOptLevelSlave</name>
<state>3</state>
</option>
<option>
<name>CompilerMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>CompilerMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>CCPosIndRopi</name>
<state>0</state>
@ -1533,13 +1500,17 @@
<name>OICompilerExtraOption</name>
<state>1</state>
</option>
<option>
<name>CCStackProtection</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>AARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>10</version>
<version>11</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -1695,6 +1666,10 @@
<name>AsmNoLiteralPool</name>
<state>0</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
</data>
</settings>
<settings>
@ -1734,13 +1709,9 @@
<extensions></extensions>
<cmdline></cmdline>
<hasPrio>0</hasPrio>
<buildSequence>inputOutputBased</buildSequence>
</data>
</settings>
<settings>
<name>BICOMP</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
@ -1753,17 +1724,13 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>23</version>
<version>25</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>IlinkLibIOConfig</name>
<state>1</state>
</option>
<option>
<name>XLinkMisraHandler</name>
<state>0</state>
</option>
<option>
<name>IlinkInputFileSlave</name>
<state>0</state>
@ -2089,6 +2056,26 @@
<name>IlinkRawBinaryAlign2</name>
<state></state>
</option>
<option>
<name>IlinkLogCrtRoutineSelection</name>
<state>0</state>
</option>
<option>
<name>IlinkLogFragmentInfo</name>
<state>0</state>
</option>
<option>
<name>IlinkLogInlining</name>
<state>0</state>
</option>
<option>
<name>IlinkLogMerging</name>
<state>0</state>
</option>
<option>
<name>IlinkDemangle</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -2112,11 +2099,6 @@
</option>
</data>
</settings>
<settings>
<name>BILINK</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>Coder</name>
<archiveVersion>0</archiveVersion>
@ -2133,9 +2115,13 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>31</version>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>BrowseInfoPath</name>
<state>Spy\BrowseInfo</state>
</option>
<option>
<name>ExePath</name>
<state>spy</state>
@ -2190,14 +2176,6 @@
<name>OGLastSavedByProductVersion</name>
<state>8.40.2.22864</state>
</option>
<option>
<name>GeneralEnableMisra</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraVerbose</name>
<state>0</state>
</option>
<option>
<name>OGChipSelectEditMenu</name>
<state>TM4C123GH6PM TexasInstruments TM4C123GH6PM</state>
@ -2218,27 +2196,13 @@
<name>GenStdoutInterface</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>GeneralMisraVer</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>27</version>
<version>30</version>
<state>39</state>
</option>
<option>
@ -2255,7 +2219,7 @@
</option>
<option>
<name>CoreVariant</name>
<version>27</version>
<version>30</version>
<state>39</state>
</option>
<option>
@ -2278,7 +2242,7 @@
</option>
<option>
<name>GFPUCoreSlave2</name>
<version>27</version>
<version>30</version>
<state>39</state>
</option>
<option>
@ -2331,13 +2295,21 @@
<version>0</version>
<state>0</state>
</option>
<option>
<name>OGAarch64Abi</name>
<state>0</state>
</option>
<option>
<name>OG_32_64Device</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>ICCARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>35</version>
<version>37</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -2465,10 +2437,6 @@
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CompilerMisraOverride</name>
<state>0</state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..</state>
@ -2503,16 +2471,6 @@
<name>CCOptLevelSlave</name>
<state>1</state>
</option>
<option>
<name>CompilerMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>CompilerMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>CCPosIndRopi</name>
<state>0</state>
@ -2594,13 +2552,17 @@
<name>OICompilerExtraOption</name>
<state>1</state>
</option>
<option>
<name>CCStackProtection</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>AARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>10</version>
<version>11</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -2756,6 +2718,10 @@
<name>AsmNoLiteralPool</name>
<state>0</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
</data>
</settings>
<settings>
@ -2795,13 +2761,9 @@
<extensions></extensions>
<cmdline></cmdline>
<hasPrio>0</hasPrio>
<buildSequence>inputOutputBased</buildSequence>
</data>
</settings>
<settings>
<name>BICOMP</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
@ -2814,17 +2776,13 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>23</version>
<version>25</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>IlinkLibIOConfig</name>
<state>1</state>
</option>
<option>
<name>XLinkMisraHandler</name>
<state>0</state>
</option>
<option>
<name>IlinkInputFileSlave</name>
<state>0</state>
@ -3150,6 +3108,26 @@
<name>IlinkRawBinaryAlign2</name>
<state></state>
</option>
<option>
<name>IlinkLogCrtRoutineSelection</name>
<state>0</state>
</option>
<option>
<name>IlinkLogFragmentInfo</name>
<state>0</state>
</option>
<option>
<name>IlinkLogInlining</name>
<state>0</state>
</option>
<option>
<name>IlinkLogMerging</name>
<state>0</state>
</option>
<option>
<name>IlinkDemangle</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -3173,11 +3151,6 @@
</option>
</data>
</settings>
<settings>
<name>BILINK</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>Coder</name>
<archiveVersion>0</archiveVersion>
@ -3185,7 +3158,6 @@
</settings>
</configuration>
<mfc>
<configuration>Debug</configuration>
<configuration>Release</configuration>
<configuration>Spy</configuration>
</mfc>

6
examples/arm-cm/dpp_ek-tm4c123gxl/table.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::table.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -64,8 +64,8 @@ static QState Table_paused(Table * const me, QEvt const * const e);
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

2
examples/arm-cm/dpp_mbed-lpc1768/dpp.h
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::dpp.h}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later

2
examples/arm-cm/dpp_mbed-lpc1768/dpp.qm
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<model version="5.2.2" links="1">
<model version="5.2.4" links="1">
<documentation>Dining Philosopher Problem example</documentation>
<!--${qpc}-->
<framework name="qpc"/>

6
examples/arm-cm/dpp_mbed-lpc1768/philo.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::philo.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -67,8 +67,8 @@ static Philo l_philo[N_PHILO]; /* storage for all Philos */
/* Global objects ----------------------------------------------------------*/
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

18
examples/arm-cm/dpp_mbed-lpc1768/qk/armclang/dpp-qk.uvoptx
View File

@ -10,7 +10,7 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
@ -215,6 +215,13 @@
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>1</EnableFlashSeq>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
@ -583,6 +590,13 @@
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>1</EnableFlashSeq>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
@ -703,7 +717,7 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\.arm\startup-lpc1768\armclang\startup_LPC17xx.s</PathWithFileName>
<PathWithFileName>..\..\..\..\..\3rd_party\mbed-lpc1768\arm\startup_LPC17xx.s</PathWithFileName>
<FilenameWithoutPath>startup_LPC17xx.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>

23
examples/arm-cm/dpp_mbed-lpc1768/qk/armclang/dpp-qk.uvprojx
View File

@ -10,13 +10,13 @@
<TargetName>dpp-dbg</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6130001::V6.13.1::.\ARMCLANG</pCCUsed>
<pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>LPC1768</Device>
<Vendor>NXP</Vendor>
<PackID>Keil.LPC1700_DFP.2.2.0</PackID>
<PackID>Keil.LPC1700_DFP.2.7.1</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IRAM(0x10000000,0x8000) IRAM2(0x2007C000,0x8000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -185,6 +185,7 @@
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -351,7 +352,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>1</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define>Stack_Size=2048 Heap_Size=16</Define>
@ -610,7 +611,7 @@
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<ClangAsOpt>0</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -655,7 +656,7 @@
<TargetCommonOption>
<Device>LPC1768</Device>
<Vendor>NXP</Vendor>
<PackID>Keil.LPC1700_DFP.2.2.0</PackID>
<PackID>Keil.LPC1700_DFP.2.7.1</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IRAM(0x10000000,0x8000) IRAM2(0x2007C000,0x8000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -824,6 +825,7 @@
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -990,7 +992,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>1</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define>Stack_Size=2048 Heap_Size=16</Define>
@ -1249,7 +1251,7 @@
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<ClangAsOpt>0</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -1288,13 +1290,13 @@
<TargetName>dpp-spy</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6130001::V6.13.1::.\ARMCLANG</pCCUsed>
<pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>LPC1768</Device>
<Vendor>NXP</Vendor>
<PackID>Keil.LPC1700_DFP.2.2.0</PackID>
<PackID>Keil.LPC1700_DFP.2.7.1</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IRAM(0x10000000,0x8000) IRAM2(0x2007C000,0x8000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -1463,6 +1465,7 @@
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -1629,7 +1632,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>1</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define>Stack_Size=2048 Heap_Size=16</Define>

16
examples/arm-cm/dpp_mbed-lpc1768/qk/bsp.c
View File

@ -132,6 +132,22 @@ void EINT0_IRQHandler(void) {
/* BSP functions ===========================================================*/
void BSP_init(void) {
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Configure the MPU to prevent NULL-pointer dereferencing ... */
MPU->RBAR = 0x0U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U); /* region 7 */
MPU->RASR = (7U << MPU_RASR_SIZE_Pos) /* 2**(7+1) region */
| (0x0U << MPU_RASR_AP_Pos) /* no access */
| MPU_RASR_ENABLE_Msk; /* region enable */
MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk /* enable background region */
| MPU_CTRL_ENABLE_Msk; /* enable the MPU */
__ISB();
__DSB();
/* NOTE: SystemInit() has been already called from the startup code
* but SystemCoreClock needs to be updated
*/

9034
examples/arm-cm/dpp_mbed-lpc1768/qk/iar/dpp-qk.ewd
View File

File diff suppressed because it is too large Load Diff

6264
examples/arm-cm/dpp_mbed-lpc1768/qk/iar/dpp-qk.ewp
View File

File diff suppressed because it is too large Load Diff

6
examples/arm-cm/dpp_mbed-lpc1768/table.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::table.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -65,8 +65,8 @@ static Table l_table; /* the single instance of the Table active object */
/* Global-scope objects ----------------------------------------------------*/
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

2
examples/arm-cm/dpp_nucleo-h743zi/dpp.h
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::dpp.h}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later

2
examples/arm-cm/dpp_nucleo-h743zi/dpp.qm
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<model version="5.2.2" links="1">
<model version="5.2.4" links="1">
<documentation>Dining Philosopher Problem example</documentation>
<!--${qpc}-->
<framework name="qpc"/>

6
examples/arm-cm/dpp_nucleo-h743zi/philo.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::philo.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -66,8 +66,8 @@ static QState Philo_eating(Philo * const me, QEvt const * const e);
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

33
examples/arm-cm/dpp_nucleo-h743zi/qk/armclang/dpp-qk.uvoptx
View File

@ -75,7 +75,7 @@
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
<IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>18</CpuCode>
<DebugOpt>
@ -140,7 +140,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
<Name>(1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=3268,1338,3745,1653,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -148,12 +148,29 @@
<Name></Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>68</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134227432</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\main.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qk\../main.c\68</Expression>
</Bp>
</Breakpoint>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<SubType>2</SubType>
<ItemText>0x20000200</ItemText>
<ItemText>0xE000ED08</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>
@ -299,7 +316,7 @@
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<nTsel>6</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -467,7 +484,7 @@
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>0</IsCurrentTarget>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>18</CpuCode>
<DebugOpt>
@ -517,7 +534,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key>
<Name>-U0675FF504955857567065746 -O8399 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20010000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM)</Name>
<Name>-U0675FF504955857567065746 -O8399 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP (ARM Core") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20010000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -532,7 +549,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
<Name>(1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=2104,292,2581,607,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>

8
examples/arm-cm/dpp_nucleo-h743zi/qk/armclang/dpp-qk.uvprojx
View File

@ -322,7 +322,7 @@
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<wLevel>3</wLevel>
<uThumb>0</uThumb>
<uSurpInc>1</uSurpInc>
<uC99>0</uC99>
@ -1683,7 +1683,7 @@
</ArmAdsMisc>
<Cads>
<interw>0</interw>
<Optim>2</Optim>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
@ -1692,7 +1692,7 @@
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<wLevel>3</wLevel>
<uThumb>0</uThumb>
<uSurpInc>1</uSurpInc>
<uC99>0</uC99>
@ -1996,7 +1996,7 @@
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>2</wLevel>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>

119
examples/arm-cm/dpp_nucleo-h743zi/qk/bsp.c
View File

@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-02-25
* @version Last updated for: @ref qpc_7_0_0
* @date Last updated on: 2022-12-18
* @version Last updated for: @ref qpc_7_2_0
*
* @file
* @brief DPP example, NUCLEO-H743ZIE board, preemptive QK kernel
@ -61,7 +61,7 @@ static uint32_t l_rnd; /* random seed */
PHILO_STAT = QS_USER,
PAUSED_STAT,
COMMAND_STAT,
CONTEXT_SW
CONTEXT_SW,
};
#endif
@ -85,7 +85,8 @@ void SysTick_Handler(void) {
}
#endif
QTIMEEVT_TICK_X(0U, &l_SysTick_Handler); /* process time events for rate 0 */
//QTIMEEVT_TICK_X(0U, &l_SysTick_Handler); /* process time events for rate 0 */
QACTIVE_POST(&ticker0.super, 0, &l_SysTick_Handler); /* post to ticker0 */
/* Perform the debouncing of buttons. The algorithm for debouncing
* adapted from the book "Embedded Systems Dictionary" by Jack Ganssle
@ -129,8 +130,63 @@ void USART3_IRQHandler(void) {
}
#endif
/* BSP functions ===========================================================*/
/*..........................................................................*/
/* MPU setup for STM32H743ZI MCU */
static void STM32H743ZI_MPU_setup(void) {
/* The following MPU configuration contains just a generic ROM
* region (with read-only access) and NULL-pointer protection region.
* Otherwise, the MPU will fall back on the background region (PRIVDEFENA).
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=128M=2^(26+1) */
/* NOTE: this region extends to 0x080'0000, which is where
* the ROM is re-mapped by STM32
*/
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(26U << MPU_RASR_SIZE_Pos) /* 2^(26+1)=128M region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_ENABLE_Msk /* enable the MPU */
| MPU_CTRL_PRIVDEFENA_Msk; /* enable background region */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
STM32H743ZI_MPU_setup();
/* NOTE: SystemInit() has been already called from the startup code
* but SystemCoreClock needs to be updated
*/
@ -167,6 +223,7 @@ void BSP_init(void) {
QS_OBJ_DICTIONARY(AO_Philo[2]);
QS_OBJ_DICTIONARY(AO_Philo[3]);
QS_OBJ_DICTIONARY(AO_Philo[4]);
QS_OBJ_DICTIONARY(&ticker0);
QS_OBJ_DICTIONARY(&l_SysTick_Handler);
QS_USR_DICTIONARY(PHILO_STAT);
@ -175,8 +232,8 @@ void BSP_init(void) {
QS_USR_DICTIONARY(CONTEXT_SW);
/* setup the QS filters... */
QS_GLB_FILTER(QS_SM_RECORDS);
QS_GLB_FILTER(QS_UA_RECORDS);
QS_GLB_FILTER(QS_ALL_RECORDS); /* all records */
QS_GLB_FILTER(-QS_QF_TICK); /* exclude the clock tick */
}
/*..........................................................................*/
void BSP_ledOn(void) {
@ -238,18 +295,15 @@ void BSP_terminate(int16_t result) {
/*..........................................................................*/
void QF_onStartup(void) {
/* assing all priority bits for preemption-prio. and none to sub-prio. */
/* assign all priority bits for preemption-prio. and none to sub-prio.
* NOTE: this might have been changed by STM32Cube.
*/
NVIC_SetPriorityGrouping(0U);
/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */
SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);
/* set priorities of ALL ISRs used in the system, see NOTE1
*
* !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
* DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
*/
/* set priorities of ALL ISRs used in the system, see NOTE1 */
NVIC_SetPriority(USART3_IRQn, 0U); /* kernel unaware interrupt */
NVIC_SetPriority(SysTick_IRQn, QF_AWARE_ISR_CMSIS_PRI);
/* ... */
@ -262,21 +316,19 @@ void QF_onStartup(void) {
/*..........................................................................*/
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QK_ON_CONTEXT_SW
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QK_onContextSw(QActive *prev, QActive *next) {
(void)prev;
if (next != (QActive *)0) {
//_impure_ptr = next->thread; /* switch to next TLS */
void QF_onContextSw(QActive *prev, QActive *next) {
if ((prev != &ticker0.super) && (next != &ticker0.super)) {
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U) /* no critical section! */
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U) /* no critical section! */
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QK_ON_CONTEXT_SW */
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QK_onIdle(void) {
/* toggle the User LED on and then off, see NOTE2 */
@ -345,7 +397,7 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
/*..........................................................................*/
uint8_t QS_onStartup(void const *arg) {
static uint8_t qsTxBuf[2*1024]; /* buffer for QS-TX channel */
static uint8_t qsRxBuf[100]; /* buffer for QS-RX channel */
static uint8_t qsRxBuf[256]; /* buffer for QS-RX channel */
QS_initBuf (qsTxBuf, sizeof(qsTxBuf));
QS_rxInitBuf(qsRxBuf, sizeof(qsRxBuf));
@ -407,22 +459,15 @@ void QS_onReset(void) {
void QS_onCommand(uint8_t cmdId,
uint32_t param1, uint32_t param2, uint32_t param3)
{
void assert_failed(char const *module, int loc);
(void)cmdId;
(void)param1;
(void)param2;
(void)param3;
Q_UNUSED_PAR(cmdId);
Q_UNUSED_PAR(param1);
Q_UNUSED_PAR(param2);
Q_UNUSED_PAR(param3);
QS_BEGIN_ID(COMMAND_STAT, 0U) /* app-specific record */
QS_U8(2, cmdId);
QS_U32(8, param1);
QS_END()
if (cmdId == 10U) {
Q_ERROR();
}
else if (cmdId == 11U) {
assert_failed("QS_onCommand", 123);
}
}
#endif /* Q_SPY */

10
examples/arm-cm/dpp_nucleo-h743zi/qk/gnu/Makefile
View File

@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C on NUCLEO-H743ZI, QK kernel, GNU-ARM
# Last Updated for Version: 7.0.1
# Date of the Last Update: 2022-05-23
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-13
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
# Copyright (C) 2005-2021 Quantum Leaps, LLC. All rights reserved.
# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@ -146,9 +146,9 @@ LIB_DIRS :=
LIBS :=
# defines
DEFINES := -DQP_API_VERSION=9999 \
DEFINES := \
-DSTM32H743xx -DUSE_HAL_DRIVER -DUSE_STM32H7XX_NUCLEO_144 \
-DQK_ON_CONTEXT_SW
-DQF_ON_CONTEXT_SW
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]

60
examples/arm-cm/dpp_nucleo-h743zi/qk/main.c
View File

@ -1,42 +1,43 @@
/*****************************************************************************
* Product: DPP example
* Last updated for version 7.1.1
* Last updated on 2022-09-22
*
* Q u a n t u m L e a P s
* ------------------------
* Modern Embedded Software
*
/*============================================================================
* QP/C Real-Time Embedded Framework (RTEF)
* Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
*
* This program is open source software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial
*
* Alternatively, this program may be distributed and modified under the
* terms of Quantum Leaps commercial licenses, which expressly supersede
* the GNU General Public License and are specifically designed for
* licensees interested in retaining the proprietary status of their code.
* This software is dual-licensed under the terms of the open source GNU
* General Public License version 3 (or any later version), or alternatively,
* under the terms of one of the closed source Quantum Leaps commercial
* licenses.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* The terms of the open source GNU General Public License version 3
* can be found at: <www.gnu.org/licenses/gpl-3.0>
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <www.gnu.org/licenses/>.
* The terms of the closed source Quantum Leaps commercial licenses
* can be found at: <www.state-machine.com/licensing>
*
* Redistributions in source code must retain this top-level comment block.
* Plagiarizing this software to sidestep the license obligations is illegal.
*
* Contact information:
* <www.state-machine.com/licensing>
* <www.state-machine.com>
* <info@state-machine.com>
*****************************************************************************/
============================================================================*/
/*!
* @date Last updated on: 2022-12-25
* @version Last updated for: @ref qpc_7_2_0
*
* @file
* @brief DPP example
*/
#include "qpc.h"
#include "dpp.h"
#include "bsp.h"
Q_DEFINE_THIS_FILE
/*..........................................................................*/
QTicker ticker0; /* global ticker0 AO */
/*..........................................................................*/
int main() {
static QEvt const *tableQueueSto[N_PHILO];
@ -64,9 +65,16 @@ int main() {
0U, /* size of the stack [bytes] */
(void *)0); /* initialization param */
}
/* example of prioritizing the Ticker0 active object */
QTicker_ctor(&ticker0, 0U); /* ticker AO for tick rate 0 */
QACTIVE_START(&ticker0.super, N_PHILO + 1U,
0, 0, 0, 0, 0); /* not used */
QS_LOC_FILTER(-ticker0.super.prio); /* don't trace ticker0 */
Table_ctor(); /* instantiate the Table active object */
QACTIVE_START(AO_Table, /* AO to start */
N_PHILO + 1U, /* QF-prio/pre-thre. */
N_PHILO + 2U, /* QF-prio/pre-thre. */
tableQueueSto, /* event queue storage */
Q_DIM(tableQueueSto), /* queue length [events] */
(void *)0, /* stack storage (not used) */

21
examples/arm-cm/dpp_nucleo-h743zi/qv/armclang/dpp-qv.uvoptx
View File

@ -125,7 +125,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key>
<Name>-U0675FF504955857567065746 -O8399 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20010000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM)</Name>
<Name>-U0675FF504955857567065746 -O8399 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP (ARM Core") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20010000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -148,7 +148,24 @@
<Name></Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>235</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134219106</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\..\..\..\..\3rd_party\STM32CubeH7\Drivers\BSP\STM32H7xx_Nucleo_144\stm32h7xx_nucleo_144.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qv\../../../../../3rd_party/STM32CubeH7/Drivers/BSP/STM32H7xx_Nucleo_144/stm32h7xx_nucleo_144.c\235</Expression>
</Bp>
</Breakpoint>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>

4
examples/arm-cm/dpp_nucleo-h743zi/qv/armclang/dpp-qv.uvprojx
View File

@ -1017,7 +1017,7 @@
<v6LangP>3</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<v6Lto>0</v6Lto>
<v6Lto>1</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
@ -1692,7 +1692,7 @@
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<wLevel>3</wLevel>
<uThumb>0</uThumb>
<uSurpInc>1</uSurpInc>
<uC99>0</uC99>

122
examples/arm-cm/dpp_nucleo-h743zi/qv/bsp.c
View File

@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-02-25
* @version Last updated for: @ref qpc_7_0_0
* @date Last updated on: 2022-12-18
* @version Last updated for: @ref qpc_7_2_0
*
* @file
* @brief DPP example, NUCLEO-H743ZIE board, cooperative QV kernel
@ -59,7 +59,9 @@ static uint32_t l_rnd; /* random seed */
enum AppRecords { /* application-specific trace records */
PHILO_STAT = QS_USER,
COMMAND_STAT
PAUSED_STAT,
COMMAND_STAT,
CONTEXT_SW,
};
#endif
@ -81,7 +83,8 @@ void SysTick_Handler(void) {
}
#endif
QTIMEEVT_TICK_X(0U, &l_SysTick_Handler); /* process time events for rate 0 */
//QTIMEEVT_TICK_X(0U, &l_SysTick_Handler); /* process time events for rate 0 */
QACTIVE_POST(&ticker0.super, 0, &l_SysTick_Handler); /* post to ticker0 */
/* Perform the debouncing of buttons. The algorithm for debouncing
* adapted from the book "Embedded Systems Dictionary" by Jack Ganssle
@ -103,6 +106,7 @@ void SysTick_Handler(void) {
QACTIVE_PUBLISH(&serveEvt, &l_SysTick_Handler);
}
}
QV_ARM_ERRATUM_838869();
}
@ -123,8 +127,68 @@ void USART3_IRQHandler(void) {
}
#endif
/* BSP functions ===========================================================*/
/*..........................................................................*/
/* MPU setup for STM32H743ZI MCU */
static void STM32H743ZI_MPU_setup(void) {
/* The following MPU configuration contains just a generic ROM
* region (with read-only access) and NULL-pointer protection region.
* Otherwise, the MPU will fall back on the background region (PRIVDEFENA).
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=128M=2^(26+1) */
/* NOTE: this region extends to 0x080'0000, which is where
* the ROM is re-mapped by STM32
*/
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(26U << MPU_RASR_SIZE_Pos) /* 2^(26+1)=128M region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_ENABLE_Msk /* enable the MPU */
| MPU_CTRL_PRIVDEFENA_Msk; /* enable background region */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
STM32H743ZI_MPU_setup();
/* NOTE: SystemInit() has been already called from the startup code
* but SystemCoreClock needs to be updated
*/
SystemCoreClockUpdate();
SCB_EnableICache(); /* Enable I-Cache */
SCB_EnableDCache(); /* Enable D-Cache */
@ -144,7 +208,8 @@ void BSP_init(void) {
//...
BSP_randomSeed(1234U);
if (QS_INIT((void *)0) == 0) { /* initialize the QS software tracing */
/* initialize the QS software tracing... */
if (QS_INIT((void *)0) == 0) {
Q_ERROR();
}
@ -155,14 +220,17 @@ void BSP_init(void) {
QS_OBJ_DICTIONARY(AO_Philo[2]);
QS_OBJ_DICTIONARY(AO_Philo[3]);
QS_OBJ_DICTIONARY(AO_Philo[4]);
QS_OBJ_DICTIONARY(&ticker0);
QS_OBJ_DICTIONARY(&l_SysTick_Handler);
QS_USR_DICTIONARY(PHILO_STAT);
QS_USR_DICTIONARY(PAUSED_STAT);
QS_USR_DICTIONARY(COMMAND_STAT);
QS_USR_DICTIONARY(CONTEXT_SW);
/* setup the QS filters... */
QS_GLB_FILTER(QS_SM_RECORDS);
QS_GLB_FILTER(QS_UA_RECORDS);
QS_GLB_FILTER(QS_ALL_RECORDS); /* all records */
QS_GLB_FILTER(-QS_QF_TICK); /* exclude the clock tick */
}
/*..........................................................................*/
void BSP_ledOn(void) {
@ -230,12 +298,7 @@ void QF_onStartup(void) {
/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */
SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);
/* set priorities of ALL ISRs used in the system, see NOTE1
*
* !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
* DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
*/
/* set priorities of ALL ISRs used in the system, see NOTE1 */
NVIC_SetPriority(USART3_IRQn, 0U); /* kernel unaware interrupt */
NVIC_SetPriority(SysTick_IRQn, QF_AWARE_ISR_CMSIS_PRI);
/* ... */
@ -248,6 +311,18 @@ void QF_onStartup(void) {
/*..........................................................................*/
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QF_onContextSw(QActive *prev, QActive *next) {
if ((prev != &ticker0.super) && (next != &ticker0.super)) {
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U) /* no critical section! */
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
}
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QV_onIdle(void) { /* CATION: called with interrupts DISABLED, NOTE01 */
@ -318,8 +393,8 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
#ifdef Q_SPY
/*..........................................................................*/
uint8_t QS_onStartup(void const *arg) {
static uint8_t qsTxBuf[1024]; /* buffer for QS-TX channel */
static uint8_t qsRxBuf[256]; /* buffer for QS-RX channel */
static uint8_t qsTxBuf[2*1024]; /* buffer for QS-TX channel */
static uint8_t qsRxBuf[256]; /* buffer for QS-RX channel */
QS_initBuf (qsTxBuf, sizeof(qsTxBuf));
QS_rxInitBuf(qsRxBuf, sizeof(qsRxBuf));
@ -381,22 +456,15 @@ void QS_onReset(void) {
void QS_onCommand(uint8_t cmdId,
uint32_t param1, uint32_t param2, uint32_t param3)
{
void assert_failed(char const *module, int loc);
(void)cmdId;
(void)param1;
(void)param2;
(void)param3;
Q_UNUSED_PAR(cmdId);
Q_UNUSED_PAR(param1);
Q_UNUSED_PAR(param2);
Q_UNUSED_PAR(param3);
QS_BEGIN_ID(COMMAND_STAT, 0U) /* app-specific record */
QS_U8(2, cmdId);
QS_U32(8, param1);
QS_END()
if (cmdId == 10U) {
Q_ERROR();
}
else if (cmdId == 11U) {
assert_failed("QS_onCommand", 123);
}
}
#endif /* Q_SPY */

9
examples/arm-cm/dpp_nucleo-h743zi/qv/gnu/Makefile
View File

@ -1,7 +1,7 @@
##############################################################################
# Product: Makefile for QP/C on NUCLEO-H743ZI, QV kernel, GNU-ARM
# Last Updated for Version: 7.0.1
# Date of the Last Update: 2022-05-23
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-15
#
# Q u a n t u m L e a P s
# ------------------------
@ -146,7 +146,10 @@ LIB_DIRS :=
LIBS :=
# defines
DEFINES := -DSTM32H743xx -DUSE_HAL_DRIVER -DUSE_STM32H7XX_NUCLEO_144
DEFINES := -DSTM32H743xx \
-DUSE_HAL_DRIVER \
-DUSE_STM32H7XX_NUCLEO_144 \
-DQF_ON_CONTEXT_SW
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]

3
examples/arm-cm/dpp_nucleo-h743zi/qv/iar/dpp-qv.ewp
View File

@ -3171,6 +3171,9 @@
<data />
</settings>
</configuration>
<mfc>
<configuration>Release</configuration>
</mfc>
<group>
<name>Application</name>
<file>

42
examples/arm-cm/dpp_nucleo-h743zi/qv/main.c
View File

@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-02-25
* @version Last updated for: @ref qpc_7_0_0
* @date Last updated on: 2022-12-25
* @version Last updated for: @ref qpc_7_2_0
*
* @file
* @brief DPP example
@ -35,6 +35,9 @@
Q_DEFINE_THIS_FILE
/*..........................................................................*/
QTicker ticker0; /* global ticker0 AO */
/*..........................................................................*/
int main() {
static QEvt const *tableQueueSto[N_PHILO];
@ -54,22 +57,29 @@ int main() {
/* start the active objects... */
Philo_ctor(); /* instantiate all Philosopher active objects */
for (uint8_t n = 0U; n < N_PHILO; ++n) {
QACTIVE_START(AO_Philo[n], /* AO to start */
n + 1U, /* QP priority of the AO */
philoQueueSto[n], /* event queue storage */
Q_DIM(philoQueueSto[n]), /* queue length [events] */
(void *)0, /* stack storage (not used) */
0U, /* size of the stack [bytes] */
(QEvt *)0); /* initialization event */
QACTIVE_START(AO_Philo[n], /* AO to start */
n + 1U, /* QP priority of the AO */
philoQueueSto[n], /* event queue storage */
Q_DIM(philoQueueSto[n]), /* queue length [events] */
(void *)0, /* stack storage (not used) */
0U, /* size of the stack [bytes] */
(void *)0); /* initialization param */
}
/* example of prioritizing the Ticker0 active object */
QTicker_ctor(&ticker0, 0U); /* ticker AO for tick rate 0 */
QACTIVE_START(&ticker0.super, N_PHILO + 1U,
0, 0, 0, 0, 0); /* not used */
QS_LOC_FILTER(-ticker0.super.prio); /* don't trace ticker0 */
Table_ctor(); /* instantiate the Table active object */
QACTIVE_START(AO_Table, /* AO to start */
N_PHILO + 1U, /* QP priority of the AO */
tableQueueSto, /* event queue storage */
Q_DIM(tableQueueSto), /* queue length [events] */
(void *)0, /* stack storage (not used) */
0U, /* size of the stack [bytes] */
(QEvt *)0); /* initialization event */
QACTIVE_START(AO_Table, /* AO to start */
N_PHILO + 2U, /* QP priority of the AO */
tableQueueSto, /* event queue storage */
Q_DIM(tableQueueSto), /* queue length [events] */
(void *)0, /* stack storage (not used) */
0U, /* size of the stack [bytes] */
(void *)0); /* initialization param */
return QF_run(); /* run the QF application */
}

31
examples/arm-cm/dpp_nucleo-h743zi/qxk/armclang/dpp-qxk.uvoptx
View File

@ -544,36 +544,27 @@
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>279</LineNumber>
<LineNumber>327</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<Address>134242960</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\bsp.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>280</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>..\bsp.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
<Expression>\\dpp_qxk\../bsp.c\327</Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>ticker0</ItemText>
</Ww>
</WatchWindow1>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>

2
examples/arm-cm/dpp_nucleo-h743zi/qxk/armclang/dpp-qxk.uvprojx
View File

@ -1747,7 +1747,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>-Wno-padded</MiscControls>
<Define>Q_SPY,QXK_ON_CONTEXT_SW,STM32H743xx,USE_HAL_DRIVER,USE_STM32H7XX_NUCLEO_144</Define>
<Define>Q_SPY,QF_ON_CONTEXT_SW,STM32H743xx,USE_HAL_DRIVER,USE_STM32H7XX_NUCLEO_144</Define>
<Undefine></Undefine>
<IncludePath>..\..;..\..\..\..\..\include;..\..\..\..\..\ports\arm-cm\qxk\armclang;..\..\..\..\..\3rd_party\CMSIS\Include;..\..\..\..\..\3rd_party\STM32CubeH7\Drivers\CMSIS\Device\ST/STM32H7xx\Include;..\..\..\..\..\3rd_party\STM32CubeH7\Drivers\BSP\STM32H7xx_Nucleo_144;..\..\..\..\..\3rd_party\STM32CubeH7\Drivers\STM32H7xx_HAL_Driver\Inc</IncludePath>
</VariousControls>

110
examples/arm-cm/dpp_nucleo-h743zi/qxk/bsp.c
View File

@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-02-25
* @version Last updated for: @ref qpc_7_0_0
* @date Last updated on: 2022-12-18
* @version Last updated for: @ref qpc_7_2_0
*
* @file
* @brief DPP example, NUCLEO-H743ZIE board, dual-mode QXK kernel
@ -131,8 +131,63 @@ void USART3_IRQHandler(void) {
}
#endif
/* BSP functions ===========================================================*/
/*..........................................................................*/
/* MPU setup for STM32H743ZI MCU */
static void STM32H743ZI_MPU_setup(void) {
/* The following MPU configuration contains just a generic ROM
* region (with read-only access) and NULL-pointer protection region.
* Otherwise, the MPU will fall back on the background region (PRIVDEFENA).
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=128M=2^(26+1) */
/* NOTE: this region extends to 0x080'0000, which is where
* the ROM is re-mapped by STM32
*/
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(26U << MPU_RASR_SIZE_Pos) /* 2^(26+1)=128M region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
/* enable the MemManage_Handler for MPU exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_ENABLE_Msk /* enable the MPU */
| MPU_CTRL_PRIVDEFENA_Msk; /* enable background region */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
STM32H743ZI_MPU_setup();
/* NOTE: SystemInit() has been already called from the startup code
* but SystemCoreClock needs to be updated
*/
@ -181,8 +236,8 @@ void BSP_init(void) {
QS_USR_DICTIONARY(CONTEXT_SW);
/* setup the QS filters... */
QS_GLB_FILTER(QS_SM_RECORDS);
QS_GLB_FILTER(QS_UA_RECORDS);
QS_GLB_FILTER(QS_ALL_RECORDS); /* all records */
QS_GLB_FILTER(-QS_QF_TICK); /* exclude the clock tick */
}
/*..........................................................................*/
void BSP_ledOn(void) {
@ -244,18 +299,13 @@ void BSP_terminate(int16_t result) {
/*..........................................................................*/
void QF_onStartup(void) {
/* assing all priority bits for preemption-prio. and none to sub-prio. */
/* assign all priority bits for preemption-prio. and none to sub-prio. */
NVIC_SetPriorityGrouping(0U);
/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */
SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);
/* set priorities of ALL ISRs used in the system, see NOTE1
*
* !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
* DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
*/
/* set priorities of ALL ISRs used in the system, see NOTE1 */
NVIC_SetPriority(USART3_IRQn, 0U); /* kernel unaware interrupt */
NVIC_SetPriority(SysTick_IRQn, QF_AWARE_ISR_CMSIS_PRI);
/* ... */
@ -270,19 +320,18 @@ void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QXK_ON_CONTEXT_SW
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QXK_onContextSw(QActive *prev, QActive *next) {
(void)prev;
if (next != (QActive *)0) {
//_impure_ptr = next->thread; /* switch to next TLS */
void QF_onContextSw(QActive *prev, QActive *next) {
if ((prev != &ticker0.super) && (next != &ticker0.super)) {
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U) /* no critical section! */
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U) /* no critical section! */
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QXK_ON_CONTEXT_SW */
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QXK_onIdle(void) {
/* toggle the User LED on and then off, see NOTE2 */
@ -351,7 +400,7 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
/*..........................................................................*/
uint8_t QS_onStartup(void const *arg) {
static uint8_t qsTxBuf[2*1024]; /* buffer for QS-TX channel */
static uint8_t qsRxBuf[100]; /* buffer for QS-RX channel */
static uint8_t qsRxBuf[256]; /* buffer for QS-RX channel */
QS_initBuf (qsTxBuf, sizeof(qsTxBuf));
QS_rxInitBuf(qsRxBuf, sizeof(qsRxBuf));
@ -413,22 +462,15 @@ void QS_onReset(void) {
void QS_onCommand(uint8_t cmdId,
uint32_t param1, uint32_t param2, uint32_t param3)
{
void assert_failed(char const *module, int loc);
(void)cmdId;
(void)param1;
(void)param2;
(void)param3;
Q_UNUSED_PAR(cmdId);
Q_UNUSED_PAR(param1);
Q_UNUSED_PAR(param2);
Q_UNUSED_PAR(param3);
QS_BEGIN_ID(COMMAND_STAT, 0U) /* app-specific record */
QS_U8(2, cmdId);
QS_U32(8, param1);
QS_END()
if (cmdId == 10U) {
Q_ERROR();
}
else if (cmdId == 11U) {
assert_failed("QS_onCommand", 123);
}
}
#endif /* Q_SPY */

8
examples/arm-cm/dpp_nucleo-h743zi/qxk/gnu/Makefile
View File

@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C on NUCLEO-H743ZI, QXK kernel, GNU-ARM
# Last Updated for Version: 7.0.1
# Date of the Last Update: 2022-05-23
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-13
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
# Copyright (C) 2005-2021 Quantum Leaps, LLC. All rights reserved.
# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@ -150,7 +150,7 @@ LIB_DIRS :=
LIBS :=
# defines
DEFINES := -DQXK_ON_CONTEXT_SW -DSTM32H743xx -DUSE_HAL_DRIVER -DUSE_STM32H7XX_NUCLEO_144
DEFINES := -DQF_ON_CONTEXT_SW -DSTM32H743xx -DUSE_HAL_DRIVER -DUSE_STM32H7XX_NUCLEO_144
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]

2
examples/arm-cm/dpp_nucleo-h743zi/qxk/iar/dpp-qxk.ewp
View File

@ -214,7 +214,7 @@
</option>
<option>
<name>CCDefines</name>
<state>QXK_ON_CONTEXT_SW</state>
<state>QF_ON_CONTEXT_SW</state>
<state>STM32H743xx</state>
<state>USE_HAL_DRIVER</state>
<state>USE_STM32H7XX_NUCLEO_144</state>

14
examples/arm-cm/dpp_nucleo-h743zi/qxk/main.c
View File

@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-02-25
* @version Last updated for: @ref qpc_7_0_0
* @date Last updated on: 2022-12-25
* @version Last updated for: @ref qpc_7_2_0
*
* @file
* @brief DPP example
@ -68,7 +68,7 @@ int main() {
Q_DIM(test1QueueSto), /* message length [events] */
test1StackSto, /* stack storage */
sizeof(test1StackSto), /* stack size [bytes] */
(QEvt *)0); /* initialization event */
(void *)0); /* initialization param */
/* NOTE: leave priority 2 free for a mutex */
@ -81,14 +81,14 @@ int main() {
Q_DIM(philoQueueSto[n]), /* queue length [events] */
(void *)0, /* stack storage (not used) */
0U, /* size of the stack [bytes] */
(QEvt *)0); /* initialization event */
(void *)0); /* initialization param */
}
/* example of prioritizing the Ticker0 active object */
QTicker_ctor(&ticker0, 0U); /* ticker AO for tick rate 0 */
QACTIVE_START(&ticker0.super, N_PHILO + 3U,
0, 0, 0, 0, 0); /* not used */
QS_LOC_FILTER(-ticker0.super.prio); /* don't trace ticker0 */
QS_LOC_FILTER(-ticker0.super.prio); /* don't trace ticker0 */
/* NOTE: leave priority (N_PHILO + 4) free for mutex */
@ -99,7 +99,7 @@ int main() {
Q_DIM(test2QueueSto), /* message length [events] */
test2StackSto, /* stack storage */
sizeof(test2StackSto), /* stack size [bytes] */
(QEvt *)0); /* initialization event */
(void *)0); /* initialization param */
/* NOTE: leave priority (N_PHILO + 6) free for mutex */
@ -110,7 +110,7 @@ int main() {
Q_DIM(tableQueueSto), /* queue length [events] */
(void *)0, /* stack storage (not used) */
0U, /* size of the stack [bytes] */
(QEvt *)0); /* initialization event */
(void *)0); /* initialization param */
return QF_run(); /* run the QF application */
}

6
examples/arm-cm/dpp_nucleo-h743zi/table.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::table.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -64,8 +64,8 @@ static QState Table_paused(Table * const me, QEvt const * const e);
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

2
examples/arm-cm/dpp_nucleo-l053r8/dpp.h
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::dpp.h}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later

2
examples/arm-cm/dpp_nucleo-l053r8/dpp.qm
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<model version="5.2.2" links="1">
<model version="5.2.4" links="1">
<documentation>Dining Philosopher Problem example</documentation>
<!--${qpc}-->
<framework name="qpc"/>

6
examples/arm-cm/dpp_nucleo-l053r8/philo.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::philo.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -66,8 +66,8 @@ static QState Philo_eating(Philo * const me, QEvt const * const e);
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

58
examples/arm-cm/dpp_nucleo-l053r8/qk/armclang/dpp-qk.uvoptx
View File

@ -140,7 +140,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=979,559,1390,1061,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
<Name>(1010=979,559,1390,1061,0)(1007=2082,245,2289,466,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -152,18 +152,66 @@
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>96</LineNumber>
<LineNumber>409</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134221926</Address>
<Address>134225552</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\..\..\..\..\ports\arm-cm\qk\armclang\qk_port.c</Filename>
<Filename>..\bsp.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qk\../../../../../ports/arm-cm/qk/armclang/qk_port.c\96</Expression>
<Expression>\\dpp_qk\../bsp.c\409</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>113</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134225852</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\bsp.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qk\../bsp.c\113</Expression>
</Bp>
<Bp>
<Number>2</Number>
<Type>0</Type>
<LineNumber>233</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134218734</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\bsp.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qk\../bsp.c\233</Expression>
</Bp>
<Bp>
<Number>3</Number>
<Type>0</Type>
<LineNumber>320</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>..\..\..\..\..\3rd_party\nucleo-l053r8\arm\startup_stm32l053xx.s</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
</Breakpoint>
<MemoryWindow1>

2
examples/arm-cm/dpp_nucleo-l053r8/qk/armclang/dpp-qk.uvprojx
View File

@ -313,7 +313,7 @@
</ArmAdsMisc>
<Cads>
<interw>0</interw>
<Optim>7</Optim>
<Optim>0</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>

169
examples/arm-cm/dpp_nucleo-l053r8/qk/bsp.c
View File

@ -1,7 +1,7 @@
/*****************************************************************************
/*============================================================================
* Product: DPP example, NUCLEO-L053R8 board, preemptive QK kernel
* Last updated for version 6.9.3
* Last updated on 2021-03-03
* Last updated for version 7.2.0
* Last updated on 2022-12-13
*
* Q u a n t u m L e a P s
* ------------------------
@ -30,7 +30,7 @@
* Contact information:
* <www.state-machine.com/licensing>
* <info@state-machine.com>
*****************************************************************************/
============================================================================*/
#include "qpc.h"
#include "dpp.h"
#include "bsp.h"
@ -107,7 +107,7 @@ void SysTick_Handler(void) { /* system clock tick ISR */
static QEvt const pauseEvt = { PAUSE_SIG, 0U, 0U};
QACTIVE_PUBLISH(&pauseEvt, &l_SysTick_Handler);
}
else { /* the button is released */
else { /* the button is released */
static QEvt const serveEvt = { SERVE_SIG, 0U, 0U};
QACTIVE_PUBLISH(&serveEvt, &l_SysTick_Handler);
}
@ -136,7 +136,128 @@ void USART2_IRQHandler(void) { /* used in QS-RX (kernel UNAWARE interrutp) */
#endif
/* BSP functions ===========================================================*/
/*..........................................................................*/
/* MPU setup for STM32L053R8 MCU */
static void STM32L053R8_MPU_setup(void) {
/* The following MPU configuration contains the general STM32 memory model
* as described in the ST AppNote AN4838 "Managing memory protection unit
* in STM32 MCUs", Figure 2. Cortex-M0+/M3/M4/M7 processor memory map.
*
* Please note that the actual STM32 MCUs provide much less Flash and SRAM
* than the maximums configured here. This means that actual MCUs have
* unmapped memory regions (e.g., beyond the actual SRAM). Attempts to
* access these regions causes the HardFault exception, which is the
* desired behavior.
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #1: SRAM: base=0x2000'0000, size=512M=2^(28+1) */
0x20000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 1U), /* region #1 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
/* region #3: (not configured) */
{ MPU_RBAR_VALID_Msk | (MPU_RBAR_REGION_Msk & 2U), 0U },
{ /* region #3: Peripherals: base=0x4000'0000, size=512M=2^(28+1) */
0x40000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 3U), /* region #3 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #4: Priv. Periph: base=0xE000'0000, size=512M=2^(28+1) */
0xE0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 4U), /* region #4 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #5: Ext RAM: base=0x6000'0000, size=1G=2^(29+1) */
0x60000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 5U), /* region #5 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #6: Ext Dev: base=0xA000'0000, size=1G=2^(29+1) */
0xA0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 6U), /* region #6 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=128M=2^(26+1) */
/* NOTE: this region extends to 0x080'0000, which is where
* the ROM is re-mapped by STM32
*/
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(26U << MPU_RASR_SIZE_Pos) /* 2^(26+1)=128M region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk /* enable background region */
| MPU_CTRL_ENABLE_Msk; /* enable the MPU */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
STM32L053R8_MPU_setup();
/* NOTE: SystemInit() has been already called from the startup code
* but SystemCoreClock needs to be updated
*/
@ -238,15 +359,10 @@ void QF_onStartup(void) {
/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */
SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);
/* set priorities of ALL ISRs used in the system, see NOTE00
*
* !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
* DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
*/
NVIC_SetPriority(SysTick_IRQn, QF_AWARE_ISR_CMSIS_PRI + 1);
NVIC_SetPriority(EXTI0_1_IRQn, QF_AWARE_ISR_CMSIS_PRI + 2);
NVIC_SetPriority(USART2_IRQn, 0); /* kernel UNAWARE interrupt */
/* set priorities of ALL ISRs used in the system */
NVIC_SetPriority(USART2_IRQn, 0);
NVIC_SetPriority(SysTick_IRQn, QF_AWARE_ISR_CMSIS_PRI + 0U);
NVIC_SetPriority(EXTI0_1_IRQn, QF_AWARE_ISR_CMSIS_PRI + 1U);
/* ... */
/* enable IRQs... */
@ -259,15 +375,15 @@ void QF_onStartup(void) {
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QK_ON_CONTEXT_SW
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QK_onContextSw(QActive *prev, QActive *next) {
void QF_onContextSw(QActive *prev, QActive *next) {
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U) /* no critical section! */
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QK_ON_CONTEXT_SW */
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QK_onIdle(void) { /* called with interrupts enabled */
@ -339,7 +455,7 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
/*..........................................................................*/
uint8_t QS_onStartup(void const *arg) {
static uint8_t qsBuf[2*1024]; /* buffer for Quantum Spy */
static uint8_t qsRxBuf[128]; /* buffer for QS-RX channel */
static uint8_t qsRxBuf[256]; /* buffer for QS-RX channel */
(void)arg; /* avoid the "unused parameter" compiler warning */
@ -418,23 +534,6 @@ void QS_onCommand(uint8_t cmdId,
/*--------------------------------------------------------------------------*/
/*****************************************************************************
* NOTE00:
* The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
* ISR priority that is disabled by the QF framework. The value is suitable
* for the NVIC_SetPriority() CMSIS function.
*
* Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e.,
* with the numerical values of priorities equal or higher than
* QF_AWARE_ISR_CMSIS_PRI) are allowed to call any QF services. These ISRs
* are "QF-aware".
*
* Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority
* level (i.e., with the numerical values of priorities less than
* QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel.
* Such "QF-unaware" ISRs cannot call any QF services. The only mechanism
* by which a "QF-unaware" ISR can communicate with the QF framework is by
* triggering a "QF-aware" ISR, which can post/publish events.
*
* NOTE01:
* Usually, one of the LEDs is used to visualize the idle loop activity.
* However, the board has not enough LEDs (only one, actually), so this

8
examples/arm-cm/dpp_nucleo-l053r8/qk/gnu/Makefile
View File

@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C on NUCLEO-L053R8, QK kernel, GNU-ARM
# Last Updated for Version: 7.0.1
# Date of the Last Update: 2022-05-23
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-13
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
# Copyright (C) 2005-2021 Quantum Leaps, LLC. All rights reserved.
# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@ -133,7 +133,7 @@ LIBS :=
# defines
DEFINES := \
-DQK_ON_CONTEXT_SW \
-DQF_ON_CONTEXT_SW \
-DQK_USE_IRQ_NUM=30 \
-DQK_USE_IRQ_HANDLER=LCD_IRQHandler

10
examples/arm-cm/dpp_nucleo-l053r8/qk/gnu_with-stack-prot/bsp_stack-prot.c
View File

@ -62,7 +62,7 @@ static uint32_t l_rnd; /* random seed */
enum AppRecords { /* application-specific trace records */
PHILO_STAT = QS_USER,
ON_CONTEXT_SW
CONTEXT_SW
};
#endif
@ -158,7 +158,7 @@ void BSP_init(void) {
}
QS_OBJ_DICTIONARY(&l_SysTick_Handler);
QS_USR_DICTIONARY(PHILO_STAT);
QS_USR_DICTIONARY(ON_CONTEXT_SW);
QS_USR_DICTIONARY(CONTEXT_SW);
/* setup the QS filters... */
QS_GLB_FILTER(QS_SM_RECORDS);
@ -242,19 +242,19 @@ void QF_onStartup(void) {
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QK_ON_CONTEXT_SW
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QK_onContextSw(QActive *prev, QActive *next) {
(void)prev;
if (next != (QActive *)0) {
//_impure_ptr = next->thread; /* switch to next TLS */
}
QS_BEGIN_NOCRIT(ON_CONTEXT_SW, 0U) /* no critical section! */
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U) /* no critical section! */
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QK_ON_CONTEXT_SW */
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QK_onIdle(void) { /* called with interrupts enabled */

25
examples/arm-cm/dpp_nucleo-l053r8/qv/armclang/dpp-qv.uvoptx
View File

@ -10,7 +10,7 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
@ -103,7 +103,7 @@
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<nTsel>6</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -125,7 +125,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key>
<Name>-U066CFF484951775087074312 -O8431 -SF480 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32L0xx_64.FLM -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$CMSIS\Flash\STM32L0xx_64.FLM)</Name>
<Name>-U066CFF484951775087074312 -O8431 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP (ARM Core") -D00(0BC11477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32L0xx_64.FLM -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$CMSIS\Flash\STM32L0xx_64.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -148,7 +148,24 @@
<Name></Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>427</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134224692</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\bsp.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\dpp_qv\../bsp.c\427</Expression>
</Bp>
</Breakpoint>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>

23
examples/arm-cm/dpp_nucleo-l053r8/qv/armclang/dpp-qv.uvprojx
View File

@ -10,13 +10,13 @@
<TargetName>dpp-dbg</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6130001::V6.13.1::.\ARMCLANG</pCCUsed>
<pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>STM32L053R8Tx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L0xx_DFP.2.0.0</PackID>
<PackID>Keil.STM32L0xx_DFP.2.2.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -185,6 +185,7 @@
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -312,7 +313,7 @@
</ArmAdsMisc>
<Cads>
<interw>0</interw>
<Optim>2</Optim>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
@ -351,7 +352,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>1</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define>Stack_Size=2048 Heap_Size=16</Define>
@ -615,7 +616,7 @@
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<ClangAsOpt>0</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -665,7 +666,7 @@
<TargetCommonOption>
<Device>STM32L053R8Tx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L0xx_DFP.2.0.0</PackID>
<PackID>Keil.STM32L0xx_DFP.2.2.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -834,6 +835,7 @@
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -1000,7 +1002,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>1</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define>Stack_Size=2048 Heap_Size=16</Define>
@ -1264,7 +1266,7 @@
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<ClangAsOpt>0</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -1314,7 +1316,7 @@
<TargetCommonOption>
<Device>STM32L053R8Tx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L0xx_DFP.2.0.0</PackID>
<PackID>Keil.STM32L0xx_DFP.2.2.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -1483,6 +1485,7 @@
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -1649,7 +1652,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>1</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define>Stack_Size=2048 Heap_Size=16</Define>

181
examples/arm-cm/dpp_nucleo-l053r8/qv/bsp.c
View File

@ -1,7 +1,7 @@
/*****************************************************************************
/*============================================================================
* Product: DPP example, NUCLEO-L053R8 board, cooperative QV kernel
* Last updated for version 6.9.3
* Last updated on 2021-03-03
* Last updated for version 7.2.0
* Last updated on 2022-12-13
*
* Q u a n t u m L e a P s
* ------------------------
@ -30,7 +30,7 @@
* Contact information:
* <www.state-machine.com/licensing>
* <info@state-machine.com>
*****************************************************************************/
============================================================================*/
#include "qpc.h"
#include "dpp.h"
#include "bsp.h"
@ -57,7 +57,8 @@ static uint32_t l_rnd; /* random seed */
static QSpyId const l_SysTick_Handler = { 0U };
enum AppRecords { /* application-specific trace records */
PHILO_STAT = QS_USER
PHILO_STAT = QS_USER,
CONTEXT_SW,
};
#endif
@ -130,7 +131,128 @@ void USART2_IRQHandler(void) { /* used in QS-RX (kernel UNAWARE interrutp) */
#endif
/* BSP functions ===========================================================*/
/*..........................................................................*/
/* MPU setup for STM32L053R8 MCU */
static void STM32L053R8_MPU_setup(void) {
/* The following MPU configuration contains the general STM32 memory model
* as described in the ST AppNote AN4838 "Managing memory protection unit
* in STM32 MCUs", Figure 2. Cortex-M0+/M3/M4/M7 processor memory map.
*
* Please note that the actual STM32 MCUs provide much less Flash and SRAM
* than the maximums configured here. This means that actual MCUs have
* unmapped memory regions (e.g., beyond the actual SRAM). Attempts to
* access these regions causes the HardFault exception, which is the
* desired behavior.
*/
static struct {
uint32_t rbar;
uint32_t rasr;
} const mpu_setup[] = {
{ /* region #0: Flash: base=0x0000'0000, size=512M=2^(28+1) */
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 0U), /* region #0 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(18+1) region */
| (0x6U << MPU_RASR_AP_Pos) /* PA:ro/UA:ro */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #1: SRAM: base=0x2000'0000, size=512M=2^(28+1) */
0x20000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 1U), /* region #1 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_C_Pos) /* C=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
/* region #3: (not configured) */
{ MPU_RBAR_VALID_Msk | (MPU_RBAR_REGION_Msk & 2U), 0U },
{ /* region #3: Peripherals: base=0x4000'0000, size=512M=2^(28+1) */
0x40000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 3U), /* region #3 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #4: Priv. Periph: base=0xE000'0000, size=512M=2^(28+1) */
0xE0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 4U), /* region #4 */
(28U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #5: Ext RAM: base=0x6000'0000, size=1G=2^(29+1) */
0x60000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 5U), /* region #5 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #6: Ext Dev: base=0xA000'0000, size=1G=2^(29+1) */
0xA0000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 6U), /* region #6 */
(29U << MPU_RASR_SIZE_Pos) /* 2^(28+1) region */
| (0x3U << MPU_RASR_AP_Pos) /* PA:rw/UA:rw */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| (1U << MPU_RASR_S_Pos) /* S=1 */
| (1U << MPU_RASR_B_Pos) /* B=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
{ /* region #7: NULL-pointer: base=0x000'0000, size=128M=2^(26+1) */
/* NOTE: this region extends to 0x080'0000, which is where
* the ROM is re-mapped by STM32
*/
0x00000000U /* base address */
| MPU_RBAR_VALID_Msk /* valid region */
| (MPU_RBAR_REGION_Msk & 7U), /* region #7 */
(26U << MPU_RASR_SIZE_Pos) /* 2^(26+1)=128M region */
| (0x0U << MPU_RASR_AP_Pos) /* PA:na/UA:na */
| (1U << MPU_RASR_XN_Pos) /* XN=1 */
| MPU_RASR_ENABLE_Msk /* region enable */
},
};
__DSB();
MPU->CTRL = 0U; /* disable the MPU */
for (uint_fast8_t n = 0U; n < Q_DIM(mpu_setup); ++n) {
MPU->RBAR = mpu_setup[n].rbar;
MPU->RASR = mpu_setup[n].rasr;
}
MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk /* enable background region */
| MPU_CTRL_ENABLE_Msk; /* enable the MPU */
__ISB();
__DSB();
}
/*..........................................................................*/
void BSP_init(void) {
/* setup the MPU... */
STM32L053R8_MPU_setup();
/* NOTE: SystemInit() has been already called from the startup code
* but SystemCoreClock needs to be updated
*/
@ -164,10 +286,11 @@ void BSP_init(void) {
}
QS_OBJ_DICTIONARY(&l_SysTick_Handler);
QS_USR_DICTIONARY(PHILO_STAT);
QS_USR_DICTIONARY(CONTEXT_SW);
/* setup the QS filters... */
QS_GLB_FILTER(QS_SM_RECORDS);
QS_GLB_FILTER(QS_UA_RECORDS);
QS_GLB_FILTER(QS_ALL_RECORDS); /* all records */
QS_GLB_FILTER(-QS_QF_TICK); /* exclude the clock tick */
}
/*..........................................................................*/
void BSP_displayPhilStat(uint8_t n, char const *stat) {
@ -230,15 +353,10 @@ void QF_onStartup(void) {
/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */
SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);
/* set priorities of ALL ISRs used in the system, see NOTE00
*
* !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
* DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
*/
NVIC_SetPriority(USART2_IRQn, 0U); /* kernel UNAWARE interrupt */
NVIC_SetPriority(SysTick_IRQn, QF_AWARE_ISR_CMSIS_PRI + 1U);
NVIC_SetPriority(EXTI0_1_IRQn, QF_AWARE_ISR_CMSIS_PRI + 2U);
/* set priorities of ALL ISRs used in the system */
NVIC_SetPriority(USART2_IRQn, 0);
NVIC_SetPriority(SysTick_IRQn, QF_AWARE_ISR_CMSIS_PRI + 0U);
NVIC_SetPriority(EXTI0_1_IRQn, QF_AWARE_ISR_CMSIS_PRI + 1U);
/* ... */
/* enable IRQs... */
@ -251,6 +369,16 @@ void QF_onStartup(void) {
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QF_onContextSw(QActive *prev, QActive *next) {
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U) /* no critical section! */
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QV_onIdle(void) { /* called with interrupts disabled, see NOTE01 */
/* toggle an LED on and then off (not enough LEDs, see NOTE02) */
@ -323,7 +451,7 @@ Q_NORETURN Q_onAssert(char const * const module, int_t const loc) {
/*..........................................................................*/
uint8_t QS_onStartup(void const *arg) {
static uint8_t qsBuf[1024]; /* buffer for Quantum Spy */
static uint8_t qsBuf[2*1024]; /* buffer for Quantum Spy */
static uint8_t qsRxBuf[256]; /* buffer for QS-RX channel */
(void)arg; /* avoid the "unused parameter" compiler warning */
@ -378,7 +506,7 @@ void QS_onFlush(void) {
QF_INT_ENABLE();
while ((USART2->ISR & (1U << 7)) == 0U) { /* while TXE not empty */
}
USART2->TDR = (b & 0xFFU); /* put into the DR register */
USART2->TDR = (b & 0xFFU); /* put into the DR register */
QF_INT_DISABLE();
}
QF_INT_ENABLE();
@ -403,23 +531,6 @@ void QS_onCommand(uint8_t cmdId,
/*--------------------------------------------------------------------------*/
/*****************************************************************************
* NOTE00:
* The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
* ISR priority that is disabled by the QF framework. The value is suitable
* for the NVIC_SetPriority() CMSIS function.
*
* Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e.,
* with the numerical values of priorities equal or higher than
* QF_AWARE_ISR_CMSIS_PRI) are allowed to call any QF services. These ISRs
* are "QF-aware".
*
* Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority
* level (i.e., with the numerical values of priorities less than
* QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel.
* Such "QF-unaware" ISRs cannot call any QF services. The only mechanism
* by which a "QF-unaware" ISR can communicate with the QF framework is by
* triggering a "QF-aware" ISR, which can post/publish events.
*
* NOTE01:
* The QV_onIdle() callback is called with interrupts disabled, because the
* determination of the idle condition might change by any interrupt posting

6
examples/arm-cm/dpp_nucleo-l053r8/qv/gnu/Makefile
View File

@ -1,7 +1,7 @@
##############################################################################
# Product: Makefile for QP/C on NUCLEO-L053R8, QV kernel, GNU-ARM
# Last Updated for Version: 7.0.1
# Date of the Last Update: 2022-05-23
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-13
#
# Q u a n t u m L e a P s
# ------------------------
@ -133,7 +133,7 @@ LIB_DIRS :=
LIBS :=
# defines
DEFINES :=
DEFINES := -DQV_ON_CONTEXT_SW
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]

328
examples/arm-cm/dpp_nucleo-l053r8/qv/iar/dpp-qv.ewp
View File

@ -11,9 +11,13 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>31</version>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>BrowseInfoPath</name>
<state>Debug\BrowseInfo</state>
</option>
<option>
<name>ExePath</name>
<state>dbg</state>
@ -32,11 +36,11 @@
</option>
<option>
<name>Input description</name>
<state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>
<state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>
</option>
<option>
<name>Output description</name>
<state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>
<state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>
</option>
<option>
<name>GOutputBinary</name>
@ -66,15 +70,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>8.40.2.22864</state>
</option>
<option>
<name>GeneralEnableMisra</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraVerbose</name>
<state>0</state>
<state>9.10.2.39304</state>
</option>
<option>
<name>OGChipSelectEditMenu</name>
@ -96,27 +92,13 @@
<name>GenStdoutInterface</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>GeneralMisraVer</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>27</version>
<version>30</version>
<state>35</state>
</option>
<option>
@ -133,7 +115,7 @@
</option>
<option>
<name>CoreVariant</name>
<version>27</version>
<version>30</version>
<state>35</state>
</option>
<option>
@ -156,7 +138,7 @@
</option>
<option>
<name>GFPUCoreSlave2</name>
<version>27</version>
<version>30</version>
<state>35</state>
</option>
<option>
@ -209,13 +191,21 @@
<version>0</version>
<state>0</state>
</option>
<option>
<name>OGAarch64Abi</name>
<state>0</state>
</option>
<option>
<name>OG_32_64Device</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>ICCARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>35</version>
<version>37</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -343,10 +333,6 @@
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CompilerMisraOverride</name>
<state>0</state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..\..</state>
@ -380,16 +366,6 @@
<name>CCOptLevelSlave</name>
<state>1</state>
</option>
<option>
<name>CompilerMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>CompilerMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>CCPosIndRopi</name>
<state>0</state>
@ -471,13 +447,17 @@
<name>OICompilerExtraOption</name>
<state>1</state>
</option>
<option>
<name>CCStackProtection</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>AARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>10</version>
<version>11</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -633,6 +613,10 @@
<name>AsmNoLiteralPool</name>
<state>0</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
</data>
</settings>
<settings>
@ -672,13 +656,9 @@
<extensions></extensions>
<cmdline></cmdline>
<hasPrio>0</hasPrio>
<buildSequence>inputOutputBased</buildSequence>
</data>
</settings>
<settings>
<name>BICOMP</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
@ -691,17 +671,13 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>23</version>
<version>25</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>IlinkLibIOConfig</name>
<state>1</state>
</option>
<option>
<name>XLinkMisraHandler</name>
<state>0</state>
</option>
<option>
<name>IlinkInputFileSlave</name>
<state>0</state>
@ -1027,6 +1003,26 @@
<name>IlinkRawBinaryAlign2</name>
<state></state>
</option>
<option>
<name>IlinkLogCrtRoutineSelection</name>
<state>0</state>
</option>
<option>
<name>IlinkLogFragmentInfo</name>
<state>0</state>
</option>
<option>
<name>IlinkLogInlining</name>
<state>0</state>
</option>
<option>
<name>IlinkLogMerging</name>
<state>0</state>
</option>
<option>
<name>IlinkDemangle</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -1050,11 +1046,6 @@
</option>
</data>
</settings>
<settings>
<name>BILINK</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>Coder</name>
<archiveVersion>0</archiveVersion>
@ -1071,9 +1062,13 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>31</version>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>BrowseInfoPath</name>
<state>Release\BrowseInfo</state>
</option>
<option>
<name>ExePath</name>
<state>rel</state>
@ -1126,15 +1121,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>8.40.2.22864</state>
</option>
<option>
<name>GeneralEnableMisra</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraVerbose</name>
<state>0</state>
<state>9.10.2.39304</state>
</option>
<option>
<name>OGChipSelectEditMenu</name>
@ -1156,27 +1143,13 @@
<name>GenStdoutInterface</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>GeneralMisraVer</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>27</version>
<version>30</version>
<state>35</state>
</option>
<option>
@ -1193,7 +1166,7 @@
</option>
<option>
<name>CoreVariant</name>
<version>27</version>
<version>30</version>
<state>35</state>
</option>
<option>
@ -1216,7 +1189,7 @@
</option>
<option>
<name>GFPUCoreSlave2</name>
<version>27</version>
<version>30</version>
<state>35</state>
</option>
<option>
@ -1269,13 +1242,21 @@
<version>0</version>
<state>0</state>
</option>
<option>
<name>OGAarch64Abi</name>
<state>0</state>
</option>
<option>
<name>OG_32_64Device</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>ICCARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>35</version>
<version>37</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -1403,10 +1384,6 @@
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CompilerMisraOverride</name>
<state>0</state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..\..</state>
@ -1440,16 +1417,6 @@
<name>CCOptLevelSlave</name>
<state>3</state>
</option>
<option>
<name>CompilerMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>CompilerMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>CCPosIndRopi</name>
<state>0</state>
@ -1531,13 +1498,17 @@
<name>OICompilerExtraOption</name>
<state>1</state>
</option>
<option>
<name>CCStackProtection</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>AARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>10</version>
<version>11</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -1693,6 +1664,10 @@
<name>AsmNoLiteralPool</name>
<state>0</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
</data>
</settings>
<settings>
@ -1732,13 +1707,9 @@
<extensions></extensions>
<cmdline></cmdline>
<hasPrio>0</hasPrio>
<buildSequence>inputOutputBased</buildSequence>
</data>
</settings>
<settings>
<name>BICOMP</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
@ -1751,17 +1722,13 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>23</version>
<version>25</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>IlinkLibIOConfig</name>
<state>1</state>
</option>
<option>
<name>XLinkMisraHandler</name>
<state>0</state>
</option>
<option>
<name>IlinkInputFileSlave</name>
<state>0</state>
@ -2087,6 +2054,26 @@
<name>IlinkRawBinaryAlign2</name>
<state></state>
</option>
<option>
<name>IlinkLogCrtRoutineSelection</name>
<state>0</state>
</option>
<option>
<name>IlinkLogFragmentInfo</name>
<state>0</state>
</option>
<option>
<name>IlinkLogInlining</name>
<state>0</state>
</option>
<option>
<name>IlinkLogMerging</name>
<state>0</state>
</option>
<option>
<name>IlinkDemangle</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -2110,11 +2097,6 @@
</option>
</data>
</settings>
<settings>
<name>BILINK</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>Coder</name>
<archiveVersion>0</archiveVersion>
@ -2131,9 +2113,13 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>31</version>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>BrowseInfoPath</name>
<state>Spy\BrowseInfo</state>
</option>
<option>
<name>ExePath</name>
<state>spy</state>
@ -2186,15 +2172,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>8.40.2.22864</state>
</option>
<option>
<name>GeneralEnableMisra</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraVerbose</name>
<state>0</state>
<state>9.10.2.39304</state>
</option>
<option>
<name>OGChipSelectEditMenu</name>
@ -2216,27 +2194,13 @@
<name>GenStdoutInterface</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>GeneralMisraVer</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>27</version>
<version>30</version>
<state>35</state>
</option>
<option>
@ -2253,7 +2217,7 @@
</option>
<option>
<name>CoreVariant</name>
<version>27</version>
<version>30</version>
<state>35</state>
</option>
<option>
@ -2276,7 +2240,7 @@
</option>
<option>
<name>GFPUCoreSlave2</name>
<version>27</version>
<version>30</version>
<state>35</state>
</option>
<option>
@ -2329,13 +2293,21 @@
<version>0</version>
<state>0</state>
</option>
<option>
<name>OGAarch64Abi</name>
<state>0</state>
</option>
<option>
<name>OG_32_64Device</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>ICCARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>35</version>
<version>37</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -2463,10 +2435,6 @@
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CompilerMisraOverride</name>
<state>0</state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..\..</state>
@ -2500,16 +2468,6 @@
<name>CCOptLevelSlave</name>
<state>1</state>
</option>
<option>
<name>CompilerMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>CompilerMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>CCPosIndRopi</name>
<state>0</state>
@ -2591,13 +2549,17 @@
<name>OICompilerExtraOption</name>
<state>1</state>
</option>
<option>
<name>CCStackProtection</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>AARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>10</version>
<version>11</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -2753,6 +2715,10 @@
<name>AsmNoLiteralPool</name>
<state>0</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
</data>
</settings>
<settings>
@ -2792,13 +2758,9 @@
<extensions></extensions>
<cmdline></cmdline>
<hasPrio>0</hasPrio>
<buildSequence>inputOutputBased</buildSequence>
</data>
</settings>
<settings>
<name>BICOMP</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
@ -2811,17 +2773,13 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>23</version>
<version>25</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>IlinkLibIOConfig</name>
<state>1</state>
</option>
<option>
<name>XLinkMisraHandler</name>
<state>0</state>
</option>
<option>
<name>IlinkInputFileSlave</name>
<state>0</state>
@ -3147,6 +3105,26 @@
<name>IlinkRawBinaryAlign2</name>
<state></state>
</option>
<option>
<name>IlinkLogCrtRoutineSelection</name>
<state>0</state>
</option>
<option>
<name>IlinkLogFragmentInfo</name>
<state>0</state>
</option>
<option>
<name>IlinkLogInlining</name>
<state>0</state>
</option>
<option>
<name>IlinkLogMerging</name>
<state>0</state>
</option>
<option>
<name>IlinkDemangle</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -3170,17 +3148,15 @@
</option>
</data>
</settings>
<settings>
<name>BILINK</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
<settings>
<name>Coder</name>
<archiveVersion>0</archiveVersion>
<data />
</settings>
</configuration>
<mfc>
<configuration>Release</configuration>
</mfc>
<group>
<name>Application</name>
<file>

4
examples/arm-cm/dpp_nucleo-l053r8/qxk/armclang/dpp-qxk.uvprojx
View File

@ -337,7 +337,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>QXK_ON_CONTEXT_SW</Define>
<Define>QF_ON_CONTEXT_SW</Define>
<Undefine></Undefine>
<IncludePath>..\..;..\..\..\..\..\include;..\..\..\..\..\ports\arm-cm\qxk\armclang;..\..\..\..\..\3rd_party\CMSIS\Include;..\..\..\..\..\3rd_party\nucleo-l053r8</IncludePath>
</VariousControls>
@ -1738,7 +1738,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>Q_SPY,QXK_ON_CONTEXT_SW</Define>
<Define>Q_SPY,QF_ON_CONTEXT_SW</Define>
<Undefine></Undefine>
<IncludePath>..\..;..\..\..\..\..\include;..\..\..\..\..\ports\arm-cm\qxk\armclang;..\..\..\..\..\3rd_party\CMSIS\Include;..\..\..\..\..\3rd_party\nucleo-l053r8</IncludePath>
</VariousControls>

6
examples/arm-cm/dpp_nucleo-l053r8/qxk/bsp.c
View File

@ -261,15 +261,15 @@ void QF_onStartup(void) {
void QF_onCleanup(void) {
}
/*..........................................................................*/
#ifdef QXK_ON_CONTEXT_SW
#ifdef QF_ON_CONTEXT_SW
/* NOTE: the context-switch callback is called with interrupts DISABLED */
void QXK_onContextSw(QActive *prev, QActive *next) {
void QF_onContextSw(QActive *prev, QActive *next) {
QS_BEGIN_NOCRIT(CONTEXT_SW, 0U) /* no critical section! */
QS_OBJ(prev);
QS_OBJ(next);
QS_END_NOCRIT()
}
#endif /* QXK_ON_CONTEXT_SW */
#endif /* QF_ON_CONTEXT_SW */
/*..........................................................................*/
void QXK_onIdle(void) { /* called with interrupts enabled */

6
examples/arm-cm/dpp_nucleo-l053r8/qxk/gnu/Makefile
View File

@ -1,7 +1,7 @@
##############################################################################
# Product: Makefile for QP/C, DPP on NUCLEO-L053R8, QXK kernel, GNU-ARM
# Last Updated for Version: 7.0.1
# Date of the Last Update: 2022-05-23
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-13
#
# Q u a n t u m L e a P s
# ------------------------
@ -138,7 +138,7 @@ LIBS :=
# defines
DEFINES := \
-DQXK_ON_CONTEXT_SW \
-DQF_ON_CONTEXT_SW \
-DQXK_USE_IRQ_NUM=30 \
-DQXK_USE_IRQ_HANDLER=LCD_IRQHandler

2
examples/arm-cm/dpp_nucleo-l053r8/qxk/iar/dpp-qxk.ewp
View File

@ -2318,7 +2318,7 @@
<option>
<name>CCDefines</name>
<state>Q_SPY</state>
<state>QXK_ON_CONTEXT_SW</state>
<state>QF_ON_CONTEXT_SW</state>
</option>
<option>
<name>CCPreprocFile</name>

6
examples/arm-cm/dpp_nucleo-l053r8/table.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::table.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -64,8 +64,8 @@ static QState Table_paused(Table * const me, QEvt const * const e);
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

2
examples/arm-cm/dpp_nucleo-l152re/dpp.h
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::dpp.h}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later

2
examples/arm-cm/dpp_nucleo-l152re/dpp.qm
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<model version="5.2.2" links="1">
<model version="5.2.4" links="1">
<documentation>Dining Philosopher Problem example</documentation>
<!--${qpc}-->
<framework name="qpc"/>

6
examples/arm-cm/dpp_nucleo-l152re/philo.c
View File

@ -3,7 +3,7 @@
* Model: dpp.qm
* File: ${.::philo.c}
*
* This code has been generated by QM 5.2.2 <www.state-machine.com/qm>.
* This code has been generated by QM 5.2.4 <www.state-machine.com/qm>.
* DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
*
* SPDX-License-Identifier: GPL-3.0-or-later
@ -66,8 +66,8 @@ static QState Philo_eating(Philo * const me, QEvt const * const e);
/*$skip${QP_VERSION} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/
/* Check for the minimum required QP version */
#if (QP_VERSION < 690U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 6.9.0 or higher required
#if (QP_VERSION < 700U) || (QP_VERSION != ((QP_RELEASE^4294967295U) % 0x3E8U))
#error qpc version 7.0.0 or higher required
#endif
/*$endskip${QP_VERSION} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

Some files were not shown because too many files have changed in this diff Show More