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6.3.3

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QL 2018-06-26 16:00:34 -04:00
parent 77be8d176c
commit 76bd2c751a
11 changed files with 2350 additions and 2331 deletions
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2
doxygen/history.dox
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@ -11,7 +11,7 @@ This release fixes the following bugs:
Also, this release demonstrates the new features of QM 4.3.0 in several example models (qpc/examples/ directory).
Finally, this release updates `3rd_party/CMSIS/Include` to the latest version from GitHub.
------------------------------------------------------------------------------
@section qpc_6_3_2 Version 6.3.2, 2018-06-20

4586
doxygen/metrics.dox
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2
examples/arm-cm/dpp_nucleo-l053r8/dpp.h
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@ -73,4 +73,4 @@ extern QActive * const AO_Table;
extern QXThread * const XT_Test2;
#endif /* qxk_h */
#endif /* dpp_h */
#endif /* dpp_h */

3
examples/arm-cm/dpp_nucleo-l053r8/dpp.qm
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@ -365,7 +365,8 @@ $declare${AOs::AO_Table}
extern QXThread * const XT_Test2;
#endif /* qxk_h */
#endif /* dpp_h */</text>
#endif /* dpp_h */
</text>
</file>
<file name="philo.c">
<text>#include &quot;qpc.h&quot;

6
examples/arm-cm/dpp_nucleo-l053r8/qk/bsp.c
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@ -1,7 +1,7 @@
/*****************************************************************************
* Product: DPP example, NUCLEO-L053R8 board, preemptive QK kernel
* Last Updated for Version: 6.1.1
* Date of the Last Update: 2018-02-17
* Last Updated for Version: 6.3.3
* Date of the Last Update: 2018-06-23
*
* Q u a n t u m L e a P s
* ---------------------------
@ -289,7 +289,7 @@ void QK_onIdle(void) { /* called with interrupts enabled */
#elif defined NDEBUG
/* Put the CPU and peripherals to the low-power mode.
* you might need to customize the clock management for your application,
* see the datasheet for your particular Cortex-M3 MCU.
* see the datasheet for your particular Cortex-M MCU.
*/
/* !!!CAUTION!!!
* The WFI instruction stops the CPU clock, which unfortunately disables

10
examples/arm-cm/dpp_nucleo-l053r8/qv/arm/dpp-qv.uvoptx
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@ -118,12 +118,12 @@
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L0xx_64 -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$Flash\STM32L0xx_64.FLM))</Name>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L0xx_64 -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$CMSIS\Flash\STM32L0xx_64.FLM))</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key>
<Name>-U066CFF484951775087074312 -O8431 -SF480 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32L0xx_64.FLM -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$Flash\STM32L0xx_64.FLM)</Name>
<Name>-U066CFF484951775087074312 -O8431 -SF480 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32L0xx_64.FLM -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$CMSIS\Flash\STM32L0xx_64.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -205,6 +205,12 @@
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>

6
examples/arm-cm/dpp_nucleo-l053r8/qv/arm/dpp-qv.uvprojx
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@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>STM32L053R8Tx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L0xx_DFP.1.6.1</PackID>
<PackID>Keil.STM32L0xx_DFP.2.0.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -662,7 +662,7 @@
<TargetCommonOption>
<Device>STM32L053R8Tx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L0xx_DFP.1.6.1</PackID>
<PackID>Keil.STM32L0xx_DFP.2.0.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -1308,7 +1308,7 @@
<TargetCommonOption>
<Device>STM32L053R8Tx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L0xx_DFP.1.6.1</PackID>
<PackID>Keil.STM32L0xx_DFP.2.0.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>

10
examples/arm-cm/dpp_nucleo-l053r8/qv/armclang/dpp-qv.uvoptx
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@ -118,12 +118,12 @@
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L0xx_64 -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$Flash\STM32L0xx_64.FLM))</Name>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L0xx_64 -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$CMSIS\Flash\STM32L0xx_64.FLM))</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key>
<Name>-U066CFF484951775087074312 -O8431 -SF480 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32L0xx_64.FLM -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$Flash\STM32L0xx_64.FLM)</Name>
<Name>-U066CFF484951775087074312 -O8431 -SF480 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32L0xx_64.FLM -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$CMSIS\Flash\STM32L0xx_64.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -205,6 +205,12 @@
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>

6
examples/arm-cm/dpp_nucleo-l053r8/qv/armclang/dpp-qv.uvprojx
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@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>STM32L053R8Tx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L0xx_DFP.1.6.1</PackID>
<PackID>Keil.STM32L0xx_DFP.2.0.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -662,7 +662,7 @@
<TargetCommonOption>
<Device>STM32L053R8Tx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L0xx_DFP.1.6.1</PackID>
<PackID>Keil.STM32L0xx_DFP.2.0.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -1308,7 +1308,7 @@
<TargetCommonOption>
<Device>STM32L053R8Tx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L0xx_DFP.1.6.1</PackID>
<PackID>Keil.STM32L0xx_DFP.2.0.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>

44
examples/arm-cm/dpp_nucleo-l053r8/qv/bsp.c
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@ -1,7 +1,7 @@
/*****************************************************************************
* Product: DPP example, NUCLEO-L053R8 board, cooperative QV kernel
* Last Updated for Version: 5.9.9
* Date of the Last Update: 2017-10-09
* Last Updated for Version: 6.3.3
* Date of the Last Update: 2018-06-23
*
* Q u a n t u m L e a P s
* ---------------------------
@ -28,7 +28,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* Contact information:
* https://state-machine.com
* https://www.state-machine.com
* mailto:info@state-machine.com
*****************************************************************************/
#include "qpc.h"
@ -47,6 +47,7 @@ Q_DEFINE_THIS_FILE
enum KernelAwareISRs {
GPIOPORTA_PRIO = QF_AWARE_ISR_CMSIS_PRI, /* see NOTE00 */
SYSTICK_PRIO,
EXTI0_1_PRIO,
/* ... */
MAX_KERNEL_AWARE_CMSIS_PRI /* keep always last */
};
@ -54,6 +55,7 @@ enum KernelAwareISRs {
Q_ASSERT_COMPILE(MAX_KERNEL_AWARE_CMSIS_PRI <= (0xFF >>(8-__NVIC_PRIO_BITS)));
void SysTick_Handler(void);
void EXTI0_1_IRQHandler(void);
/* Local-scope defines -----------------------------------------------------*/
/* LED pins available on the board (just one user LED LD2--Green on PA.5) */
@ -73,7 +75,8 @@ static uint32_t l_rnd; /* random seed */
static uint8_t const l_SysTick_Handler = 0U;
enum AppRecords { /* application-specific trace records */
PHILO_STAT = QS_USER
PHILO_STAT = QS_USER,
ON_CONTEXT_SW
};
#endif
@ -95,8 +98,8 @@ void SysTick_Handler(void) { /* system clock tick ISR */
}
#endif
//QF_TICK_X(0U, &l_SysTick_Handler); /* process time events for rate 0 */
QACTIVE_POST(the_Ticker0, 0, &l_SysTick_Handler); /* post to Ticker0 */
QF_TICK_X(0U, &l_SysTick_Handler); /* process time events for rate 0 */
//QACTIVE_POST(the_Ticker0, 0, &l_SysTick_Handler); /* post to Ticker0 */
/* get state of the user button */
/* Perform the debouncing of buttons. The algorithm for debouncing
@ -120,6 +123,13 @@ void SysTick_Handler(void) { /* system clock tick ISR */
}
}
}
/*..........................................................................*/
/* interrupt handler for testing preemptions in QXK */
void EXTI0_1_IRQHandler(void) {
static QEvt const testEvt = { TEST_SIG, 0U, 0U };
QACTIVE_POST(AO_Table, &testEvt, (void *)0);
}
/* BSP functions ===========================================================*/
void BSP_init(void) {
@ -142,7 +152,7 @@ void BSP_init(void) {
/* enable GPIOC clock port for the Button B1 */
RCC->IOPENR |= (1U << 2);
/* Configure Button (PC.13) pins as input, no pull-up, pull-down */
/* configure Button (PC.13) pins as input, no pull-up, pull-down */
GPIOC->MODER &= ~(3U << 2*13);
GPIOC->OSPEEDR &= ~(3U << 2*13);
GPIOC->OSPEEDR |= (1U << 2*13);
@ -151,10 +161,12 @@ void BSP_init(void) {
BSP_randomSeed(1234U); /* seed the random number generator */
/* initialize the QS software tracing... */
if (QS_INIT((void *)0) == 0) {
if (QS_INIT((void *)0) == 0U) {
Q_ERROR();
}
QS_OBJ_DICTIONARY(&l_SysTick_Handler);
QS_USR_DICTIONARY(PHILO_STAT);
QS_USR_DICTIONARY(ON_CONTEXT_SW);
}
/*..........................................................................*/
void BSP_displayPhilStat(uint8_t n, char const *stat) {
@ -224,9 +236,11 @@ void QF_onStartup(void) {
* DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
*/
NVIC_SetPriority(SysTick_IRQn, SYSTICK_PRIO);
NVIC_SetPriority(EXTI0_1_IRQn, EXTI0_1_PRIO);
/* ... */
/* enable IRQs... */
NVIC_EnableIRQ(EXTI0_1_IRQn);
}
/*..........................................................................*/
void QF_onCleanup(void) {
@ -330,17 +344,8 @@ uint8_t QS_onStartup(void const *arg) {
QS_tickTime_ = QS_tickPeriod_; /* to start the timestamp at zero */
/* setup the QS filters... */
QS_FILTER_ON(QS_QEP_STATE_ENTRY);
QS_FILTER_ON(QS_QEP_STATE_EXIT);
QS_FILTER_ON(QS_QEP_STATE_INIT);
QS_FILTER_ON(QS_QEP_INIT_TRAN);
QS_FILTER_ON(QS_QEP_INTERN_TRAN);
QS_FILTER_ON(QS_QEP_TRAN);
QS_FILTER_ON(QS_QEP_IGNORED);
QS_FILTER_ON(QS_QEP_DISPATCH);
QS_FILTER_ON(QS_QEP_UNHANDLED);
QS_FILTER_ON(PHILO_STAT);
QS_FILTER_ON(QS_SM_RECORDS);
QS_FILTER_ON(QS_UA_RECORDS);
return (uint8_t)1; /* return success */
}
@ -370,6 +375,7 @@ void QS_onFlush(void) {
}
QF_INT_ENABLE();
}
#endif /* Q_SPY */
/*--------------------------------------------------------------------------*/

6
examples/arm-cm/dpp_nucleo-l053r8/qxk/bsp.c
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@ -1,7 +1,7 @@
/*****************************************************************************
* Product: DPP example, NUCLEO-L053R8 board, preemptive QXK kernel
* Last Updated for Version: 6.1.1
* Date of the Last Update: 2018-02-15
* Last Updated for Version: 6.3.3
* Date of the Last Update: 2018-06-23
*
* Q u a n t u m L e a P s
* ---------------------------
@ -289,7 +289,7 @@ void QXK_onIdle(void) { /* called with interrupts enabled */
#elif defined NDEBUG
/* Put the CPU and peripherals to the low-power mode.
* you might need to customize the clock management for your application,
* see the datasheet for your particular Cortex-M3 MCU.
* see the datasheet for your particular Cortex-M MCU.
*/
/* !!!CAUTION!!!
* The WFI instruction stops the CPU clock, which unfortunately disables