/***************************************************************************** * Product: "Dining Philosophers Problem" example, preemptive QK kernel * Last Updated for Version: 5.1.0 * Date of the Last Update: Sep 19, 2013 * * Q u a n t u m L e a P s * --------------------------- * innovating embedded systems * * Copyright (C) 2002-2013 Quantum Leaps, LLC. All rights reserved. * * This program is open source software: you can redistribute it and/or * modify it under the terms of the GNU General Public License as published * by the Free Software Foundation, either version 2 of the License, or * (at your option) any later version. * * Alternatively, this program may be distributed and modified under the * terms of Quantum Leaps commercial licenses, which expressly supersede * the GNU General Public License and are specifically designed for * licensees interested in retaining the proprietary status of their code. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . * * Contact information: * Quantum Leaps Web sites: http://www.quantum-leaps.com * http://www.state-machine.com * e-mail: info@quantum-leaps.com *****************************************************************************/ #include "qp_port.h" #include "dpp.h" #include "bsp.h" #include "lm3s_cmsis.h" #include "display96x16x1.h" Q_DEFINE_THIS_FILE /*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! * Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority(). * DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE! */ enum KernelUnawareISRs { /* see NOTE00 */ /* ... */ MAX_KERNEL_UNAWARE_CMSIS_PRI /* keep always last */ }; /* "kernel-unaware" interrupts can't overlap "kernel-aware" interrutps */ Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI <= QF_AWARE_ISR_CMSIS_PRI); enum KernelAwareISRs { GPIOPORTA_PRIO = QF_AWARE_ISR_CMSIS_PRI, /* see NOTE00 */ SYSTICK_PRIO, /* ... */ MAX_KERNEL_AWARE_CMSIS_PRI /* keep always last */ }; /* "kernel-aware" interrutps should not overlap the PendSV priority */ Q_ASSERT_COMPILE(MAX_KERNEL_AWARE_CMSIS_PRI <= (0xFF >>(8-__NVIC_PRIO_BITS))); /* ISRs defined in this BSP ------------------------------------------------*/ void SysTick_Handler(void); void GPIOPortA_IRQHandler(void); void assert_failed(char const *file, int line); /* Local-scope objects -----------------------------------------------------*/ static unsigned l_rnd; /* random seed */ #define PUSH_BUTTON (1U << 4) #define USER_LED (1U << 5) #ifdef Q_SPY QSTimeCtr QS_tickTime_; QSTimeCtr QS_tickPeriod_; static uint8_t l_SysTick_Handler; static uint8_t l_GPIOPortA_IRQHandler; #define UART_BAUD_RATE 115200U #define UART_TXFIFO_DEPTH 16U #define UART_FR_TXFE 0x00000080U enum AppRecords { /* application-specific trace records */ PHILO_STAT = QS_USER }; #endif /*..........................................................................*/ void SysTick_Handler(void) { static uint32_t btn_debounced = PUSH_BUTTON; static uint8_t debounce_state = 0U; uint32_t btn; QK_ISR_ENTRY(); /* infrom QK about entering an ISR */ #ifdef Q_SPY { uint32_t dummy = SysTick->CTRL; /* clear SysTick_CTRL_COUNTFLAG */ QS_tickTime_ += QS_tickPeriod_; /* account for the clock rollover */ } #endif QF_TICK(&l_SysTick_Handler); /* process all armed time events */ /* debounce the USER button... */ btn = GPIOC->DATA_Bits[PUSH_BUTTON]; /* read the push btn */ switch (debounce_state) { case 0: if (btn != btn_debounced) { debounce_state = 1U; /* transition to the next state */ } break; case 1: if (btn != btn_debounced) { debounce_state = 2U; /* transition to the next state */ } else { debounce_state = 0U; /* transition back to state 0 */ } break; case 2: if (btn != btn_debounced) { debounce_state = 3U; /* transition to the next state */ } else { debounce_state = 0U; /* transition back to state 0 */ } break; case 3: if (btn != btn_debounced) { btn_debounced = btn; /* save the debounced button value */ if (btn == 0U) { /* is the button depressed? */ static QEvt const pauseEvt = { PAUSE_SIG, 0U, 0U}; QF_PUBLISH(&pauseEvt, &l_SysTick_Handler); } else { static QEvt const pauseEvt = { PAUSE_SIG, 0U, 0U}; QF_PUBLISH(&pauseEvt, &l_SysTick_Handler); } } debounce_state = 0U; /* transition back to state 0 */ break; } QK_ISR_EXIT(); /* infrom QK about exiting an ISR */ } /*..........................................................................*/ void GPIOPortA_IRQHandler(void) { QK_ISR_ENTRY(); /* infrom QK about entering an ISR */ QACTIVE_POST(AO_Table, Q_NEW(QEvt, MAX_PUB_SIG), /* for testing... */ &l_GPIOPortA_IRQHandler); QK_ISR_EXIT(); /* infrom QK about exiting an ISR */ } /*..........................................................................*/ void BSP_init(void) { /* set the system clock as specified in lm3s_config.h (20MHz from PLL) */ SystemInit(); /* enable clock to the peripherals used by the application */ SYSCTL->RCGC2 |= (1 << 0) | (1 << 2); /* enable clock to GPIOA & C */ __NOP(); /* wait after enabling clocks */ __NOP(); __NOP(); /* configure the LED and push button */ GPIOC->DIR |= USER_LED; /* set direction: output */ GPIOC->DEN |= USER_LED; /* digital enable */ GPIOC->DATA_Bits[USER_LED] = 0; /* turn the User LED off */ GPIOC->DIR &= ~PUSH_BUTTON; /* set direction: input */ GPIOC->DEN |= PUSH_BUTTON; /* digital enable */ Display96x16x1Init(1); /* initialize the OLED display */ Display96x16x1StringDraw("Dining Philos", 0, 0); Display96x16x1StringDraw("0 ,1 ,2 ,3 ,4", 0, 1); BSP_randomSeed(1234U); if (QS_INIT((void *)0) == 0) { /* initialize the QS software tracing */ Q_ERROR(); } QS_RESET(); QS_OBJ_DICTIONARY(&l_SysTick_Handler); QS_OBJ_DICTIONARY(&l_GPIOPortA_IRQHandler); } /*..........................................................................*/ void BSP_displayPhilStat(uint8_t n, char_t const *stat) { char str[2]; str[0] = stat[0]; str[1] = '\0'; Display96x16x1StringDraw(str, (3*6*n + 6), 1); QS_BEGIN(PHILO_STAT, AO_Philo[n]) /* application-specific record begin */ QS_U8(1, n); /* Philosopher number */ QS_STR(stat); /* Philosopher status */ QS_END() } /*..........................................................................*/ void BSP_displayPaused(uint8_t paused) { Display96x16x1StringDraw(paused ? "P" : " ", 15*6, 0); } /*..........................................................................*/ uint32_t BSP_random(void) { /* a very cheap pseudo-random-number generator */ /* "Super-Duper" Linear Congruential Generator (LCG) * LCG(2^32, 3*7*11*13*23, 0, seed) */ l_rnd = l_rnd * (3*7*11*13*23); return l_rnd >> 8; } /*..........................................................................*/ void BSP_randomSeed(uint32_t seed) { l_rnd = seed; } /*..........................................................................*/ void BSP_terminate(int16_t result) { (void)result; } /*..........................................................................*/ void QF_onStartup(void) { /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */ SysTick_Config(SystemFrequency / BSP_TICKS_PER_SEC); /* assing all priority bits for preemption-prio. and none to sub-prio. */ NVIC_SetPriorityGrouping(0U); /* set priorities of ALL ISRs used in the system, see NOTE00 * * !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! * Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority(). * DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE! */ NVIC_SetPriority(SysTick_IRQn, SYSTICK_PRIO); NVIC_SetPriority(GPIOPortA_IRQn, GPIOPORTA_PRIO); /* ... */ /* enable IRQs... */ NVIC_EnableIRQ(GPIOPortA_IRQn); } /*..........................................................................*/ void QF_onCleanup(void) { } /*..........................................................................*/ void QK_onIdle(void) { /* toggle the User LED on and then off, see NOTE01 */ QF_INT_DISABLE(); GPIOC->DATA_Bits[USER_LED] = USER_LED; /* turn the User LED on */ GPIOC->DATA_Bits[USER_LED] = 0; /* turn the User LED off */ QF_INT_ENABLE(); #ifdef Q_SPY if ((UART0->FR & UART_FR_TXFE) != 0) { /* TX done? */ uint16_t fifo = UART_TXFIFO_DEPTH; /* max bytes we can accept */ uint8_t const *block; QF_INT_DISABLE(); block = QS_getBlock(&fifo); /* try to get next block to transmit */ QF_INT_ENABLE(); while (fifo-- != 0) { /* any bytes in the block? */ UART0->DR = *block++; /* put into the FIFO */ } } #elif defined NDEBUG /* Put the CPU and peripherals to the low-power mode. * you might need to customize the clock management for your application, * see the datasheet for your particular Cortex-M3 MCU. */ __WFI(); /* Wait-For-Interrupt */ #endif } /*..........................................................................*/ void Q_onAssert(char const Q_ROM * const Q_ROM_VAR file, int_t line) { (void)file; /* avoid compiler warning */ (void)line; /* avoid compiler warning */ QF_INT_DISABLE(); /* make sure that all interrupts are disabled */ for (;;) { /* NOTE: replace the loop with reset for final version */ } } /*..........................................................................*/ /* error routine that is called if the CMSIS library encounters an error */ void assert_failed(char const *file, int line) { Q_onAssert(file, line); } /*--------------------------------------------------------------------------*/ #ifdef Q_SPY /*..........................................................................*/ uint8_t QS_onStartup(void const *arg) { static uint8_t qsBuf[2*1024]; /* buffer for Quantum Spy */ uint32_t tmp; QS_initBuf(qsBuf, sizeof(qsBuf)); /* enable the peripherals used by the UART0 */ SYSCTL->RCGC1 |= (1 << 0); /* enable clock to UART0 */ SYSCTL->RCGC2 |= (1 << 0); /* enable clock to GPIOA */ __NOP(); /* wait after enabling clocks */ __NOP(); __NOP(); /* configure UART0 pins for UART operation */ tmp = (1 << 0) | (1 << 1); GPIOA->DIR &= ~tmp; GPIOA->AFSEL |= tmp; GPIOA->DR2R |= tmp; /* set 2mA drive, DR4R and DR8R are cleared */ GPIOA->SLR &= ~tmp; GPIOA->ODR &= ~tmp; GPIOA->PUR &= ~tmp; GPIOA->PDR &= ~tmp; GPIOA->DEN |= tmp; /* configure the UART for the desired baud rate, 8-N-1 operation */ tmp = (((SystemFrequency * 8) / UART_BAUD_RATE) + 1) / 2; UART0->IBRD = tmp / 64; UART0->FBRD = tmp % 64; UART0->LCRH = 0x60; /* configure 8-N-1 operation */ UART0->LCRH |= 0x10; UART0->CTL |= (1 << 0) | (1 << 8) | (1 << 9); QS_tickPeriod_ = SystemFrequency / BSP_TICKS_PER_SEC; QS_tickTime_ = QS_tickPeriod_; /* to start the timestamp at zero */ /* setup the QS filters... */ QS_FILTER_ON(QS_ALL_RECORDS); // QS_FILTER_OFF(QS_QEP_STATE_EMPTY); // QS_FILTER_OFF(QS_QEP_STATE_ENTRY); // QS_FILTER_OFF(QS_QEP_STATE_EXIT); // QS_FILTER_OFF(QS_QEP_STATE_INIT); // QS_FILTER_OFF(QS_QEP_INIT_TRAN); // QS_FILTER_OFF(QS_QEP_INTERN_TRAN); // QS_FILTER_OFF(QS_QEP_TRAN); // QS_FILTER_OFF(QS_QEP_IGNORED); // QS_FILTER_OFF(QS_QF_ACTIVE_ADD); // QS_FILTER_OFF(QS_QF_ACTIVE_REMOVE); // QS_FILTER_OFF(QS_QF_ACTIVE_SUBSCRIBE); // QS_FILTER_OFF(QS_QF_ACTIVE_UNSUBSCRIBE); // QS_FILTER_OFF(QS_QF_ACTIVE_POST_FIFO); // QS_FILTER_OFF(QS_QF_ACTIVE_POST_LIFO); // QS_FILTER_OFF(QS_QF_ACTIVE_GET); // QS_FILTER_OFF(QS_QF_ACTIVE_GET_LAST); // QS_FILTER_OFF(QS_QF_EQUEUE_INIT); // QS_FILTER_OFF(QS_QF_EQUEUE_POST_FIFO); // QS_FILTER_OFF(QS_QF_EQUEUE_POST_LIFO); // QS_FILTER_OFF(QS_QF_EQUEUE_GET); // QS_FILTER_OFF(QS_QF_EQUEUE_GET_LAST); // QS_FILTER_OFF(QS_QF_MPOOL_INIT); // QS_FILTER_OFF(QS_QF_MPOOL_GET); // QS_FILTER_OFF(QS_QF_MPOOL_PUT); // QS_FILTER_OFF(QS_QF_PUBLISH); // QS_FILTER_OFF(QS_QF_NEW); // QS_FILTER_OFF(QS_QF_GC_ATTEMPT); // QS_FILTER_OFF(QS_QF_GC); // QS_FILTER_OFF(QS_QF_TICK); // QS_FILTER_OFF(QS_QF_TIMEEVT_ARM); // QS_FILTER_OFF(QS_QF_TIMEEVT_AUTO_DISARM); // QS_FILTER_OFF(QS_QF_TIMEEVT_DISARM_ATTEMPT); // QS_FILTER_OFF(QS_QF_TIMEEVT_DISARM); // QS_FILTER_OFF(QS_QF_TIMEEVT_REARM); // QS_FILTER_OFF(QS_QF_TIMEEVT_POST); QS_FILTER_OFF(QS_QF_CRIT_ENTRY); QS_FILTER_OFF(QS_QF_CRIT_EXIT); QS_FILTER_OFF(QS_QF_ISR_ENTRY); QS_FILTER_OFF(QS_QF_ISR_EXIT); return (uint8_t)1; /* return success */ } /*..........................................................................*/ void QS_onCleanup(void) { } /*..........................................................................*/ QSTimeCtr QS_onGetTime(void) { /* invoked with interrupts locked */ if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) { /* not set? */ return QS_tickTime_ - (QSTimeCtr)SysTick->VAL; } else { /* the rollover occured, but the SysTick_ISR did not run yet */ return QS_tickTime_ + QS_tickPeriod_ - (QSTimeCtr)SysTick->VAL; } } /*..........................................................................*/ void QS_onFlush(void) { uint16_t fifo = UART_TXFIFO_DEPTH; /* Tx FIFO depth */ uint8_t const *block; QF_INT_DISABLE(); while ((block = QS_getBlock(&fifo)) != (uint8_t *)0) { QF_INT_ENABLE(); /* busy-wait until TX FIFO empty */ while ((UART0->FR & UART_FR_TXFE) == 0) { } while (fifo-- != 0) { /* any bytes in the block? */ UART0->DR = *block++; /* put into the TX FIFO */ } fifo = UART_TXFIFO_DEPTH; /* re-load the Tx FIFO depth */ QF_INT_DISABLE(); } QF_INT_ENABLE(); } #endif /* Q_SPY */ /*--------------------------------------------------------------------------*/ /***************************************************************************** * NOTE00: * The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest * ISR priority that is disabled by the QF framework. The value is suitable * for the NVIC_SetPriority() CMSIS function. * * Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e., * with the numerical values of priorities equal or higher than * QF_AWARE_ISR_CMSIS_PRI) are allowed to call the QK_ISR_ENTRY/QK_ISR_ENTRY * macros or any other QF/QK services. These ISRs are "QF-aware". * * Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority * level (i.e., with the numerical values of priorities less than * QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel. * Such "QF-unaware" ISRs cannot call any QF/QK services. In particular they * can NOT call the macros QK_ISR_ENTRY/QK_ISR_ENTRY. The only mechanism * by which a "QF-unaware" ISR can communicate with the QF framework is by * triggering a "QF-aware" ISR, which can post/publish events. * * NOTE01: * The User LED is used to visualize the idle loop activity. The brightness * of the LED is proportional to the frequency of invcations of the idle loop. * Please note that the LED is toggled with interrupts locked, so no interrupt * execution time contributes to the brightness of the User LED. */