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126 lines
4.0 KiB
C
126 lines
4.0 KiB
C
/**
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* @file
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* @brief QV/C port to ARM Cortex-M, ARM-KEIL toolset
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* @cond
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******************************************************************************
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* Last updated for version 6.8.0
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* Last updated on 2020-01-25
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*
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* Q u a n t u m L e a P s
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* ------------------------
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* Modern Embedded Software
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*
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* Copyright (C) 2005-2020 Quantum Leaps, LLC. All rights reserved.
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*
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* This program is open source software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Alternatively, this program may be distributed and modified under the
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* terms of Quantum Leaps commercial licenses, which expressly supersede
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* the GNU General Public License and are specifically designed for
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* licensees interested in retaining the proprietary status of their code.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <www.gnu.org/licenses/>.
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*
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* Contact information:
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* <www.state-machine.com/licensing>
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* <info@state-machine.com>
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******************************************************************************
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* @endcond
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*/
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/* This QV port is part of the interanl QP implementation */
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#define QP_IMPL 1U
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#include "qf_port.h"
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#if (__TARGET_ARCH_THUMB == 3) /* Cortex-M0/M0+/M1(v6-M, v6S-M)? */
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/* hand-optimized fast LOG2 in assembly for Cortex-M0/M0+/M1(v6-M, v6S-M) */
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__asm uint_fast8_t QF_qlog2(uint32_t x) {
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MOVS r1,#0
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#if (QF_MAX_ACTIVE > 16)
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LSRS r2,r0,#16
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BEQ.N QF_qlog2_1
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MOVS r1,#16
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MOVS r0,r2
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QF_qlog2_1
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#endif
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#if (QF_MAX_ACTIVE > 8)
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LSRS r2,r0,#8
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BEQ.N QF_qlog2_2
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ADDS r1,r1,#8
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MOVS r0,r2
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QF_qlog2_2
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#endif
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LSRS r2,r0,#4
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BEQ.N QF_qlog2_3
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ADDS r1,r1,#4
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MOVS r0,r2
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QF_qlog2_3
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LDR r2,=QF_qlog2_LUT
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LDRB r0,[r2,r0]
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ADDS r0,r1,r0
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BX lr
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ALIGN
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QF_qlog2_LUT
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DCB 0, 1, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4
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}
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#else /* NOT Cortex-M0/M0+/M1(v6-M, v6S-M)? */
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#define SCnSCB_ICTR ((uint32_t volatile *)0xE000E004)
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#define SCB_SYSPRI ((uint32_t volatile *)0xE000ED14)
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#define NVIC_IP ((uint32_t volatile *)0xE000E400)
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/*
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* Initialize the exception priorities and IRQ priorities to safe values.
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*
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* Description:
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* On Cortex-M3/M4/M7, this QV port disables interrupts by means of the
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* BASEPRI register. However, this method cannot disable interrupt
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* priority zero, which is the default for all interrupts out of reset.
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* The following code changes the SysTick priority and all IRQ priorities
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* to the safe value QF_BASEPRI, wich the QF critical section can disable.
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* This avoids breaching of the QF critical sections in case the
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* application programmer forgets to explicitly set priorities of all
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* "kernel aware" interrupts.
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*
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* The interrupt priorities established in QV_init() can be later
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* changed by the application-level code.
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*/
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void QV_init(void) {
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uint32_t n;
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/* set exception priorities to QF_BASEPRI...
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* SCB_SYSPRI1: Usage-fault, Bus-fault, Memory-fault
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*/
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SCB_SYSPRI[1] |= (QF_BASEPRI << 16) | (QF_BASEPRI << 8) | QF_BASEPRI;
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/* SCB_SYSPRI2: SVCall */
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SCB_SYSPRI[2] |= (QF_BASEPRI << 24);
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/* SCB_SYSPRI3: SysTick, PendSV, Debug */
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SCB_SYSPRI[3] |= (QF_BASEPRI << 24) | (QF_BASEPRI << 16) | QF_BASEPRI;
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/* set all implemented IRQ priories to QF_BASEPRI... */
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n = 8U + ((*SCnSCB_ICTR & 0x7U) << 3); /* (# NVIC_PRIO registers)/4 */
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do {
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--n;
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NVIC_IP[n] = (QF_BASEPRI << 24) | (QF_BASEPRI << 16)
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| (QF_BASEPRI << 8) | QF_BASEPRI;
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} while (n != 0);
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}
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#endif /* NOT Cortex-M0/M0+/M1(v6-M, v6S-M)? */
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