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155 lines
6.4 KiB
C
155 lines
6.4 KiB
C
/**
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* @file
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* @brief QF/C port to Cortex-M, cooperative QV kernel, GNU-ARM toolset
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* @cond
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******************************************************************************
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* Last updated for version 6.3.8
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* Last updated on 2019-01-10
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*
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* Q u a n t u m L e a P s
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* ------------------------
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* Modern Embedded Software
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*
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* Copyright (C) 2005-2019 Quantum Leaps, LLC. All rights reserved.
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*
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* This program is open source software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Alternatively, this program may be distributed and modified under the
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* terms of Quantum Leaps commercial licenses, which expressly supersede
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* the GNU General Public License and are specifically designed for
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* licensees interested in retaining the proprietary status of their code.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <www.gnu.org/licenses/>.
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*
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* Contact information:
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* <www.state-machine.com/licensing>
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* <info@state-machine.com>
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******************************************************************************
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* @endcond
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*/
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#ifndef QF_PORT_H
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#define QF_PORT_H
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/* The maximum number of system clock tick rates */
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#define QF_MAX_TICK_RATE 2U
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/* QF interrupt disable/enable and log2()... */
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#if (__ARM_ARCH == 6) /* Cortex-M0/M0+/M1(v6-M, v6S-M)? */
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/* The maximum number of active objects in the application, see NOTE1 */
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#define QF_MAX_ACTIVE 16U
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/* Cortex-M0/M0+/M1(v6-M, v6S-M) interrupt disabling policy, see NOTE2 */
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#define QF_INT_DISABLE() __asm volatile ("cpsid i")
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#define QF_INT_ENABLE() __asm volatile ("cpsie i")
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/* QF critical section entry/exit (unconditional interrupt disabling) */
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/*#define QF_CRIT_STAT_TYPE not defined */
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#define QF_CRIT_ENTRY(dummy) QF_INT_DISABLE()
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#define QF_CRIT_EXIT(dummy) QF_INT_ENABLE()
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/* CMSIS threshold for "QF-aware" interrupts, see NOTE2 and NOTE4 */
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#define QF_AWARE_ISR_CMSIS_PRI 0
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/* hand-optimized LOG2 in assembly for Cortex-M0/M0+/M1(v6-M, v6S-M) */
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#define QF_LOG2(n_) QF_qlog2((uint32_t)(n_))
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#else /* Cortex-M3/M4/M7 */
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/* The maximum number of active objects in the application, see NOTE1 */
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#define QF_MAX_ACTIVE 32U
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/* Cortex-M3/M4/M7 alternative interrupt disabling with PRIMASK */
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#define QF_PRIMASK_DISABLE() __asm volatile ("cpsid i")
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#define QF_PRIMASK_ENABLE() __asm volatile ("cpsie i")
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/* Cortex-M3/M4/M7 interrupt disabling policy, see NOTE3 and NOTE4 */
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#define QF_INT_DISABLE() __asm volatile (\
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"cpsid i\n" "msr BASEPRI,%0\n" "cpsie i" :: "r" (QF_BASEPRI) : )
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#define QF_INT_ENABLE() __asm volatile (\
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"msr BASEPRI,%0" :: "r" (0) : )
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/* QF critical section entry/exit (unconditional interrupt disabling) */
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/*#define QF_CRIT_STAT_TYPE not defined */
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#define QF_CRIT_ENTRY(dummy) QF_INT_DISABLE()
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#define QF_CRIT_EXIT(dummy) QF_INT_ENABLE()
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/* BASEPRI threshold for "QF-aware" interrupts, see NOTE3 */
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#define QF_BASEPRI 0x3F
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/* CMSIS threshold for "QF-aware" interrupts, see NOTE5 */
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#define QF_AWARE_ISR_CMSIS_PRI (QF_BASEPRI >> (8 - __NVIC_PRIO_BITS))
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/* Cortex-M3/M4/M7 provide the CLZ instruction for fast LOG2 */
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#define QF_LOG2(n_) ((uint_fast8_t)(32U - __builtin_clz((unsigned)(n_))))
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#endif
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#define QF_CRIT_EXIT_NOP() __asm volatile ("isb")
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#include "qep_port.h" /* QEP port */
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#if (__ARM_ARCH == 6) /* Cortex-M0/M0+/M1(v6-M, v6S-M)? */
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/* hand-optimized quick LOG2 in assembly */
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uint_fast8_t QF_qlog2(uint32_t x);
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#endif /* Cortex-M0/M0+/M1(v6-M, v6S-M) */
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#include "qv_port.h" /* QV cooperative kernel port */
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#include "qf.h" /* QF platform-independent public interface */
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/*****************************************************************************
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* NOTE1:
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* The maximum number of active objects QF_MAX_ACTIVE can be increased
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* up to 64U, if necessary. Here it is set to a lower level to save some RAM.
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*
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* NOTE2:
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* On Cortex-M0/M0+/M1 (architecture v6-M, v6S-M), the interrupt disabling
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* policy uses the PRIMASK register to disable interrupts globally. The
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* QF_AWARE_ISR_CMSIS_PRI level is zero, meaning that all interrupts are
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* "QF-aware".
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*
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* NOTE3:
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* On Cortex-M3/M4/M7, the interrupt disable/enable policy uses the BASEPRI
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* register (which is not implemented in Cortex-M0/M0+/M1) to disable
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* interrupts only with priority lower than the threshold specified by the
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* QF_BASEPRI macro. The interrupts with priorities above QF_BASEPRI (i.e.,
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* with numerical priority values lower than QF_BASEPRI) are NOT disabled in
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* this method. These free-running interrupts have very low ("zero") latency,
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* but they are not allowed to call any QF services, because QF is unaware
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* of them ("QF-unaware" interrutps). Consequently, only interrupts with
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* numerical values of priorities eqal to or higher than QF_BASEPRI
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* ("QF-aware" interrupts ), can call QF services.
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*
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* NOTE4:
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* The QF_AWARE_ISR_CMSIS_PRI macro is useful as an offset for enumerating
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* the "QF-aware" interrupt priorities in the applications, whereas the
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* numerical values of the "QF-aware" interrupts must be greater or equal to
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* QF_AWARE_ISR_CMSIS_PRI. The values based on QF_AWARE_ISR_CMSIS_PRI can be
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* passed directly to the CMSIS function NVIC_SetPriority(), which shifts
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* them by (8 - __NVIC_PRIO_BITS) into the correct bit position, while
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* __NVIC_PRIO_BITS is the CMSIS macro defining the number of implemented
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* priority bits in the NVIC. Please note that the macro QF_AWARE_ISR_CMSIS_PRI
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* is intended only for applications and is not used inside the QF port, which
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* remains generic and not dependent on the number of implemented priority bits
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* implemented in the NVIC.
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*
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* NOTE5:
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* The selective disabling of "QF-aware" interrupts with the BASEPRI register
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* has a problem on ARM Cortex-M7 core r0p1 (see ARM-EPM-064408, errata
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* 837070). The workaround recommended by ARM is to surround MSR BASEPRI with
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* the CPSID i/CPSIE i pair, which is implemented in the QF_INT_DISABLE()
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* macro. This workaround works also for Cortex-M3/M4 cores.
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*/
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#endif /* QF_PORT_H */
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