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132 lines
4.6 KiB
C
132 lines
4.6 KiB
C
/*============================================================================
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* QP/C Real-Time Embedded Framework (RTEF)
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* Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial
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*
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* This software is dual-licensed under the terms of the open source GNU
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* General Public License version 3 (or any later version), or alternatively,
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* under the terms of one of the closed source Quantum Leaps commercial
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* licenses.
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*
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* The terms of the open source GNU General Public License version 3
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* can be found at: <www.gnu.org/licenses/gpl-3.0>
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*
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* The terms of the closed source Quantum Leaps commercial licenses
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* can be found at: <www.state-machine.com/licensing>
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*
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* Redistributions in source code must retain this top-level comment block.
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* Plagiarizing this software to sidestep the license obligations is illegal.
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*
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* Contact information:
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* <www.state-machine.com>
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* <info@state-machine.com>
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============================================================================*/
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/*!
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* @date Last updated on: 2022-12-18
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* @version Last updated for: @ref qpc_7_2_0
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*
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* @file
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* @brief QV/C port to ARM Cortex-M, ARM-CLANG toolset
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*/
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/* This QV port is part of the internal QP implementation */
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#define QP_IMPL 1U
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#include "qf_port.h"
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#define SCnSCB_ICTR ((uint32_t volatile *)0xE000E004U)
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#define SCB_SYSPRI ((uint32_t volatile *)0xE000ED14U)
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#define NVIC_IP ((uint32_t volatile *)0xE000E400U)
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#define FPU_FPCCR *((uint32_t volatile *)0xE000EF34U)
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/*..........................................................................*/
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/*
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* Initialize the exception priorities and IRQ priorities to safe values.
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*
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* Description:
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* On ARMv7-M or higher, this QK port disables interrupts by means of the
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* BASEPRI register. However, this method cannot disable interrupt
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* priority zero, which is the default for all interrupts out of reset.
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* The following code changes the SysTick priority and all IRQ priorities
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* to the safe value QF_BASEPRI, which the QF critical section can disable.
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* This avoids breaching of the QF critical sections in case the
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* application programmer forgets to explicitly set priorities of all
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* "kernel aware" interrupts.
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*
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* The interrupt priorities established in QV_init() can be later
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* changed by the application-level code.
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*/
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void QV_init(void) {
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#if (__ARM_ARCH != 6) /*--------- if ARMv7-M and higher... */
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/* set exception priorities to QF_BASEPRI...
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* SCB_SYSPRI1: Usage-fault, Bus-fault, Memory-fault
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*/
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SCB_SYSPRI[1] = (SCB_SYSPRI[1]
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| (QF_BASEPRI << 16U) | (QF_BASEPRI << 8U) | QF_BASEPRI);
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/* SCB_SYSPRI2: SVCall */
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SCB_SYSPRI[2] = (SCB_SYSPRI[2] | (QF_BASEPRI << 24U));
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/* SCB_SYSPRI3: SysTick, PendSV, Debug */
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SCB_SYSPRI[3] = (SCB_SYSPRI[3]
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| (QF_BASEPRI << 24U) | (QF_BASEPRI << 16U) | QF_BASEPRI);
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/* set all implemented IRQ priories to QF_BASEPRI... */
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uint8_t nprio = (8U + ((*SCnSCB_ICTR & 0x7U) << 3U)) * 4U;
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for (uint8_t n = 0U; n < nprio; ++n) {
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NVIC_IP[n] = QF_BASEPRI;
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}
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#endif /*--------- ARMv7-M or higher */
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/* SCB_SYSPRI3: PendSV set to priority 0xFF (lowest) */
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SCB_SYSPRI[3] = (SCB_SYSPRI[3] | (0xFFU << 16U));
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#if (__ARM_FP != 0) /*--------- if VFP available... */
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/* configure the FPU for QK */
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FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
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| (1U << 31U); /* lazy stacking (LSPEN) */
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#endif /*--------- VFP available */
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}
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/*==========================================================================*/
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#if (__ARM_ARCH == 6) /* if ARMv6-M... */
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/* hand-optimized quick LOG2 in assembly (no CLZ instruction in ARMv6-M) */
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__attribute__ ((naked))
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uint_fast8_t QF_qlog2(uint32_t x) {
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__asm volatile (
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" MOVS r1,#0 \n"
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#if (QF_MAX_ACTIVE > 16U)
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" LSRS r2,r0,#16 \n"
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" BEQ QF_qlog2_1 \n"
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" MOVS r1,#16 \n"
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" MOVS r0,r2 \n"
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"QF_qlog2_1: \n"
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#endif
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#if (QF_MAX_ACTIVE > 8U)
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" LSRS r2,r0,#8 \n"
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" BEQ QF_qlog2_2 \n"
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" ADDS r1, r1,#8 \n"
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" MOVS r0, r2 \n"
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"QF_qlog2_2: \n"
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#endif
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" LSRS r2,r0,#4 \n"
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" BEQ QF_qlog2_3 \n"
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" ADDS r1,r1,#4 \n"
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" MOV r0,r2 \n"
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"QF_qlog2_3: \n"
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" LDR r2,=QF_qlog2_LUT \n"
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" LDRB r0,[r2,r0] \n"
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" ADDS r0,r1,r0 \n"
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" BX lr \n"
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" .align \n"
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"QF_qlog2_LUT: \n"
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" .byte 0, 1, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4"
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);
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}
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#endif /* ARMv6-M */
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