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132 lines
5.4 KiB
C
132 lines
5.4 KiB
C
/**
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* @file
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* @brief QF/C port to Cortex-M, cooperative QV kernel, ARM-KEIL toolset
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* @cond
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******************************************************************************
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* Last Updated for Version: 5.7.1
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* Date of the Last Update: 2016-09-18
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*
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* Q u a n t u m L e a P s
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* ---------------------------
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* innovating embedded systems
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*
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* Copyright (C) Quantum Leaps, LLC. All rights reserved.
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*
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* This program is open source software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Alternatively, this program may be distributed and modified under the
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* terms of Quantum Leaps commercial licenses, which expressly supersede
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* the GNU General Public License and are specifically designed for
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* licensees interested in retaining the proprietary status of their code.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Contact information:
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* http://www.state-machine.com
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* mailto:info@state-machine.com
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******************************************************************************
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* @endcond
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*/
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#ifndef qf_port_h
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#define qf_port_h
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/* The maximum number of active objects in the application, see NOTE1 */
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#define QF_MAX_ACTIVE 32
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/* The maximum number of system clock tick rates */
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#define QF_MAX_TICK_RATE 2
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/* QF interrupt disable/enable and log2()... */
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#if (__TARGET_ARCH_THUMB == 3) /* Cortex-M0/M0+/M1(v6-M, v6S-M)?, see NOTE2 */
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#define QF_INT_DISABLE() __disable_irq()
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#define QF_INT_ENABLE() __enable_irq()
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/* QF-aware ISR priority for CMSIS function NVIC_SetPriority(), NOTE2 */
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#define QF_AWARE_ISR_CMSIS_PRI 0
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#else /* Cortex-M3/M4/M4F, see NOTE3 */
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#define QF_INT_DISABLE() QF_set_BASEPRI(QF_BASEPRI)
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#define QF_INT_ENABLE() QF_set_BASEPRI(0U)
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/* NOTE: leave 2-bits for "kernel-unaware" interrupts, see NOTE4 */
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#define QF_BASEPRI (0xFFU >> 2)
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/* QF-aware ISR priority for CMSIS function NVIC_SetPriority(), NOTE5 */
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#define QF_AWARE_ISR_CMSIS_PRI (QF_BASEPRI >> (8 - __NVIC_PRIO_BITS))
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/* Cortex-M3/M4/M4F provide the CLZ instruction for fast LOG2 */
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#define QF_LOG2(n_) ((uint_fast8_t)(32U - __clz(n_)))
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/* inline function for setting the BASEPRI register */
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static __inline void QF_set_BASEPRI(unsigned basePri) {
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register unsigned volatile __regBasePri __asm("basepri");
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__regBasePri = basePri;
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}
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#endif
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/* QF critical section entry/exit */
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/* QF_CRIT_STAT_TYPE not defined: unconditional interrupt disabling" policy */
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#define QF_CRIT_ENTRY(dummy) QF_INT_DISABLE()
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#define QF_CRIT_EXIT(dummy) QF_INT_ENABLE()
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#define QF_CRIT_EXIT_NOP() __asm("isb")
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#include "qep_port.h" /* QEP port */
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#include "qv_port.h" /* QV port cooperative kernel port */
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#include "qf.h" /* QF platform-independent public interface */
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/*****************************************************************************
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* NOTE1:
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* The maximum number of active objects QF_MAX_ACTIVE can be increased
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* up to 63, if necessary. Here it is set to a lower level to save some RAM.
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*
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* NOTE2:
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* On Cortex-M0/M0+/M1 (architecture v6-M, v6S-M), the interrupt disabling
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* policy uses the PRIMASK register to disable interrupts globally. The
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* QF_AWARE_ISR_CMSIS_PRI level is zero, meaning that all interrupts are
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* "kernel-aware".
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*
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* NOTE3:
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* On Cortex-M3/M4/M4F, the interrupt disable/enable policy uses the BASEPRI
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* register (which is not implemented in Cortex-M0/M0+/M1) to disable
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* interrupts only with priority lower than the level specified by the
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* QF_BASEPRI macro. The interrupts with priorities above QF_BASEPRI (i.e.,
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* with numerical priority values lower than QF_BASEPRI) are not disabled in
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* this method. These free-running interrupts are not allowed to call any QF
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* services, because QF is not aware of these interrupts. Coversely, only
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* "QF-aware" interrupts, with numerical values of priorities eqal to or
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* higher than QF_BASEPRI, can call QF services.
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*
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* NOTE4:
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* For Cortex-M3/M4/M4F, the macro QF_BASEPRI leaves the top 2 priority bits
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* empty for QF-aware interrupts. This is the highest-possible priority
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* (lowest possible numerical value) for the guaranteed 3 priority bits
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* implemented in the NVIC.
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*
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* NOTE5:
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* The QF_AWARE_ISR_CMSIS_PRI macro is useful as an offset for enumerating
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* the QF-aware interrupt priority levels in the applications, whereas the
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* numerical values of the QF-aware interrupts must be greater or equal to
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* QF_AWARE_ISR_CMSIS_PRI. The enumerated values based on
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* QF_AWARE_ISR_CMSIS_PRI can be passed directly to the CMSIS function
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* NVIC_SetPriority(), which shifts them by (8 - __NVIC_PRIO_BITS) into the
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* correct bit position, while __NVIC_PRIO_BITS is the CMSIS macro defining
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* the number of implemented priority bits in the NVIC. Please note that
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* the macro QF_AWARE_ISR_CMSIS_PRI is intended only for applications and
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* is not used inside the QF port, which remains generic and not dependent
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* on the number of implemented priority bits in the NVIC.
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*/
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#endif /* qf_port_h */
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