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516 lines
19 KiB
C
516 lines
19 KiB
C
/*****************************************************************************
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* Product: DPP example, NXP mbed-LPC1768 board, coopearative QV kernel
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* Last Updated for Version: 5.6.5
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* Date of the Last Update: 2016-07-05
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*
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* Q u a n t u m L e a P s
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* ---------------------------
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* innovating embedded systems
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*
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* Copyright (C) Quantum Leaps, LLC. All rights reserved.
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*
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* This program is open source software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Alternatively, this program may be distributed and modified under the
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* terms of Quantum Leaps commercial licenses, which expressly supersede
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* the GNU General Public License and are specifically designed for
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* licensees interested in retaining the proprietary status of their code.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Contact information:
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* https://state-machine.com
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* mailto:info@state-machine.com
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*****************************************************************************/
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#include "qpc.h"
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#include "dpp.h"
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#include "bsp.h"
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#include "LPC17xx.h" /* CMSIS-compliant header file for the MCU used */
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/* add other drivers if necessary... */
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Q_DEFINE_THIS_FILE
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/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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* Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
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* DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
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*/
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enum KernelUnawareISRs { /* see NOTE00 */
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/* ... */
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MAX_KERNEL_UNAWARE_CMSIS_PRI /* keep always last */
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};
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/* "kernel-unaware" interrupts can't overlap "kernel-aware" interrupts */
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Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI <= QF_AWARE_ISR_CMSIS_PRI);
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enum KernelAwareISRs {
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EINT0_PRIO = QF_AWARE_ISR_CMSIS_PRI, /* see NOTE00 */
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SYSTICK_PRIO,
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/* ... */
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MAX_KERNEL_AWARE_CMSIS_PRI /* keep always last */
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};
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/* "kernel-aware" interrupts should not overlap the PendSV priority */
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Q_ASSERT_COMPILE(MAX_KERNEL_AWARE_CMSIS_PRI <= (0xFF >>(8-__NVIC_PRIO_BITS)));
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/* ISRs defined in this BSP ------------------------------------------------*/
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void SysTick_Handler(void);
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void EINT0_IRQHandler(void);
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/* Local-scope objects -----------------------------------------------------*/
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/* LEDs available on the board */
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#define LED_1 (1U << 18) /* P1.18 */
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#define LED_2 (1U << 20) /* P1.20 */
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#define LED_3 (1U << 21) /* P1.21 */
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#define LED_4 (1U << 23) /* P1.23 */
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/* Push-Button wired externally to DIP8 (P0.6) */
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#define BTN_EXT (1U << 6) /* P0.6 */
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static uint32_t l_rnd; /* random seed */
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#ifdef Q_SPY
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QSTimeCtr QS_tickTime_;
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QSTimeCtr QS_tickPeriod_;
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/* event-source identifiers used for tracing */
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static uint8_t l_SysTick_Handler;
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static uint8_t l_EINT0_IRQHandler;
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#define UART_BAUD_RATE 115200U
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#define UART_FR_TXFE 0x80U
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#define UART_TXFIFO_DEPTH 16U
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enum AppRecords { /* application-specific trace records */
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PHILO_STAT = QS_USER
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};
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#endif
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/* ISRs used in the application ==========================================*/
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void SysTick_Handler(void) {
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/* state of the button debouncing, see below */
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static struct ButtonsDebouncing {
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uint32_t depressed;
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uint32_t previous;
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} buttons = { ~0U, ~0U };
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uint32_t current;
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uint32_t tmp;
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#ifdef Q_SPY
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{
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tmp = SysTick->CTRL; /* clear CTRL_COUNTFLAG */
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QS_tickTime_ += QS_tickPeriod_; /* account for the clock rollover */
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}
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#endif
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QF_TICK_X(0U, &l_SysTick_Handler); /* process time events for rate 0 */
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/* get state of the buttons */
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/* Perform the debouncing of buttons. The algorithm for debouncing
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* adapted from the book "Embedded Systems Dictionary" by Jack Ganssle
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* and Michael Barr, page 71.
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*/
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current = ~LPC_GPIO0->FIOPIN; /* read P0 with the state of the Buttons */
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tmp = buttons.depressed; /* save the debounced depressed buttons */
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buttons.depressed |= (buttons.previous & current); /* set depressed */
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buttons.depressed &= (buttons.previous | current); /* clear released */
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buttons.previous = current; /* update the history */
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tmp ^= buttons.depressed; /* changed debounced depressed */
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if ((tmp & BTN_EXT) != 0U) { /* debounced BTN_EXT state changed? */
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if ((buttons.depressed & BTN_EXT) != 0U) { /* is BTN_EXT depressed? */
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static QEvt const pauseEvt = { PAUSE_SIG, 0U, 0U};
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QF_PUBLISH(&pauseEvt, &l_SysTick_Handler);
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}
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else { /* the button is released */
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static QEvt const serveEvt = { SERVE_SIG, 0U, 0U};
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QF_PUBLISH(&serveEvt, &l_SysTick_Handler);
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}
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}
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}
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/*..........................................................................*/
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void EINT0_IRQHandler(void) {
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QACTIVE_POST(AO_Table, Q_NEW(QEvt, MAX_PUB_SIG), /* for testing... */
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&l_EINT0_IRQHandler);
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}
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/* BSP functions ===========================================================*/
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void BSP_init(void) {
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/* NOTE: SystemInit() has been already called from the startup code
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* but SystemCoreClock needs to be updated
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*/
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SystemCoreClockUpdate();
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/* turn the GPIO clock on */
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LPC_SC->PCONP |= (1U << 15);
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/* setup the GPIO pin functions for the LEDs... */
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LPC_PINCON->PINSEL3 &= ~(3U << 4); /* LED_1: function P1.18 to GPIO */
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LPC_PINCON->PINSEL3 &= ~(3U << 8); /* LED_2: function P1.20 to GPIO */
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LPC_PINCON->PINSEL3 &= ~(3U << 10); /* LED_3: function P1.21 to GPIO */
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LPC_PINCON->PINSEL3 &= ~(3U << 14); /* LED_4: function P1.23 to GPIO */
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/* Set GPIO-P1 LED pins to output */
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LPC_GPIO1->FIODIR |= (LED_1 | LED_2 | LED_3 | LED_4);
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/* setup the GPIO pin function for the Button... */
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LPC_PINCON->PINSEL0 &= ~(3U << 12); /* function P0.6 to GPIO, pull-up */
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/* Set GPIO-P0 Button pin as input */
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LPC_GPIO0->FIODIR &= ~BTN_EXT;
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BSP_randomSeed(1234U);
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if (QS_INIT((void *)0) == 0U) { /* initialize the QS software tracing */
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Q_ERROR();
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}
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QS_OBJ_DICTIONARY(&l_SysTick_Handler);
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QS_OBJ_DICTIONARY(&l_EINT0_IRQHandler);
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QS_USR_DICTIONARY(PHILO_STAT);
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}
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/*..........................................................................*/
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void BSP_displayPhilStat(uint8_t n, char const *stat) {
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if (stat[0] == 'h') {
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LPC_GPIO1->FIOSET = LED_1; /* turn LED on */
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}
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else {
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LPC_GPIO1->FIOCLR = LED_1; /* turn LED off */
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}
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if (stat[0] == 'e') {
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LPC_GPIO1->FIOSET = LED_2; /* turn LED on */
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}
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else {
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LPC_GPIO1->FIOCLR = LED_2; /* turn LED off */
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}
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QS_BEGIN(PHILO_STAT, AO_Philo[n]) /* application-specific record begin */
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QS_U8(1, n); /* Philosopher number */
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QS_STR(stat); /* Philosopher status */
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QS_END()
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}
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/*..........................................................................*/
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void BSP_displayPaused(uint8_t paused) {
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if (paused != (uint8_t)0) {
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LPC_GPIO1->FIOSET = LED_3; /* turn LED on */
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}
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else {
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LPC_GPIO1->FIOCLR = LED_3; /* turn LED off */
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}
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}
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/*..........................................................................*/
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uint32_t BSP_random(void) { /* a very cheap pseudo-random-number generator */
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/* "Super-Duper" Linear Congruential Generator (LCG)
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* LCG(2^32, 3*7*11*13*23, 0, seed)
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*/
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l_rnd = l_rnd * (3U*7U*11U*13U*23U);
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return l_rnd >> 8;
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}
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/*..........................................................................*/
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void BSP_randomSeed(uint32_t seed) {
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l_rnd = seed;
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}
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/*..........................................................................*/
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void BSP_terminate(int16_t result) {
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(void)result;
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}
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/* QF callbacks ============================================================*/
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void QF_onStartup(void) {
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/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */
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SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);
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/* set priorities of ALL ISRs used in the system, see NOTE00
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*
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* !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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* Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
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* DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
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*/
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NVIC_SetPriority(SysTick_IRQn, SYSTICK_PRIO);
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NVIC_SetPriority(EINT0_IRQn, EINT0_PRIO);
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/* ... */
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/* enable IRQs in the NVIC... */
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NVIC_EnableIRQ(EINT0_IRQn);
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}
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/*..........................................................................*/
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void QF_onCleanup(void) {
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}
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/*..........................................................................*/
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void QV_onIdle(void) { /* called with interrupts disabled, see NOTE01 */
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/* toggle the LED on and then off, see NOTE02 */
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QF_INT_DISABLE();
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LPC_GPIO1->FIOSET = LED_4; /* turn LED on */
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__NOP(); /* a couple of NOPs to actually see the LED glow */
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__NOP();
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__NOP();
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__NOP();
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LPC_GPIO1->FIOCLR = LED_4; /* turn LED off */
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QF_INT_ENABLE();
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#ifdef Q_SPY
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if ((LPC_UART0->LSR & 0x20U) != 0U) { /* TX Holding Register empty? */
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uint16_t fifo = UART_TXFIFO_DEPTH; /* max bytes we can accept */
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uint8_t const *block;
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QF_INT_DISABLE();
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block = QS_getBlock(&fifo); /* try to get next block to transmit */
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QF_INT_ENABLE();
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while (fifo-- != 0) { /* any bytes in the block? */
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LPC_UART0->THR = *block++; /* put into the FIFO */
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}
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}
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#elif defined NDEBUG
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/* Put the CPU and peripherals to the low-power mode.
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* you might need to customize the clock management for your application,
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* see the datasheet for your particular Cortex-M MCU.
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*/
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QV_CPU_SLEEP(); /* atomically go to sleep and enable interrupts */
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#else
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QF_INT_ENABLE(); /* just enable interrupts */
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#endif
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}
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/*..........................................................................*/
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void Q_onAssert(char const *module, int loc) {
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/*
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* NOTE: add here your application-specific error handling
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*/
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(void)module;
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(void)loc;
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QS_ASSERTION(module, loc, (uint32_t)10000U); /* report assertion to QS */
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NVIC_SystemReset();
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}
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/* QS callbacks ============================================================*/
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#ifdef Q_SPY
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static void UART0_setBaudrate(uint32_t baud); /* helper function */
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/*..........................................................................*/
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uint8_t QS_onStartup(void const *arg) {
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static uint8_t qsBuf[2*1024]; /* buffer for Quantum Spy */
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QS_initBuf(qsBuf, sizeof(qsBuf));
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// setup the P0_2 UART0 TX pin
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LPC_PINCON->PINSEL0 &= ~(3U << 4); /* clear P0_2 function */
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LPC_PINCON->PINSEL0 |= (1U << 4); /* P0_2 to UART function (TX) */
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LPC_PINCON->PINMODE0 &= ~(3U << 4); /* P0_2 pull-up register */
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// setup the P0_3 UART0 RX pin
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LPC_PINCON->PINSEL0 &= ~(3U << 6); /* clear P0_3 function */
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LPC_PINCON->PINSEL0 |= (1U << 6); /* P0_3 to UART function (RX) */
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LPC_PINCON->PINMODE0 &= ~(3U << 6); /* P0_3 pull-up register */
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/* enable power to UART0 */
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LPC_SC->PCONP |= (1U << 3);
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/* enable FIFOs and default RX trigger level */
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LPC_UART0->FCR =
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(1U << 0) /* FIFO Enable - 0 = Disables, 1 = Enabled */
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| (0U << 1) /* Rx Fifo Reset */
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| (0U << 2) /* Tx Fifo Reset */
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| (0U << 6); /* Rx irq trig: 0=1char, 1=4chars, 2=8chars, 3=14chars */
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/* disable IRQs */
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LPC_UART0->IER =
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(0U << 0) /* Rx Data available IRQ disable */
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| (0U << 1) /* Tx Fifo empty IRQ disable */
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| (0U << 2); /* Rx Line Status IRQ disable */
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// set default baud rate
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UART0_setBaudrate(115200U);
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// format 8-data-bits, 1-stop-bit, parity-none
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LPC_UART0->LCR =
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(3U << 0) /* 8-data-bits */
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| (0U << 2) /* 1 stop-bit */
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| (0U << 3) /* parity disable */
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| (0U << 4); /* parity none */
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QS_tickPeriod_ = SystemCoreClock / BSP_TICKS_PER_SEC;
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QS_tickTime_ = QS_tickPeriod_; /* to start the timestamp at zero */
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/* setup the QS filters... */
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QS_FILTER_ON(QS_QEP_STATE_ENTRY);
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QS_FILTER_ON(QS_QEP_STATE_EXIT);
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QS_FILTER_ON(QS_QEP_STATE_INIT);
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QS_FILTER_ON(QS_QEP_INIT_TRAN);
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QS_FILTER_ON(QS_QEP_INTERN_TRAN);
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QS_FILTER_ON(QS_QEP_TRAN);
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QS_FILTER_ON(QS_QEP_IGNORED);
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QS_FILTER_ON(QS_QEP_DISPATCH);
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QS_FILTER_ON(QS_QEP_UNHANDLED);
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QS_FILTER_ON(PHILO_STAT);
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return (uint8_t)1; /* return success */
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}
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/*..........................................................................*/
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void QS_onCleanup(void) {
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}
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/*..........................................................................*/
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QSTimeCtr QS_onGetTime(void) { /* NOTE: invoked with interrupts DISABLED */
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if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) { /* not set? */
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return QS_tickTime_ - (QSTimeCtr)SysTick->VAL;
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}
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else { /* the rollover occured, but the SysTick_ISR did not run yet */
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return QS_tickTime_ + QS_tickPeriod_ - (QSTimeCtr)SysTick->VAL;
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}
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}
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/*..........................................................................*/
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void QS_onFlush(void) {
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uint16_t b;
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QF_INT_DISABLE();
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while ((b = QS_getByte()) != QS_EOD) { /* while not End-Of-Data... */
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QF_INT_ENABLE();
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while ((LPC_UART0->LSR & 0x20U) == 0U) { /* while THR empty... */
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}
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LPC_UART0->THR = (b & 0xFFU); /* put into the DR register */
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QF_INT_DISABLE();
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}
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QF_INT_ENABLE();
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}
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/*..........................................................................*/
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/*
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* Set the LPC UART0 barud-rate generator according to
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* Section 14.4.12 in LPC176x Manual (document UM10360)
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*/
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static void UART0_setBaudrate(uint32_t baud) {
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/* First we check to see if the basic divide with no DivAddVal/MulVal
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* ratio gives us an integer result. If it does, we set DivAddVal = 0,
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* MulVal = 1. Otherwise, we search the valid ratio value range to find
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* the closest match. This could be more elegant, using search methods
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* and/or lookup tables, but the brute force method is not that much
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* slower, and is more maintainable.
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*/
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uint32_t PCLK = SystemCoreClock; /* divider /1 set below */
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uint16_t DL = PCLK / (16U * baud);
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uint8_t DivAddVal = 0U;
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uint8_t MulVal = 1U;
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/* set PCLK divider to 1 */
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LPC_SC->PCLKSEL0 &= ~(0x3U << 6); /* clear divider bits */
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LPC_SC->PCLKSEL0 |= (0x1U << 6); /* set divider to 1 */
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if ((PCLK % (16U * baud)) != 0U) { /* non zero remainder? */
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uint32_t err_best = baud;
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bool found = false;
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uint32_t b;
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uint8_t mv;
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for (mv = 1U; mv < 16U && !found; mv++) {
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uint16_t dlv;
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uint8_t dav;
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for (dav = 0U; dav < mv; ++dav) {
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/*
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* baud = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
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* solving for dlv, we get
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* dlv = mul * PCLK / (16 * baud * (divadd + mul))
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* mul has 4 bits, PCLK has 27 so we have 1 bit headroom,
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* which can be used for rounding for many values of mul
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* and PCLK we have 2 or more bits of headroom which can
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* be used to improve precision
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* note: X / 32 doesn't round correctly.
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* Instead, we use ((X / 16) + 1) / 2 for correct rounding
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*/
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if ((mv*PCLK*2U) & 0x80000000U) { /* 1 bit headroom */
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dlv = ((((2U*mv*PCLK) / (baud*(dav + mv)))/16U) + 1U)/2U;
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}
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else { /* 2 bits headroom, use more precision */
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dlv = ((((4U*mv*PCLK) / (baud*(dav+mv)))/32U) + 1U)/2U;
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}
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/* datasheet says if DLL==DLM==0, then 1 is used instead */
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if (dlv == 0U) {
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dlv = 1U;
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}
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/* datasheet says if dav > 0 then DL must be >= 2 */
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if ((dav > 0U) && (dlv < 2U)) {
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dlv = 2U;
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}
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/* integer rearrangement of baud equation (with rounding) */
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b = ((PCLK*mv / (dlv*(dav + mv)*8U)) + 1U)/2U;
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b = (b >= baud) ? (b - baud) : (baud - b);
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/* check to see how we did */
|
|
if (b < err_best) {
|
|
err_best = b;
|
|
DL = dlv;
|
|
MulVal = mv;
|
|
DivAddVal = dav;
|
|
|
|
if (b == baud) {
|
|
found = true;
|
|
break; /* break out of the inner for-loop */
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// set LCR[DLAB] to enable writing to divider registers
|
|
LPC_UART0->LCR |= (1U << 7);
|
|
|
|
// set divider values
|
|
LPC_UART0->DLM = (DL >> 8) & 0xFFU;
|
|
LPC_UART0->DLL = (DL >> 0) & 0xFFU;
|
|
LPC_UART0->FDR = ((uint32_t)DivAddVal << 0)
|
|
| ((uint32_t)MulVal << 4);
|
|
|
|
// clear LCR[DLAB]
|
|
LPC_UART0->LCR &= ~(1U << 7);
|
|
}
|
|
|
|
#endif /* Q_SPY */
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*****************************************************************************
|
|
* NOTE00:
|
|
* The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
|
|
* ISR priority that is disabled by the QF framework. The value is suitable
|
|
* for the NVIC_SetPriority() CMSIS function.
|
|
*
|
|
* Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e.,
|
|
* with the numerical values of priorities equal or higher than
|
|
* QF_AWARE_ISR_CMSIS_PRI) are allowed to call the QK_ISR_ENTRY/QK_ISR_ENTRY
|
|
* macros or any other QF/QK services. These ISRs are "QF-aware".
|
|
*
|
|
* Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority
|
|
* level (i.e., with the numerical values of priorities less than
|
|
* QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel.
|
|
* Such "QF-unaware" ISRs cannot call any QF/QK services. In particular they
|
|
* can NOT call the macros QK_ISR_ENTRY/QK_ISR_ENTRY. The only mechanism
|
|
* by which a "QF-unaware" ISR can communicate with the QF framework is by
|
|
* triggering a "QF-aware" ISR, which can post/publish events.
|
|
*
|
|
* NOTE01:
|
|
* The QV_onIdle() callback is called with interrupts disabled, because the
|
|
* determination of the idle condition might change by any interrupt posting
|
|
* an event. QV_onIdle() must internally enable interrupts, ideally
|
|
* atomically with putting the CPU to the power-saving mode.
|
|
*
|
|
* NOTE02:
|
|
* The User LED is used to visualize the idle loop activity. The brightness
|
|
* The User LED is used to visualize the idle loop activity. The brightness
|
|
* of the LED is proportional to the frequency of invcations of the idle loop.
|
|
* Please note that the LED is toggled with interrupts locked, so no interrupt
|
|
* execution time contributes to the brightness of the User LED.
|
|
*/
|