mirror of
https://github.com/QuantumLeaps/qpc.git
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228 lines
10 KiB
ArmAsm
228 lines
10 KiB
ArmAsm
;/**************************************************************************/
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;/* */
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;/* Copyright (c) 1996-2011 by Express Logic Inc. */
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;/* */
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;/* This software is copyrighted by and is the sole property of Express */
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;/* Logic, Inc. All rights, title, ownership, or other interests */
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;/* in the software remain the property of Express Logic, Inc. This */
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;/* software may only be used in accordance with the corresponding */
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;/* license agreement. Any unauthorized use, duplication, transmission, */
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;/* distribution, or disclosure of this software is expressly forbidden. */
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;/* */
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;/* This Copyright notice may not be removed or modified without prior */
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;/* written consent of Express Logic, Inc. */
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;/* */
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;/* Express Logic, Inc. reserves the right to modify this software */
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;/* without notice. */
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;/* */
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;/* Express Logic, Inc. info@expresslogic.com */
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;/* 11423 West Bernardo Court http://www.expresslogic.com */
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;/* San Diego, CA 92127 */
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;/* */
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;/**************************************************************************/
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;
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;
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;/**************************************************************************/
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;/**************************************************************************/
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;/** */
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;/** ThreadX Component */
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;/** */
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;/** Initialize */
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;/** */
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;/**************************************************************************/
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;/**************************************************************************/
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;
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;#define TX_SOURCE_CODE
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;
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;
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;/* Include necessary system files. */
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;
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;#include "tx_api.h"
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;#include "tx_initialize.h"
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;#include "tx_thread.h"
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;#include "tx_timer.h"
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;
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;
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EXTERN _tx_thread_system_stack_ptr
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EXTERN _tx_initialize_unused_memory
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EXTERN _tx_thread_context_save
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EXTERN _tx_thread_context_restore
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EXTERN _tx_timer_interrupt
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EXTERN __iar_program_start
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EXTERN __tx_SVCallHandler
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EXTERN __tx_PendSVHandler
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EXTERN __tx_vectors
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EXTERN __iar_program_start
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;
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;
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SYSTEM_CLOCK EQU 150000000
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SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
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RSEG FREE_MEM:DATA
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PUBLIC __tx_free_memory_start
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__tx_free_memory_start
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DS32 4
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;
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;
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SECTION `.text`:CODE:NOROOT(2)
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THUMB
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;/**************************************************************************/
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;/* */
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;/* FUNCTION RELEASE */
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;/* */
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;/* _tx_initialize_low_level Cortex-M4/IAR */
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;/* 5.1 */
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;/* AUTHOR */
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;/* */
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;/* William E. Lamie, Express Logic, Inc. */
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;/* */
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;/* DESCRIPTION */
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;/* */
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;/* This function is responsible for any low-level processor */
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;/* initialization, including setting up interrupt vectors, setting */
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;/* up a periodic timer interrupt source, saving the system stack */
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;/* pointer for use in ISR processing later, and finding the first */
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;/* available RAM memory address for tx_application_define. */
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;/* */
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;/* INPUT */
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;/* */
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;/* None */
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;/* */
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;/* OUTPUT */
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;/* */
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;/* None */
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;/* */
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;/* CALLS */
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;/* */
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;/* None */
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;/* */
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;/* CALLED BY */
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;/* */
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;/* _tx_initialize_kernel_enter ThreadX entry function */
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;/* */
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;/* RELEASE HISTORY */
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;/* */
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;/* DATE NAME DESCRIPTION */
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;/* */
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;/* 10-10-2010 William E. Lamie Initial Version 5.0 */
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;/* 07-15-2011 William E. Lamie Modified comment(s), */
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;/* resulting in version 5.1 */
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;/* */
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;/**************************************************************************/
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;VOID _tx_initialize_low_level(VOID)
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;{
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PUBLIC _tx_initialize_low_level
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_tx_initialize_low_level:
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;
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; /* Ensure that interrupts are disabled. */
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;
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CPSID i ; Disable interrupts
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;
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;
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; /* Set base of available memory to end of non-initialised RAM area. */
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;
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LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area
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LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer
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STR r0, [r2, #0] ; Save first free memory address
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;
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; /* Enable the cycle count register. */
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;
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LDR r0, =0xE0001000 ; Build address of DWT register
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LDR r1, [r0] ; Pickup the current value
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ORR r1, r1, #1 ; Set the CYCCNTENA bit
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STR r1, [r0] ; Enable the cycle count register
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;
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; /* Setup Vector Table Offset Register. */
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;
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MOV r0, #0xE000E000 ; Build address of NVIC registers
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LDR r1, =__tx_vectors ; Pickup address of vector table
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STR r1, [r0, #0xD08] ; Set vector table address
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;
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; /* Set system stack pointer from vector value. */
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;
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LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer
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LDR r1, =__tx_vectors ; Pickup address of vector table
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LDR r1, [r1] ; Pickup reset stack pointer
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STR r1, [r0] ; Save system stack pointer
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;
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; /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
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;
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MOV r0, #0xE000E000 ; Build address of NVIC registers
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LDR r1, =SYSTICK_CYCLES
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STR r1, [r0, #0x14] ; Setup SysTick Reload Value
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MOV r1, #0x7 ; Build SysTick Control Enable Value
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STR r1, [r0, #0x10] ; Setup SysTick Control
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;
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; /* Configure handler priorities. */
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;
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LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
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STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers
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LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
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STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers
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; Note: SVC must be lowest priority, which is 0xFF
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LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
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STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers
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; Note: PnSV must be lowest priority, which is 0xFF
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LDR r0, =0xE000EF34 ; Pickup FPCCR
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LDR r1, [r0] ;
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LDR r2, =0x3FFFFFFF ; Build mask to clear ASPEN and LSPEN
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AND r1, r1, r2 ; Clear the ASPEN and LSPEN bits
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STR r1, [r0] ; Update FPCCR
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;
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; /* Return to caller. */
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;
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BX lr
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;}
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;
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;
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PUBLIC __stack_test
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__stack_test:
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push {r0}
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push {r1}
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push {r2}
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push {r3}
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pop {r3}
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pop {r2}
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pop {r1}
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pop {r0}
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bx lr
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;/* Define shells for each of the unused vectors. */
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;
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PUBLIC __tx_IntHandler
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__tx_IntHandler:
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; VOID InterruptHandler (VOID)
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; {
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PUSH {lr}
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BL _tx_thread_context_save
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; /* Do interrupt handler work here */
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; /* .... */
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B _tx_thread_context_restore
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; }
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PUBLIC __tx_SysTickHandler
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__tx_SysTickHandler:
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; VOID TimerInterruptHandler (VOID)
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; {
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;
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PUSH {lr}
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BL _tx_thread_context_save
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MOV r0, #0xE000E000 ; Build address of NVIC registers
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LDR r1, [r0, #0x10] ; Clear SysTick interrupt
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BL _tx_timer_interrupt
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B _tx_thread_context_restore
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; }
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END
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