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260 lines
11 KiB
ArmAsm
260 lines
11 KiB
ArmAsm
;*****************************************************************************
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; Product: QK port to ARM Cortex-M (M0,M0+,M3,M4,M7), ARM-KEIL assembler
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; Last Updated for Version: 5.8.1
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; Date of the Last Update: 2016-12-12
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;
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; Q u a n t u m L e a P s
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; ---------------------------
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; innovating embedded systems
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;
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; Copyright (C) Quantum Leaps, LLC. All rights reserved.
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;
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; This program is open source software: you can redistribute it and/or
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; modify it under the terms of the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or
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; (at your option) any later version.
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;
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; Alternatively, this program may be distributed and modified under the
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; terms of Quantum Leaps commercial licenses, which expressly supersede
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; the GNU General Public License and are specifically designed for
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; licensees interested in retaining the proprietary status of their code.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program. If not, see <http://www.gnu.org/licenses/>.
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;
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; Contact information:
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; http://www.state-machine.com
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; mailto:info@state-machine.com
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;*****************************************************************************
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EXPORT QK_init
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EXPORT PendSV_Handler ; CMSIS-compliant PendSV exception name
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EXPORT NMI_Handler ; CMSIS-compliant NMI exception name
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IMPORT QK_activate_ ; external reference
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IMPORT QK_attr_ ; QK attribute structure
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; NOTE: keep in synch with QF_BASEPRI value defined in "qf_port.h" !!!
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QF_BASEPRI EQU (0xFF:SHR:2)
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AREA |.text|, CODE, READONLY
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THUMB
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PRESERVE8 ; this code preserves 8-byte stack alignment
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ALIGN ; ensures alignment
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;*****************************************************************************
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; The QK_init() function sets the priority of PendSV to 0xFF (lowest urgency).
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; For Cortex-M3/4/7, it also sets priorities of all other exceptions and IRQs
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; to the safe value. All this is performed in a nestable critical section.
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;*****************************************************************************
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QK_init FUNCTION
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MRS r0,PRIMASK ; store the state of the PRIMASK
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MOV r12,r0 ; r12 := PRIMASK
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CPSID i ; PRIMASK := 1
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IF {TARGET_ARCH_THUMB} == 3 ; Cortex-M0/M0+/M1 (v6-M, v6S-M)?
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LDR r1,=0xE000ED18 ; System Handler Priority Register
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LDR r2,[r1,#8] ; load the System 12-15 Priority Register
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MOVS r3,#0xFF
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LSLS r3,r3,#16
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ORRS r2,r3 ; set PRI_14 (PendSV) to 0xFF
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STR r2,[r1,#8] ; write the System 12-15 Priority Register
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ELSE ; Cortex-M3/M4/..
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; NOTE:
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; On Cortex-M3/M4/.., this QK port disables interrupts by means of the
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; BASEPRI register. However, this method cannot disable interrupt
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; priority zero, which is the default for all interrupts out of reset.
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; The following code changes the SysTick priority and all IRQ priorities
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; to the safe value QF_BASEPRI, wich the QF critical section can disable.
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; This avoids breaching of the QF critical sections in case the
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; application programmer forgets to explicitly set priorities of all
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; "kernel aware" interrupts.
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; set all prioriy bytes to QF_BASEPRI in r1
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MOVS r1,#QF_BASEPRI
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LSLS r1,r1,#8
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ORRS r1,r1,#QF_BASEPRI
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LSLS r1,r1,#8
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ORRS r1,r1,#QF_BASEPRI
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LSLS r1,r1,#8
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ORRS r1,r1,#QF_BASEPRI
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LDR r3,=0xE000ED18 ; System Handler Priority Register
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LDR r2,[r3] ; r2 := SYSPRI1
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ORRS r2,r1 ; r2 |= "all values to QF_BASEPRI"
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STR r2,[r3] ; SYSPRI1 |= r2, Usage-fault/Bus-fault/Mem-fault
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LDR r2,[r3,#4] ; r2 := SYSPRI2
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ORRS r2,r1 ; r2 |= "all values to QF_BASEPRI"
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STR r2,[r3,#4] ; SYSPRI2 := r2, SVCall
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LDR r2,[r3,#8] ; r2 := SYSPRI3
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ORRS r1,r1,#(0xFF << 16) ; r1 |= 0xFF for PendSV
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ORRS r2,r1
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STR r2,[r3,#8] ; SYSPRI3 |= r2, SysTick/PendSV/Debug
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; set again all prioriy bytes to QF_BASEPRI in r1
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MOVS r1,#QF_BASEPRI
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LSLS r1,r1,#8
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ORRS r1,r1,#QF_BASEPRI
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LSLS r1,r1,#8
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ORRS r1,r1,#QF_BASEPRI
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LSLS r1,r1,#8
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ORRS r1,r1,#QF_BASEPRI
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LDR r3,=0xE000E004 ; Interrupt Controller Type Register
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LDR r3,[r3] ; r3 := INTLINESUM
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LSLS r3,r3,#3
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ADDS r3,r3,#8 ; r3 == number of NVIC_PRIO registers
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; loop over all implemented NVIC_PRIO registers for IRQs...
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QK_init_irq
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SUBS r3,r3,#1
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LDR r2,=0xE000E400 ; NVIC_PRI0 register
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STR r1,[r2,r3,LSL #2] ; NVIC_PRI0[r3] := r1
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CMP r3,#0
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BNE QK_init_irq
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ENDIF ; M3/M4/M7
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MOV r0,r12 ; r0 := original PRIMASK
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MSR PRIMASK,r0 ; PRIMASK := r0
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BX lr ; return to the caller
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ENDFUNC
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;*****************************************************************************
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; The PendSV_Handler exception handler is used for handling asynchronous
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; preemption in QK. The use of the PendSV exception is the recommended
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; and most efficient method for performing context switches with ARM Cortex-M.
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;
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; The PendSV exception should have the lowest priority in the whole system
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; (0xFF, see QK_init). All other exceptions and interrupts should have higher
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; priority. For example, for NVIC with 2 priority bits all interrupts and
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; exceptions must have numerical value of priority lower than 0xC0. In this
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; case the interrupt priority levels available to your applications are (in
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; the order from the lowest urgency to the highest urgency): 0x80, 0x40, 0x00.
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;
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; Also, *all* "kernel aware" ISRs in the QK application must trigger
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; the PendSV exception by calling the QK_ISR_EXIT() macro.
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;
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; Due to tail-chaining and its lowest priority, the PendSV exception will be
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; entered immediately after the exit from the *last* nested interrupt (or
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; exception). In QK, this is exactly the time when the QK activator needs to
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; handle the asynchronous preemption.
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;*****************************************************************************
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PendSV_Handler FUNCTION
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; Prepare some constants in registers before entering critical section
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LDR r3,=0xE000ED04 ; Interrupt Control and State Register
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MOVS r1,#1
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LSLS r1,r1,#27 ; r0 := (1 << 27) (UNPENDSVSET bit)
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; <<<<<<<<<<<<<<<<<<<<<<< CRITICAL SECTION BEGIN <<<<<<<<<<<<<<<<<<<<<<<<<
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IF {TARGET_ARCH_THUMB} == 3 ; Cortex-M0/M0+/M1 (v6-M, v6S-M)?
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CPSID i ; disable interrupts (set PRIMASK)
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ELSE ; M3/M4/M7
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IF {TARGET_FPU_VFP} == {TRUE} ; if VFP available...
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PUSH {r0,lr} ; ... push lr (EXC_RETURN) plus stack-aligner
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ENDIF ; VFP available
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MOVS r0,#QF_BASEPRI
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MSR BASEPRI,r0 ; selectively disable interrupts
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ENDIF ; M3/M4/M7
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; The PendSV exception handler can be preempted by an interrupt,
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; which might pend PendSV exception again. The following write to
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; ICSR[27] un-pends any such spurious instance of PendSV.
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STR r1,[r3] ; ICSR[27] := 1 (unpend PendSV)
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; The QK activator must be called in a Thread mode, while this code
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; executes in the Handler mode of the PendSV exception. The switch
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; to the Thread mode is accomplished by returning from PendSV using
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; a fabricated exception stack frame, where the return address is
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; QK_activate_().
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;
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; NOTE: the QK activator is called with interrupts DISABLED and also
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; returns with interrupts DISABLED.
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LSRS r3,r1,#3 ; r3 := (r1 >> 3), set the T bit (new xpsr)
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LDR r2,=QK_activate_ ; address of QK_activate_
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SUBS r2,r2,#1 ; align Thumb-address at halfword (new pc)
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LDR r1,=Thread_ret ; return address after the call (new lr)
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SUB sp,sp,#8*4 ; reserve space for exception stack frame
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ADD r0,sp,#5*4 ; r0 := 5 registers below the top of stack
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STM r0!,{r1-r3} ; save xpsr,pc,lr
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MOVS r0,#6
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MVNS r0,r0 ; r0 := ~6 == 0xFFFFFFF9
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BX r0 ; exception-return to the QK activator
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ENDFUNC
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;*****************************************************************************
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; Thread_ret is a helper function executed when the QXK activator returns.
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;
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; NOTE: Thread_ret does not execute in the PendSV context!
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; NOTE: Thread_ret executes entirely with interrupts DISABLED.
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;*****************************************************************************
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Thread_ret FUNCTION
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; After the QK activator returns, we need to resume the preempted
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; task. However, this must be accomplished by a return-from-exception,
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; while we are still in the task context. The switch to the exception
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; contex is accomplished by triggering the NMI exception.
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; NOTE: The NMI exception is triggered with nterrupts DISABLED,
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; because QK activator disables interrutps before return.
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; before triggering the NMI exception, make sure that the
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; VFP stack frame will NOT be used...
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IF {TARGET_FPU_VFP} == {TRUE} ; if VFP available...
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MRS r0,CONTROL ; r0 := CONTROL
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BICS r0,r0,#4 ; r0 := r0 & ~4 (FPCA bit)
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MSR CONTROL,r0 ; CONTROL := r0 (clear CONTROL[2] FPCA bit)
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ENDIF ; VFP available
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; trigger NMI to return to preempted task...
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LDR r0,=0xE000ED04 ; Interrupt Control and State Register
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MOVS r1,#1
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LSLS r1,r1,#31 ; r0 := (1 << 31) (NMI bit)
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STR r1,[r0] ; ICSR[31] := 1 (pend NMI)
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B . ; wait for preemption by NMI
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ENDFUNC
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;*****************************************************************************
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; The NMI_Handler exception handler is used for returning back to the
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; interrupted task. The NMI exception simply removes its own interrupt
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; stack frame from the stack and returns to the preempted task using the
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; interrupt stack frame that must be at the top of the stack.
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;
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; NOTE: The NMI exception is entered with interrupts DISABLED, so it needs
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; to re-enable interrupts before it returns to the preempted task.
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;*****************************************************************************
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NMI_Handler FUNCTION
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ADD sp,sp,#(8*4) ; remove one 8-register exception frame
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IF {TARGET_ARCH_THUMB} == 3 ; Cortex-M0/M0+/M1 (v6-M, v6S-M)?
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CPSIE i ; enable interrupts (clear PRIMASK)
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BX lr ; return to the preempted task
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ELSE ; M3/M4/M7
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MOVS r0,#0
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MSR BASEPRI,r0 ; enable interrupts (clear BASEPRI)
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IF {TARGET_FPU_VFP} == {TRUE} ; if VFP available...
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POP {r0,pc} ; pop stack "aligner" and EXC_RETURN to PC
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ELSE
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BX lr ; return to the preempted task
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ENDIF ; VFP available ENDIF
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ENDIF ; M3/M4/M7
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ENDFUNC
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ALIGN ; make sure the END is properly aligned
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END
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