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e032055963
7.1.3 Replaced QF_EVT_REF_CTR_INC_() with QEvt_refCtr_inc_() in ports - embOS - ESP-IDF - Qt 7.1.3 7.1.3 7.1.3 7.1.3 7.1.3 7.1.3 7.1.2 first commit after fixing history Revert "7.1.2" This reverts commit 90cf4e1471b5e9c0853af97af8ec0bc67c7e19c6. 7.1.2 first commit after fixing the history 7.0.1
72 lines
2.3 KiB
C
72 lines
2.3 KiB
C
/*============================================================================
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* QP/C Real-Time Embedded Framework (RTEF)
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* Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial
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*
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* This software is dual-licensed under the terms of the open source GNU
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* General Public License version 3 (or any later version), or alternatively,
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* under the terms of one of the closed source Quantum Leaps commercial
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* licenses.
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*
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* The terms of the open source GNU General Public License version 3
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* can be found at: <www.gnu.org/licenses/gpl-3.0>
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*
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* The terms of the closed source Quantum Leaps commercial licenses
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* can be found at: <www.state-machine.com/licensing>
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*
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* Redistributions in source code must retain this top-level comment block.
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* Plagiarizing this software to sidestep the license obligations is illegal.
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*
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* Contact information:
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* <www.state-machine.com>
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* <info@state-machine.com>
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============================================================================*/
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/*!
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* @date Last updated on: 2022-06-12
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* @version Last updated for: @ref qpc_7_0_1
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*
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* @file
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* @brief QV/C port to ARM Cortex-M, IAR-ARM toolset
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*/
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#ifndef QV_PORT_H
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#define QV_PORT_H
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#if (__CORE__ == __ARM6M__) /* Cortex-M0/M0+/M1 ? */
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/* macro to put the CPU to sleep inside QV_onIdle() */
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#define QV_CPU_SLEEP() do { \
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__WFI(); \
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QF_INT_ENABLE(); \
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} while (false)
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#define QV_ARM_ERRATUM_838869() ((void)0)
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#else /* Cortex-M3/M4/M7(v7-M) */
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/* macro to put the CPU to sleep inside QV_onIdle() */
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#define QV_CPU_SLEEP() do { \
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QF_PRIMASK_DISABLE(); \
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QF_INT_ENABLE(); \
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__WFI(); \
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QF_PRIMASK_ENABLE(); \
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} while (false)
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/* initialization of the QV kernel for Cortex-M3/M4/M4F */
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#define QV_INIT() QV_init()
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void QV_init(void);
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/* The following macro implements the recommended workaround for the
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* ARM Erratum 838869. Specifically, for Cortex-M3/M4/M7 the DSB
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* (memory barrier) instruction needs to be added before exiting an ISR.
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* This macro should be inserted at the end of ISRs.
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*/
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#define QV_ARM_ERRATUM_838869() __DSB()
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#endif
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#include "qv.h" /* QV platform-independent public interface */
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#endif /* QV_PORT_H */
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