mirror of
https://github.com/QuantumLeaps/qpcpp.git
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380 lines
14 KiB
C++
380 lines
14 KiB
C++
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//****************************************************************************
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// Product: DPP on AT91SAM7S-EK, cooperative QV kernel, IAR-ARM toolset
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// Last Updated for Version: 5.4.0
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// Date of the Last Update: 2015-05-04
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//
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// Q u a n t u m L e a P s
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// ---------------------------
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// innovating embedded systems
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//
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// Copyright (C) 2002-2013 Quantum Leaps, LLC. All rights reserved.
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//
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// This program is open source software: you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Alternatively, this program may be distributed and modified under the
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// terms of Quantum Leaps commercial licenses, which expressly supersede
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// the GNU General Public License and are specifically designed for
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// licensees interested in retaining the proprietary status of their code.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Contact information:
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// Web : http://www.state-machine.com
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// Email: info@state-machine.com
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//****************************************************************************
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#include "qpcpp.h"
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#include "dpp.h"
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#include "bsp.h"
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#include "AT91SAM7S64.h" // Atmel AT91SAM7S64 MCU
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#pragma diag_suppress=Ta021 // call __iar_disable_interrupt from __ramfunc
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#pragma diag_suppress=Ta022 // possible ROM access <ptr> from __ramfunc
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#pragma diag_suppress=Ta023 // call to non __ramfunc from __ramfunc
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// extern "C" functions in C =================================================
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extern "C" {
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//............................................................................
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__ramfunc
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void BSP_irq(void) {
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IntVector vect = (IntVector)AT91C_BASE_AIC->AIC_IVR; // read the IVR
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AT91C_BASE_AIC->AIC_IVR = (AT91_REG)vect; // write AIC_IVR if protected
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QF_INT_ENABLE(); // allow nesting interrupts
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(*vect)(); // call the IRQ ISR via the pointer to function
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QF_INT_DISABLE(); // disable interrups for the exit sequence
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AT91C_BASE_AIC->AIC_EOICR = 0; // write AIC_EOICR to clear interrupt
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}
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} // extern "C"
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namespace DPP {
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Q_DEFINE_THIS_FILE
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// Local objects -------------------------------------------------------------
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typedef void (*IntVector)(void); // IntVector pointer-to-function
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uint32_t const l_led[] = {
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(1U << 0), // LED D1 on AT91SAM7S-EK
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(1U << 1), // LED D2 on AT91SAM7S-EK
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(1U << 2), // LED D3 on AT91SAM7S-EK
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(1U << 3), // LED D4 on AT91SAM7S-EK
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0U // no LED 5 on AT91SAM7S-EK
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};
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#define LED_ON(num_) (AT91C_BASE_PIOA->PIO_CODR = l_led[num_])
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#define LED_OFF(num_) (AT91C_BASE_PIOA->PIO_SODR = l_led[num_])
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static unsigned l_rnd; // random seed
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#ifdef Q_SPY
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static uint8_t const l_ISR_tick = 0;
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enum AppRecords { // application-specific trace records
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PHILO_STAT = QP::QS_USER
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};
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#endif
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// ISRs ======================================================================
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__ramfunc
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static void ISR_tick(void) {
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uint32_t volatile tmp = AT91C_BASE_PITC->PITC_PIVR; // clear interrupt
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(void)tmp; // avoid the compiler warning about unused variable
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QP::QF::TICK_X(0U, &l_ISR_tick); // process all time events at tick rate 0
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}
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//............................................................................
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__ramfunc
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static void ISR_spur(void) {
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}
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// BSP functions =============================================================
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void BSP_init(void) {
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uint32_t i;
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for (i = 0; i < Q_DIM(l_led); ++i) { // initialize the LEDs...
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AT91C_BASE_PIOA->PIO_PER = l_led[i]; // enable pin
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AT91C_BASE_PIOA->PIO_OER = l_led[i]; // configure as output pin
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LED_OFF(i); // extinguish the LED
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}
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// configure Advanced Interrupt Controller (AIC) of AT91...
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AT91C_BASE_AIC->AIC_IDCR = ~0; // disable all interrupts
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AT91C_BASE_AIC->AIC_ICCR = ~0; // clear all interrupts
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for (i = 0; i < 8; ++i) {
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AT91C_BASE_AIC->AIC_EOICR = 0; // write AIC_EOICR 8 times
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}
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// set the desired ticking rate for the PIT...
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i = (get_MCK_FREQ() / 16U / BSP_TICKS_PER_SEC) - 1U;
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AT91C_BASE_PITC->PITC_PIMR = (AT91C_PITC_PITEN | AT91C_PITC_PITIEN | i);
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BSP_randomSeed(1234U); // seed the random number generator
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if (QS_INIT((void *)0) == 0) { // initialize the QS software tracing
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Q_ERROR();
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}
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QS_OBJ_DICTIONARY(&l_ISR_tick);
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}
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//............................................................................
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void BSP_terminate(int16_t result) {
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(void)result;
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}
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//............................................................................
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void BSP_displayPhilStat(uint8_t n, char const *stat) {
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if (stat[0] == (uint8_t)'e') { // is this Philosopher eating?
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LED_ON(n);
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}
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else { // this Philosopher is not eating
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LED_OFF(n);
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}
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QS_BEGIN(PHILO_STAT, AO_Philo[n]) // application-specific record begin
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QS_U8(1, n); // Philosopher number
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QS_STR(stat); // Philosopher status
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QS_END()
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}
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//............................................................................
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void BSP_displayPaused(uint8_t paused) {
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(void)paused;
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}
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//............................................................................
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uint32_t BSP_random(void) { // a very cheap pseudo-random-number generator
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// "Super-Duper" Linear Congruential Generator (LCG)
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// LCG(2^32, 3*7*11*13*23, 0, seed)
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//
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l_rnd = l_rnd * (3U*7U*11U*13U*23U);
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return l_rnd >> 8;
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}
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//............................................................................
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void BSP_randomSeed(uint32_t seed) {
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l_rnd = seed;
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}
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} // namespace DPP
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namespace QP {
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// QF callbacks ==============================================================
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void QF::onStartup(void) {
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// hook the exception handlers from the QF port...
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*(uint32_t volatile *)0x24 = (uint32_t)&QF_undef;
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*(uint32_t volatile *)0x28 = (uint32_t)&QF_swi;
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*(uint32_t volatile *)0x2C = (uint32_t)&QF_pAbort;
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*(uint32_t volatile *)0x30 = (uint32_t)&QF_dAbort;
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*(uint32_t volatile *)0x34 = (uint32_t)&QF_reserved;
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*(uint32_t volatile *)0x38 = (uint32_t)&QV_irq;
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*(uint32_t volatile *)0x3C = (uint32_t)0; // unimplemented!
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AT91C_BASE_AIC->AIC_SVR[AT91C_ID_SYS] = (uint32_t)&DPP::ISR_tick;
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AT91C_BASE_AIC->AIC_SPU = (uint32_t)&DPP::ISR_spur; // spurious IRQ
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AT91C_BASE_AIC->AIC_SMR[AT91C_ID_SYS] =
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(AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | AT91C_AIC_PRIOR_LOWEST);
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AT91C_BASE_AIC->AIC_ICCR = (1 << AT91C_ID_SYS);
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AT91C_BASE_AIC->AIC_IECR = (1 << AT91C_ID_SYS);
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}
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//............................................................................
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void QF_onCleanup(void) {
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}
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//............................................................................
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__ramfunc
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void QV::onIdle(void) { // NOTE: called with interrupts DISABLED
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#ifdef Q_SPY
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// use the idle cycles for QS transmission...
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QF_INT_ENABLE();
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if ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXBUFE) != 0) { // not busy?
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uint16_t nBytes = 0xFFFFU; // get all available bytes
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uint8_t const *block;
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QF_INT_DISABLE();
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if ((block = QS::getBlock(&nBytes)) != (uint8_t *)0) { // new block?
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AT91C_BASE_DBGU->DBGU_TPR = (uint32_t)block;
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AT91C_BASE_DBGU->DBGU_TCR = (uint32_t)nBytes;
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nBytes = 0xFFFFU; // get all available bytes
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if ((block = QS::getBlock(&nBytes)) != (uint8_t *)0) {//another?
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AT91C_BASE_DBGU->DBGU_TNPR = (uint32_t)block;
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AT91C_BASE_DBGU->DBGU_TNCR = (uint32_t)nBytes;
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}
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}
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QF_INT_ENABLE();
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}
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#elif defined NDEBUG // only if not debugging (idle mode hinders debugging)
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AT91C_BASE_PMC->PMC_SCDR = 1;// Power-Management: disable the CPU clock
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// NOTE: an interrupt starts the CPU clock again
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QF_INT_ENABLE(); // enable interrupts as soon as CPU clock starts
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#else
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QF_INT_ENABLE();
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#endif
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}
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//............................................................................
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extern "C" void Q_onAssert(char const * const file, int line) {
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QF_INT_DISABLE(); // disable all interrupts
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for (;;) { // hang here in the for-ever loop
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}
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}
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// QS callbacks ==============================================================
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#ifdef Q_SPY
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uint32_t l_timeOverflow;
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#define QS_BUF_SIZE (2*1024)
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#define BAUD_RATE 115200U
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bool QS::onStartup(void const *arg) {
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static uint8_t qsBuf[QS_BUF_SIZE]; // buffer for Quantum Spy
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AT91PS_DBGU pDBGU = AT91C_BASE_DBGU;
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AT91PS_TC pTC0 = AT91C_BASE_TC0;// TC0 used for timestamp generation
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uint32_t volatile tmp;
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initBuf(qsBuf, sizeof(qsBuf));
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// configure the Debug UART for QSPY output ...
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AT91C_BASE_PIOA->PIO_PDR = AT91C_PA10_DTXD; // configure pin as DTXD
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pDBGU->DBGU_CR = AT91C_US_TXEN; // enable only transmitter
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pDBGU->DBGU_IDR = ~0U; // disable all DBGU interrupts
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pDBGU->DBGU_MR = AT91C_US_PAR_NONE; // no parity bit
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pDBGU->DBGU_BRGR = ((get_MCK_FREQ()/BAUD_RATE + 8) >> 4); // baud rate
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pDBGU->DBGU_PTCR = AT91C_PDC_TXTEN; // enable PDC transfer from DBGU
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// configure Timer/Counter 0 for time measurements ...
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0); // enable clock to TC0
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pTC0->TC_CCR = AT91C_TC_CLKDIS; // TC_CCR: disable Clock Counter
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pTC0->TC_IDR = ~0; // TC_IDR: disable all timer interrupts
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tmp = pTC0->TC_SR; // TC_SR: read
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(void)tmp; // avoid the compiler warning about the unused variable
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// CPCTRG, MCK/32 clock...
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pTC0->TC_CMR = (AT91C_TC_CPCTRG | AT91C_TC_CLKS_TIMER_DIV3_CLOCK);
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pTC0->TC_CCR = AT91C_TC_CLKEN; // TC_CCR: enable Clock Counter
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pTC0->TC_CCR = AT91C_TC_SWTRG; // TC_CCR: start counting
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// setup the QS filters...
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QS_FILTER_ON(QS_QEP_STATE_ENTRY);
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QS_FILTER_ON(QS_QEP_STATE_EXIT);
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QS_FILTER_ON(QS_QEP_STATE_INIT);
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QS_FILTER_ON(QS_QEP_INIT_TRAN);
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QS_FILTER_ON(QS_QEP_INTERN_TRAN);
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QS_FILTER_ON(QS_QEP_TRAN);
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QS_FILTER_ON(QS_QEP_IGNORED);
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QS_FILTER_ON(QS_QEP_DISPATCH);
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QS_FILTER_ON(QS_QEP_UNHANDLED);
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// QS_FILTER_ON(QS_QF_ACTIVE_ADD);
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// QS_FILTER_ON(QS_QF_ACTIVE_REMOVE);
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// QS_FILTER_ON(QS_QF_ACTIVE_SUBSCRIBE);
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// QS_FILTER_ON(QS_QF_ACTIVE_UNSUBSCRIBE);
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// QS_FILTER_ON(QS_QF_ACTIVE_POST_FIFO);
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// QS_FILTER_ON(QS_QF_ACTIVE_POST_LIFO);
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// QS_FILTER_ON(QS_QF_ACTIVE_GET);
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// QS_FILTER_ON(QS_QF_ACTIVE_GET_LAST);
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// QS_FILTER_ON(QS_QF_EQUEUE_INIT);
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// QS_FILTER_ON(QS_QF_EQUEUE_POST_FIFO);
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// QS_FILTER_ON(QS_QF_EQUEUE_POST_LIFO);
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// QS_FILTER_ON(QS_QF_EQUEUE_GET);
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// QS_FILTER_ON(QS_QF_EQUEUE_GET_LAST);
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// QS_FILTER_ON(QS_QF_MPOOL_INIT);
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// QS_FILTER_ON(QS_QF_MPOOL_GET);
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// QS_FILTER_ON(QS_QF_MPOOL_PUT);
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// QS_FILTER_ON(QS_QF_PUBLISH);
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// QS_FILTER_ON(QS_QF_RESERVED8);
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// QS_FILTER_ON(QS_QF_NEW);
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// QS_FILTER_ON(QS_QF_GC_ATTEMPT);
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// QS_FILTER_ON(QS_QF_GC);
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QS_FILTER_ON(QS_QF_TICK);
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// QS_FILTER_ON(QS_QF_TIMEEVT_ARM);
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// QS_FILTER_ON(QS_QF_TIMEEVT_AUTO_DISARM);
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// QS_FILTER_ON(QS_QF_TIMEEVT_DISARM_ATTEMPT);
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// QS_FILTER_ON(QS_QF_TIMEEVT_DISARM);
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// QS_FILTER_ON(QS_QF_TIMEEVT_REARM);
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// QS_FILTER_ON(QS_QF_TIMEEVT_POST);
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// QS_FILTER_ON(QS_QF_TIMEEVT_CTR);
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// QS_FILTER_ON(QS_QF_CRIT_ENTRY);
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// QS_FILTER_ON(QS_QF_CRIT_EXIT);
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// QS_FILTER_ON(QS_QF_ISR_ENTRY);
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// QS_FILTER_ON(QS_QF_ISR_EXIT);
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// QS_FILTER_ON(QS_QF_INT_DISABLE);
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// QS_FILTER_ON(QS_QF_INT_ENABLE);
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// QS_FILTER_ON(QS_QF_ACTIVE_POST_ATTEMPT);
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// QS_FILTER_ON(QS_QF_EQUEUE_POST_ATTEMPT);
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// QS_FILTER_ON(QS_QF_MPOOL_GET_ATTEMPT);
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// QS_FILTER_ON(QS_QF_RESERVED1);
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// QS_FILTER_ON(QS_QF_RESERVED0);
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// QS_FILTER_ON(QS_QK_MUTEX_LOCK);
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// QS_FILTER_ON(QS_QK_MUTEX_UNLOCK);
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// QS_FILTER_ON(QS_QK_SCHEDULE);
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// QS_FILTER_ON(QS_QK_RESERVED1);
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// QS_FILTER_ON(QS_QK_RESERVED0);
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// QS_FILTER_ON(QS_QEP_TRAN_HIST);
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// QS_FILTER_ON(QS_QEP_TRAN_EP);
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// QS_FILTER_ON(QS_QEP_TRAN_XP);
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// QS_FILTER_ON(QS_QEP_RESERVED1);
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// QS_FILTER_ON(QS_QEP_RESERVED0);
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QS_FILTER_ON(QS_SIG_DICT);
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QS_FILTER_ON(QS_OBJ_DICT);
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QS_FILTER_ON(QS_FUN_DICT);
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QS_FILTER_ON(QS_USR_DICT);
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QS_FILTER_ON(QS_EMPTY);
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QS_FILTER_ON(QS_RESERVED3);
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QS_FILTER_ON(QS_RESERVED2);
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QS_FILTER_ON(QS_TEST_RUN);
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QS_FILTER_ON(QS_TEST_FAIL);
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QS_FILTER_ON(QS_ASSERT_FAIL);
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return true; // indicate successfull QS initialization
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}
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//............................................................................
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void QS::onCleanup(void) {
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}
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//............................................................................
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void QS::onFlush(void) {
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uint16_t nBytes = 0xFFFFU; // get all available bytes
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uint8_t const *block;
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while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXBUFE) == 0) { // busy?
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}
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if ((block = getBlock(&nBytes)) != (uint8_t *)0) {
|
||
|
AT91C_BASE_DBGU->DBGU_TPR = (uint32_t)block;
|
||
|
AT91C_BASE_DBGU->DBGU_TCR = (uint32_t)nBytes;
|
||
|
nBytes = 0xFFFFU; // get all available bytes
|
||
|
if ((block = getBlock(&nBytes)) != (uint8_t *)0) {
|
||
|
AT91C_BASE_DBGU->DBGU_TNPR = (uint32_t)block;
|
||
|
AT91C_BASE_DBGU->DBGU_TNCR = (uint32_t)nBytes;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
//............................................................................
|
||
|
// NOTE: getTime is invoked within a critical section (inetrrupts disabled)
|
||
|
__ramfunc
|
||
|
uint32_t QS::onGetTime(void) {
|
||
|
AT91PS_TC pTC0 = AT91C_BASE_TC0; // TC0 used for timestamp generation
|
||
|
uint32_t now = pTC0->TC_CV; // get the counter value
|
||
|
// did the timer overflow 0xFFFF?
|
||
|
if ((pTC0->TC_SR & AT91C_TC_COVFS) != 0) {
|
||
|
l_timeOverflow += (uint32_t)0x10000; // account for the overflow
|
||
|
}
|
||
|
return l_timeOverflow + now;
|
||
|
}
|
||
|
#endif // Q_SPY
|
||
|
//----------------------------------------------------------------------------
|
||
|
|
||
|
} // namespace QP
|