mirror of
https://github.com/QuantumLeaps/qpcpp.git
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172 lines
4.7 KiB
C
172 lines
4.7 KiB
C
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/* ============================================================================
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* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
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*
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* Use of this software is controlled by the terms and conditions found in the
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* license agreement under which this software has been supplied.
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* ============================================================================
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*/
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/** @file csl_pllAux.h
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*
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* @brief PLL functional layer inline header file
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* -Extra Inline functions
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*
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* Path: \(CSLPATH)/inc
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*/
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/* ============================================================================
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* Revision History
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* ================
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* 21-Aug-2008 Created
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* ============================================================================
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*/
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#ifndef _CSL_PLLAUX_H_
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#define _CSL_PLLAUX_H_
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#include <csl_pll.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup CSL_PLL_FUNCTION
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@{*/
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/** ============================================================================
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* @n@b PLL_getTestLockMonStatus
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*
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* @b Description
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* @n This API is used to get the status of TEST LOCK bit in PLL CNTL2 reg
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*
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* @b Arguments
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* @verbatim
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hPll Handle to the pll
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@endverbatim
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*
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* <b> Return Value </b> Bool
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* @li TRUE - Test lock bit is set
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*
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* @li FALSE - Test lock bit is not set.
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*
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* <b> Pre Condition </b>
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* @n PLL_init and PLL_config should be called successfully.
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*
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* <b> Post Condition </b>
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* @n None
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*
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* @b Modifies
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* @n hPll variable
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*
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* @b Example
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* @verbatim
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CSL_Status status;
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Bool bStatus;
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PLL_Obj pllObj;
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PLL_Config configInfo;
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PLL_Handle hPll;
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Uint32 pllInstId;
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pllInstId = 0;
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status = PLL_init(&pllObj,pllInstId);
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hPll = &pllObj;
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.......
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Configure the PLL for 12.288MHz
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configInfo.PLLCNTL1 = 0x82ed; //Give proper value
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configInfo.PLLCNTL2 = 0x8000;
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configInfo.PLLINCNTL = 0x0806;
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configInfo.PLLOUTCNTL = 0x0200;
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status = PLL_config(hPll, &configInfo);
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bStatus = PLL_getTestLockMonStatus(hPll);
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@endverbatim
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* ============================================================================
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*/
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static inline
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Bool PLL_getTestLockMonStatus(PLL_Handle hPll)
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{
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Uint16 TstLckMon = 0;
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TstLckMon = ((hPll->sysAddr->CGCR2 & (0x0008u)) >> (0x0003u));
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if( TstLckMon )
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return TRUE;
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return FALSE;
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}
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/** ============================================================================
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* @n@b PLL_getConfig
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*
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* @b Description
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* @n This API is used to retrieve the current configuration of the pll.
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*
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* @b Arguments
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* @verbatim
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hPll Handle to the pll
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@endverbatim
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*
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* <b> Return Value </b> CSL_Status
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* @li CSL_SOK - PLL config information is available
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*
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* @li CSL_ESYS_BADHANDLE - Handle is invalid
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*
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* @li CSL_ESYS_INVPARAMS - Pointer to the config structure is NULL
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*
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* <b> Pre Condition </b>
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* @n PLL_init and PLL_config should be called successfully.
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*
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* <b> Post Condition </b>
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* @n None
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*
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* @b Modifies
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* @n pConfig variable
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*
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* @b Example
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* @verbatim
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CSL_Status status;
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Bool bStatus;
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PLL_Obj pllObj;
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PLL_Config configInfo;
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PLL_Config gconfig;
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PLL_Handle hPll;
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Uint32 pllInstId;
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pllInstId = 0;
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status = PLL_init(&pllObj,pllInstId);
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hPll = &pllObj;
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.......
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Configure the PLL for 12.288MHz
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configInfo.PLLCNTL1 = 0x82ed;
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configInfo.PLLINCNTL = 0x8000;
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configInfo.PLLCNTL2 = 0x0806;
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configInfo.PLLOUTCNTL = 0x0200;
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status = PLL_config(hPll, &configInfo);
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status = PLL_getConfig(hPll,&gconfig);
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@endverbatim
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* ============================================================================
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*/
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static inline
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CSL_Status PLL_getConfig(PLL_Handle hPll,PLL_Config *pConfig)
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{
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CSL_Status status = CSL_SOK;
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if(NULL == hPll)
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{
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status = CSL_ESYS_BADHANDLE;
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return status;
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}
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if(NULL == pConfig)
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{
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status = CSL_ESYS_INVPARAMS;
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return status;
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}
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pConfig->PLLCNTL1 = hPll->sysAddr->CGCR1;
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pConfig->PLLCNTL2 = hPll->sysAddr->CGCR2;
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pConfig->PLLINCNTL = hPll->sysAddr->CGICR;
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pConfig->PLLOUTCNTL = hPll->sysAddr->CGOCR;
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return status;
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}
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/**
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@} */
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#endif// _CSL_PLLAUX_H_
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