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added FreeRTOS port

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Quantum Leaps 2014-10-02 10:40:48 -04:00
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examples/arm-cm/vanilla/iar/game_ek-lm3s811/.game Normal file
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examples/freertos/iar/blinky_ek-tm4c123gxl/FreeRTOSConfig.h Normal file
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/*
FreeRTOS config file for the "Blinky" demo on EK-TM4C123GXL board
Quantum Leaps, LLC, www.state-machine.com
*/
/*
FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/* Ensure stdint is only used by the compiler, and not the assembler. */
#ifdef __ICCARM__
#include <stdint.h>
extern uint32_t SystemCoreClock;
/* assertion failure handler prototype */
extern void assert_failed(char const *file, int line);
#endif
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ( ( TickType_t ) 100 )
#define configMAX_PRIORITIES ( 32 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 4 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 8 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 0
#define configQUEUE_REGISTRY_SIZE 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 0
#define configUSE_MALLOC_FAILED_HOOK 0
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 0
#define configGENERATE_RUN_TIME_STATS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 0
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 0
#define INCLUDE_vTaskDelay 0
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 3 /* 7 priority levels */
#endif
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 3
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY 0xFF
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
#define configASSERT( x ) if( ( x ) == 0 ) { assert_failed(__FILE__, __LINE__); }
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
#endif /* FREERTOS_CONFIG_H */

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examples/freertos/iar/blinky_ek-tm4c123gxl/README.txt Normal file
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The project file provided with this example assumes that
the environment variables QPC and FREERTOS are defined and
that they point to the location of the QP/C framework and
FreeRTOS, respectively.
For example, assuming that you have installed QP/C into the
directory C:\qp\qpc and FreeRTOS to C:\software\FreeRTOSV8.1.2
you should define the environment variable QPC to C:\qp\qpc
and the environment variable FREERTOS to C:\software\FreeRTOSV8.1.2.
Editing the Environment Variables on Windows
--------------------------------------------
Open the Windows Explorer and right-click on the Computer
icon. Then select Properties from the pop-up menu. This opens
a window with the basic information about your computer. In the
left panel of this window, click on "Advanced system settings".
This opens the dialog "System Properties". Click the
"Environment Variables..." button.
To add a new environment variable, click the "New..." button
in the System variables section and provide the variable name
(e.g., QPC) and value (e.g., C:\qp\qpc).
****
NOTE: After updating envrinment variables, you shold reboot your
computer so that all applications, such as IAR Embedded Workbench
can pick up the changes.
****

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examples/freertos/iar/blinky_ek-tm4c123gxl/blinky.cpp Normal file
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//****************************************************************************
// Product: Simple Blinky example
// Last Updated for Version: 5.3.1
// Date of the Last Update: 2014-09-29
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, LLC. state-machine.com.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Web: http://www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#include "qp_port.h"
#include "bsp.h"
using namespace QP;
//Q_DEFINE_THIS_FILE
//............................................................................
enum BlinkySignals {
TIMEOUT_SIG = QP::Q_USER_SIG, // the periodic timeout signal
};
//............................................................................
class Blinky : public QActive {
private:
QTimeEvt m_timeEvt;
public:
Blinky();
protected:
static QState initial(Blinky * const me, QEvt const * const e);
static QState off(Blinky * const me, QEvt const * const e);
static QState on(Blinky * const me, QEvt const * const e);
};
//............................................................................
Blinky::Blinky()
: QActive(Q_STATE_CAST(&Blinky::initial)),
m_timeEvt(this, TIMEOUT_SIG, 0U)
{
// empty
}
// HSM definition ------------------------------------------------------------
QState Blinky::initial(Blinky * const me, QEvt const * const e) {
(void)e; // avoid compiler warning about unused argument
// arm the time event to expire in half a second and every half second
me->m_timeEvt.armX(BSP_TICKS_PER_SEC/2U, BSP_TICKS_PER_SEC/2U);
return Q_TRAN(&Blinky::off);
}
//............................................................................
QState Blinky::off(Blinky * const me, QEvt const * const e) {
QState status;
switch (e->sig) {
case Q_ENTRY_SIG: {
BSP_ledOff();
status = Q_HANDLED();
break;
}
case TIMEOUT_SIG: {
status = Q_TRAN(&Blinky::on);
break;
}
default: {
status = Q_SUPER(&QHsm::top);
break;
}
}
return status;
}
//............................................................................
QState Blinky::on(Blinky * const me, QEvt const * const e) {
QState status;
switch (e->sig) {
case Q_ENTRY_SIG: {
BSP_ledOn();
status = Q_HANDLED();
break;
}
case TIMEOUT_SIG: {
status = Q_TRAN(&Blinky::off);
break;
}
default: {
status = Q_SUPER(&QHsm::top);
break;
}
}
return status;
}
// test harness ==============================================================
// Local-scope objects -------------------------------------------------------
static Blinky l_blinky; // the Blinky active object
static QEvt const *l_blinkyQSto[10]; // Event queue storage for Blinky
//............................................................................
int main() {
BSP_init(); // initialize the Board Support Package
QF::init(); // initialize the framework and the underlying RT kernel
// publish-subscribe not used, no call to QF::psInit()
// dynamic event allocation not used, no call to QF::poolInit()
// instantiate and start the active objects...
l_blinky.start(1U,
l_blinkyQSto, Q_DIM(l_blinkyQSto),
(void *)0, 512U);
return QF::run(); // run the QF application
}

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examples/freertos/iar/blinky_ek-tm4c123gxl/blinky.ewp Normal file
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examples/freertos/iar/blinky_ek-tm4c123gxl/blinky.eww Normal file
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\blinky.ewp</path>
</project>
<batchBuild/>
</workspace>

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examples/freertos/iar/blinky_ek-tm4c123gxl/blinky.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 1024;
define symbol __ICFEDIT_size_heap__ = 0;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place at start of RAM_region {block CSTACK };
place in RAM_region { readwrite, block HEAP };

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//****************************************************************************
// Product: Simple Blinky example, Tiva EK-TM4C123GXL, Vanilla kernel
// Last Updated for Version: 5.3.1
// Date of the Last Update: 2014-09-29
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, LLC. state-machine.com.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Web: http://www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#include "qp_port.h"
#include "bsp.h"
extern "C" {
#include "tm4c_cmsis.h" // Tiva-C CMSIS-compliant interface
#include "sysctl.h"
#include "gpio.h"
#include "rom.h"
}
using namespace QP;
Q_DEFINE_THIS_FILE
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
//
enum KernelUnawareISRs { // see NOTE1
// ...
MAX_KERNEL_UNAWARE_CMSIS_PRI // keep always last
};
// "kernel-unaware" interrupts can't overlap "kernel-aware" interrupts
Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI
<= configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
enum KernelAwareISRs {
SYSTICK_PRIO = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY, // see NOTE1
// ...
MAX_KERNEL_AWARE_CMSIS_PRI // keep always last
};
// "kernel-aware" interrupts should not overlap the PendSV priority
Q_ASSERT_COMPILE(MAX_KERNEL_AWARE_CMSIS_PRI <= (0xFF >>(8-__NVIC_PRIO_BITS)));
uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
// LEDs and Switches of the EK-TM4C123GXL board ..............................
#define LED_RED (1U << 1)
#define LED_GREEN (1U << 3)
#define LED_BLUE (1U << 2)
#define USR_SW1 (1U << 4)
#define USR_SW2 (1U << 0)
//............................................................................
extern "C" void vApplicationTickHook(void) {
QF_CRIT_STAT_TYPE intStat;
BaseType_t lHigherPriorityTaskWoken = pdFALSE;
QF_ISR_ENTRY(intStat); // <=== inform QF about ISR entry
QF::TICK_X(0U, (void *)0); // process all armed time events
QF_ISR_EXIT(intStat, lHigherPriorityTaskWoken); // <=== ISR exit
// yield only when needed...
if (lHigherPriorityTaskWoken != pdFALSE) {
vTaskMissedYield();
}
}
//............................................................................
extern "C" void vApplicationIdleHook(void) {
#ifdef NDEBUG
// Put the CPU and peripherals to the low-power mode.
// you might need to customize the clock management for your application,
// see the datasheet for your particular Cortex-M MCU.
//
__WFI(); // Wait-For-Interrupt
#endif
}
//............................................................................
extern "C" void vApplicationStackOverflowHook(TaskHandle_t, char *) {
Q_ERROR();
}
//............................................................................
void BSP_init(void) {
// Enable the floating-point unit
SCB->CPACR |= (0xFU << 20);
// Enable lazy stacking for interrupt handlers. This allows FPU
// instructions to be used within interrupt handlers, but at the
// expense of extra stack and CPU usage.
//
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
// Set the clocking to run directly from the crystal
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC
| SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);
SystemCoreClock = ROM_SysCtlClockGet(); // get the actual clock
// enable clock to the peripherals used by the application
SYSCTL->RCGC2 |= (1U << 5); // enable clock to GPIOF
__NOP(); // wait after enabling clocks
__NOP();
__NOP();
// configure the LEDs...
GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE); // set direction: output
GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); // digital enable
GPIOF->DATA_Bits[LED_RED] = 0; // turn the LED off
GPIOF->DATA_Bits[LED_GREEN] = 0; // turn the LED off
GPIOF->DATA_Bits[LED_BLUE] = 0; // turn the LED off
}
//............................................................................
void BSP_ledOff() {
GPIOF->DATA_Bits[LED_GREEN] = 0U;
}
//............................................................................
void BSP_ledOn() {
GPIOF->DATA_Bits[LED_GREEN] = LED_GREEN;
}
//............................................................................
void QF::onStartup(void) {
// set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate
SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);
// assing all priority bits for preemption-prio. and none to sub-prio.
NVIC_SetPriorityGrouping(0U);
// set priorities of ALL ISRs used in the system, see NOTE00
//
// !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
//
NVIC_SetPriority(SysTick_IRQn, SYSTICK_PRIO);
// ...
// enable IRQs...
}
//............................................................................
void QF::onCleanup(void) {
}
//............................................................................
extern "C" void Q_onAssert(char const Q_ROM * const file, int_t line) {
assert_failed(file, line);
}
//............................................................................
// error routine that is called if the CMSIS library encounters an error
extern "C" void assert_failed(char const *file, int line) {
(void)file; // avoid compiler warning
(void)line; // avoid compiler warning
QF_INT_DISABLE(); // make sure that all interrupts are disabled
ROM_SysCtlReset(); // reset the system
}
//****************************************************************************
// NOTE00:
// The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
// ISR priority that is disabled by the QF framework. The value is suitable
// for the NVIC_SetPriority() CMSIS function.
//
// Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e.,
// with the numerical values of priorities equal or higher than
// QF_AWARE_ISR_CMSIS_PRI) are allowed to call any QF services. These ISRs
// are "QF-aware".
//
// Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority
// level (i.e., with the numerical values of priorities less than
// QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel.
// Such "QF-unaware" ISRs cannot call any QF services. The only mechanism
// by which a "QF-unaware" ISR can communicate with the QF framework is by
// triggering a "QF-aware" ISR, which can post/publish events.
//
// NOTE01:
// The QF::onIdle() callback is called with interrupts disabled, because the
// determination of the idle condition might change by any interrupt posting
// an event. QF::onIdle() must internally enable interrupts, ideally
// atomically with putting the CPU to the power-saving mode.
//

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//****************************************************************************
// Product: Simple Blinky example
// Last Updated for Version: 5.3.1
// Date of the Last Update: 2014-09-29
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, LLC. state-machine.com.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Web: http://www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#ifndef bsp_h
#define bsp_h
uint32_t const BSP_TICKS_PER_SEC = static_cast<uint32_t>(configTICK_RATE_HZ);
void BSP_init(void);
void BSP_ledOff(void);
void BSP_ledOn(void);
#endif // bsp_h

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//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfnIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinConfigure(unsigned long ulPinConfig);
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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examples/freertos/iar/blinky_ek-tm4c123gxl/startup_tm4c.c Normal file
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/*****************************************************************************
// This TM4C startup file has been adapted from startup_ewarm.c
// Quantum Leaps on 28-Jul-2014
// www.state-machine.com
*****************************************************************************/
//*****************************************************************************
//
// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench,
// version 5.
//
// Copyright (c) 2012-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2.0.1.11577 of the EK-TM4C123GXL Firmware Package.
//
//*****************************************************************************
#include "tm4c_cmsis.h"
/* Enable the IAR extensions for this source file */
#pragma language=extended
/* Function prototypes -----------------------------------------------------*/
void __iar_program_start(void); /* IAR startup code */
void Spurious_Handler(void); /* spurious exception/interrupt handler */
/* CSTACK section limits (created by the IAR linker) -----------------------*/
extern int CSTACK$$Base; /* symbol created by the IAR linker */
extern int CSTACK$$Limit; /* symbol created by the IAR linker */
/* exception and interrupt vector table ------------------------------------*/
typedef void (*handler)(void); /* pointer to handler function type */
/*..........................................................................*/
__root handler const __vector_table[] @ ".intvec" = {
(handler)&CSTACK$$Limit, /* The initial stack pointer */
&__iar_program_start, /* Reset Handler */
&NMI_Handler, /* NMI Handler */
&HardFault_Handler, /* Hard Fault Handler */
&MemManage_Handler, /* MPU Fault Handler */
&BusFault_Handler, /* Bus Fault Handler */
&UsageFault_Handler, /* Usage Fault Handler */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&SVC_Handler, /* SVCall Handler */
&DebugMon_Handler, /* Debug Monitor Handler */
&Spurious_Handler, /* Reserved */
&PendSV_Handler, /* PendSV Handler */
&SysTick_Handler, /* SysTick Handler */
/* external interrupts (IRQs) ... */
&GPIOPortA_IRQHandler, /* GPIO Port A */
&GPIOPortB_IRQHandler, /* GPIO Port B */
&GPIOPortC_IRQHandler, /* GPIO Port C */
&GPIOPortD_IRQHandler, /* GPIO Port D */
&GPIOPortE_IRQHandler, /* GPIO Port E */
&UART0_IRQHandler, /* UART0 Rx and Tx */
&UART1_IRQHandler, /* UART1 Rx and Tx */
&SSI0_IRQHandler, /* SSI0 Rx and Tx */
&I2C0_IRQHandler, /* I2C0 Master and Slave */
&PWMFault_IRQHandler, /* PWM Fault */
&PWMGen0_IRQHandler, /* PWM Generator 0 */
&PWMGen1_IRQHandler, /* PWM Generator 1 */
&PWMGen2_IRQHandler, /* PWM Generator 2 */
&QEI0_IRQHandler, /* Quadrature Encoder 0 */
&ADCSeq0_IRQHandler, /* ADC Sequence 0 */
&ADCSeq1_IRQHandler, /* ADC Sequence 1 */
&ADCSeq2_IRQHandler, /* ADC Sequence 2 */
&ADCSeq3_IRQHandler, /* ADC Sequence 3 */
&Watchdog_IRQHandler, /* Watchdog timer */
&Timer0A_IRQHandler, /* Timer 0 subtimer A */
&Timer0B_IRQHandler, /* Timer 0 subtimer B */
&Timer1A_IRQHandler, /* Timer 1 subtimer A */
&Timer1B_IRQHandler, /* Timer 1 subtimer B */
&Timer2A_IRQHandler, /* Timer 2 subtimer A */
&Timer2B_IRQHandler, /* Timer 2 subtimer B */
&Comp0_IRQHandler, /* Analog Comparator 0 */
&Comp1_IRQHandler, /* Analog Comparator 1 */
&Comp2_IRQHandler, /* Analog Comparator 2 */
&SysCtrl_IRQHandler, /* System Control (PLL,OSC,BO) */
&FlashCtrl_IRQHandler, /* FLASH Control */
&GPIOPortF_IRQHandler, /* GPIO Port F */
&GPIOPortG_IRQHandler, /* GPIO Port G */
&GPIOPortH_IRQHandler, /* GPIO Port H */
&UART2_IRQHandler, /* UART2 Rx and Tx */
&SSI1_IRQHandler , /* SSI1 Rx and Tx */
&Timer3A_IRQHandler, /* Timer 3 subtimer A */
&Timer3B_IRQHandler, /* Timer 3 subtimer B */
&I2C1_IRQHandler, /* I2C1 Master and Slave */
&QEI1_IRQHandler, /* Quadrature Encoder 1 */
&CAN0_IRQHandler, /* CAN0 */
&CAN1_IRQHandler, /* CAN1 */
&CAN2_IRQHandler, /* CAN2 */
&Spurious_Handler, /* Reserved */
&Hibernate_IRQHandler, /* Hibernate */
&USB0_IRQHandler, /* USB0 */
&PWMGen3_IRQHandler, /* PWM Generator 3 */
&uDMAST_IRQHandler, /* uDMA Software Transfer */
&uDMAError_IRQHandler, /* uDMA Error */
&ADC1Seq0_IRQHandler, /* ADC1 Sequence 0 */
&ADC1Seq1_IRQHandler, /* ADC1 Sequence 1 */
&ADC1Seq2_IRQHandler, /* ADC1 Sequence 2 */
&ADC1Seq3_IRQHandler, /* ADC1 Sequence 3 */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&GPIOPortJ_IRQHandler, /* GPIO Port J */
&GPIOPortK_IRQHandler, /* GPIO Port K */
&GPIOPortL_IRQHandler, /* GPIO Port L */
&SSI2_IRQHandler, /* SSI2 Rx and Tx */
&SSI3_IRQHandler, /* SSI3 Rx and Tx */
&UART3_IRQHandler, /* UART3 Rx and Tx */
&UART4_IRQHandler, /* UART4 Rx and Tx */
&UART5_IRQHandler, /* UART5 Rx and Tx */
&UART6_IRQHandler, /* UART6 Rx and Tx */
&UART7_IRQHandler, /* UART7 Rx and Tx */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&I2C2_IRQHandler, /* I2C2 Master and Slave */
&I2C3_IRQHandler, /* I2C3 Master and Slave */
&Timer4A_IRQHandler, /* Timer 4 subtimer A */
&Timer4B_IRQHandler, /* Timer 4 subtimer B */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Timer5A_IRQHandler, /* Timer 5 subtimer A */
&Timer5B_IRQHandler, /* Timer 5 subtimer B */
&WideTimer0A_IRQHandler, /* Wide Timer 0 subtimer A */
&WideTimer0B_IRQHandler, /* Wide Timer 0 subtimer B */
&WideTimer1A_IRQHandler, /* Wide Timer 1 subtimer A */
&WideTimer1B_IRQHandler, /* Wide Timer 1 subtimer B */
&WideTimer2A_IRQHandler, /* Wide Timer 2 subtimer A */
&WideTimer2B_IRQHandler, /* Wide Timer 2 subtimer B */
&WideTimer3A_IRQHandler, /* Wide Timer 3 subtimer A */
&WideTimer3B_IRQHandler, /* Wide Timer 3 subtimer B */
&WideTimer4A_IRQHandler, /* Wide Timer 4 subtimer A */
&WideTimer4B_IRQHandler, /* Wide Timer 4 subtimer B */
&WideTimer5A_IRQHandler, /* Wide Timer 5 subtimer A */
&WideTimer5B_IRQHandler, /* Wide Timer 5 subtimer B */
&FPU_IRQHandler, /* FPU */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&I2C4_IRQHandler, /* I2C4 Master and Slave */
&I2C5_IRQHandler, /* I2C5 Master and Slave */
&GPIOPortM_IRQHandler, /* GPIO Port M */
&GPIOPortN_IRQHandler, /* GPIO Port N */
&QEI2_IRQHandler, /* Quadrature Encoder 2 */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&GPIOPortP0_IRQHandler, /* GPIO Port P (Summary or P0) */
&GPIOPortP1_IRQHandler, /* GPIO Port P1 */
&GPIOPortP2_IRQHandler, /* GPIO Port P2 */
&GPIOPortP3_IRQHandler, /* GPIO Port P3 */
&GPIOPortP4_IRQHandler, /* GPIO Port P4 */
&GPIOPortP5_IRQHandler, /* GPIO Port P5 */
&GPIOPortP6_IRQHandler, /* GPIO Port P6 */
&GPIOPortP7_IRQHandler, /* GPIO Port P7 */
&GPIOPortQ0_IRQHandler, /* GPIO Port Q (Summary or Q0) */
&GPIOPortQ1_IRQHandler, /* GPIO Port Q1 */
&GPIOPortQ2_IRQHandler, /* GPIO Port Q2 */
&GPIOPortQ3_IRQHandler, /* GPIO Port Q3 */
&GPIOPortQ4_IRQHandler, /* GPIO Port Q4 */
&GPIOPortQ5_IRQHandler, /* GPIO Port Q5 */
&GPIOPortQ6_IRQHandler, /* GPIO Port Q6 */
&GPIOPortQ7_IRQHandler, /* GPIO Port Q7 */
&GPIOPortR_IRQHandler, /* GPIO Port R */
&GPIOPortS_IRQHandler, /* GPIO Port S */
&PWM1Gen0_IRQHandler, /* PWM 1 Generator 0 */
&PWM1Gen1_IRQHandler, /* PWM 1 Generator 1 */
&PWM1Gen2_IRQHandler, /* PWM 1 Generator 2 */
&PWM1Gen3_IRQHandler, /* PWM 1 Generator 3 */
&PWM1Fault_IRQHandler /* PWM 1 Fault */
};
/* exception handlers ------------------------------------------------------*/
/*..........................................................................*/
__stackless void NMI_Handler(void) {
assert_failed("NMI", __LINE__); /* should never return! */
}
/*..........................................................................*/
__stackless void MemManage_Handler(void) {
assert_failed("MemManage", __LINE__); /* should never return! */
}
/*..........................................................................*/
__stackless void HardFault_Handler(void) {
unsigned old_sp = __get_SP();
if (old_sp < (unsigned)&CSTACK$$Base) { /* stack overflow? */
__set_SP((unsigned)&CSTACK$$Limit); /* initial stack pointer */
assert_failed("StackOverflow", old_sp); /* should never return! */
}
else {
assert_failed("HardFault", __LINE__); /* should never return! */
}
}
/*..........................................................................*/
__stackless void BusFault_Handler(void) {
assert_failed("BusFault", __LINE__); /* should never return! */
}
/*..........................................................................*/
__stackless void UsageFault_Handler(void) {
assert_failed("UsageFault", __LINE__); /* should never return! */
}
/*..........................................................................*/
__stackless void Spurious_Handler(void) {
assert_failed("Spurious", __LINE__); /* should never return! */
}
/*----------------------------------------------------------------------------
* Weak aliases for each Exception handler to the Spurious_Handler.
*/
#pragma weak SVC_Handler = Spurious_Handler
#pragma weak DebugMon_Handler = Spurious_Handler
#pragma weak PendSV_Handler = Spurious_Handler
#pragma weak SysTick_Handler = Spurious_Handler
#pragma weak GPIOPortA_IRQHandler = Spurious_Handler
#pragma weak GPIOPortB_IRQHandler = Spurious_Handler
#pragma weak GPIOPortC_IRQHandler = Spurious_Handler
#pragma weak GPIOPortD_IRQHandler = Spurious_Handler
#pragma weak GPIOPortE_IRQHandler = Spurious_Handler
#pragma weak UART0_IRQHandler = Spurious_Handler
#pragma weak UART1_IRQHandler = Spurious_Handler
#pragma weak SSI0_IRQHandler = Spurious_Handler
#pragma weak I2C0_IRQHandler = Spurious_Handler
#pragma weak PWMFault_IRQHandler = Spurious_Handler
#pragma weak PWMGen0_IRQHandler = Spurious_Handler
#pragma weak PWMGen1_IRQHandler = Spurious_Handler
#pragma weak PWMGen2_IRQHandler = Spurious_Handler
#pragma weak QEI0_IRQHandler = Spurious_Handler
#pragma weak ADCSeq0_IRQHandler = Spurious_Handler
#pragma weak ADCSeq1_IRQHandler = Spurious_Handler
#pragma weak ADCSeq2_IRQHandler = Spurious_Handler
#pragma weak ADCSeq3_IRQHandler = Spurious_Handler
#pragma weak Watchdog_IRQHandler = Spurious_Handler
#pragma weak Timer0A_IRQHandler = Spurious_Handler
#pragma weak Timer0B_IRQHandler = Spurious_Handler
#pragma weak Timer1A_IRQHandler = Spurious_Handler
#pragma weak Timer1B_IRQHandler = Spurious_Handler
#pragma weak Timer2A_IRQHandler = Spurious_Handler
#pragma weak Timer2B_IRQHandler = Spurious_Handler
#pragma weak Comp0_IRQHandler = Spurious_Handler
#pragma weak Comp1_IRQHandler = Spurious_Handler
#pragma weak Comp2_IRQHandler = Spurious_Handler
#pragma weak SysCtrl_IRQHandler = Spurious_Handler
#pragma weak FlashCtrl_IRQHandler = Spurious_Handler
#pragma weak GPIOPortF_IRQHandler = Spurious_Handler
#pragma weak GPIOPortG_IRQHandler = Spurious_Handler
#pragma weak GPIOPortH_IRQHandler = Spurious_Handler
#pragma weak UART2_IRQHandler = Spurious_Handler
#pragma weak SSI1_IRQHandler = Spurious_Handler
#pragma weak Timer3A_IRQHandler = Spurious_Handler
#pragma weak Timer3B_IRQHandler = Spurious_Handler
#pragma weak I2C1_IRQHandler = Spurious_Handler
#pragma weak QEI1_IRQHandler = Spurious_Handler
#pragma weak CAN0_IRQHandler = Spurious_Handler
#pragma weak CAN1_IRQHandler = Spurious_Handler
#pragma weak CAN2_IRQHandler = Spurious_Handler
#pragma weak Hibernate_IRQHandler = Spurious_Handler
#pragma weak USB0_IRQHandler = Spurious_Handler
#pragma weak PWMGen3_IRQHandler = Spurious_Handler
#pragma weak uDMAST_IRQHandler = Spurious_Handler
#pragma weak uDMAError_IRQHandler = Spurious_Handler
#pragma weak ADC1Seq0_IRQHandler = Spurious_Handler
#pragma weak ADC1Seq1_IRQHandler = Spurious_Handler
#pragma weak ADC1Seq2_IRQHandler = Spurious_Handler
#pragma weak ADC1Seq3_IRQHandler = Spurious_Handler
#pragma weak I2S0_IRQHandler = Spurious_Handler
#pragma weak EBI0_IRQHandler = Spurious_Handler
#pragma weak GPIOPortJ_IRQHandler = Spurious_Handler
#pragma weak GPIOPortK_IRQHandler = Spurious_Handler
#pragma weak GPIOPortL_IRQHandler = Spurious_Handler
#pragma weak SSI2_IRQHandler = Spurious_Handler
#pragma weak SSI3_IRQHandler = Spurious_Handler
#pragma weak UART3_IRQHandler = Spurious_Handler
#pragma weak UART4_IRQHandler = Spurious_Handler
#pragma weak UART5_IRQHandler = Spurious_Handler
#pragma weak UART6_IRQHandler = Spurious_Handler
#pragma weak UART7_IRQHandler = Spurious_Handler
#pragma weak I2C2_IRQHandler = Spurious_Handler
#pragma weak I2C3_IRQHandler = Spurious_Handler
#pragma weak Timer4A_IRQHandler = Spurious_Handler
#pragma weak Timer4B_IRQHandler = Spurious_Handler
#pragma weak Timer5A_IRQHandler = Spurious_Handler
#pragma weak Timer5B_IRQHandler = Spurious_Handler
#pragma weak WideTimer0A_IRQHandler = Spurious_Handler
#pragma weak WideTimer0B_IRQHandler = Spurious_Handler
#pragma weak WideTimer1A_IRQHandler = Spurious_Handler
#pragma weak WideTimer1B_IRQHandler = Spurious_Handler
#pragma weak WideTimer2A_IRQHandler = Spurious_Handler
#pragma weak WideTimer2B_IRQHandler = Spurious_Handler
#pragma weak WideTimer3A_IRQHandler = Spurious_Handler
#pragma weak WideTimer3B_IRQHandler = Spurious_Handler
#pragma weak WideTimer4A_IRQHandler = Spurious_Handler
#pragma weak WideTimer4B_IRQHandler = Spurious_Handler
#pragma weak WideTimer5A_IRQHandler = Spurious_Handler
#pragma weak WideTimer5B_IRQHandler = Spurious_Handler
#pragma weak FPU_IRQHandler = Spurious_Handler
#pragma weak PECI0_IRQHandler = Spurious_Handler
#pragma weak LPC0_IRQHandler = Spurious_Handler
#pragma weak I2C4_IRQHandler = Spurious_Handler
#pragma weak I2C5_IRQHandler = Spurious_Handler
#pragma weak GPIOPortM_IRQHandler = Spurious_Handler
#pragma weak GPIOPortN_IRQHandler = Spurious_Handler
#pragma weak QEI2_IRQHandler = Spurious_Handler
#pragma weak Fan0_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP0_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP1_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP2_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP3_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP4_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP5_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP6_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP7_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ0_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ1_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ2_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ3_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ4_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ5_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ6_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ7_IRQHandler = Spurious_Handler
#pragma weak GPIOPortR_IRQHandler = Spurious_Handler
#pragma weak GPIOPortS_IRQHandler = Spurious_Handler
#pragma weak PWM1Gen0_IRQHandler = Spurious_Handler
#pragma weak PWM1Gen1_IRQHandler = Spurious_Handler
#pragma weak PWM1Gen2_IRQHandler = Spurious_Handler
#pragma weak PWM1Gen3_IRQHandler = Spurious_Handler
#pragma weak PWM1Fault_IRQHandler = Spurious_Handler

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//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
typedef unsigned char tBoolean;
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#ifndef DEPRECATED
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#endif
#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
#ifndef DEPRECATED
#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
#endif
#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#endif
#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
#ifndef DEPRECATED
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
#endif
#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
#endif
#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
#endif
#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
#define SYSCTL_PERIPH_ETH 0x20105000 // Ethernet
#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0
#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1
#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0
#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1
#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2
#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
#define SYSCTL_PERIPH2_EPI0 0xf0001000 // EPI0
#define SYSCTL_PERIPH2_ETH 0xf0002c00 // ETH
#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A
#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B
#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C
#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D
#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E
#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F
#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G
#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H
#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J
#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module
#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0
#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1
#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
#define SYSCTL_PERIPH2_I2S0 0xf0002400 // I2S0
#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0
#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0
#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0
#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0
#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1
#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0
#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1
#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0
#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1
#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2
#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3
#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0
#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1
#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2
#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA
#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0
#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0
#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1
#define SYSCTL_PERIPH2_HIBERNATE \
0xf0001400 // Hibernate
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPinPresent() API
// as the ulPin parameter.
//
//*****************************************************************************
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSet() API as
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
//
//*****************************************************************************
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
//
//*****************************************************************************
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPWMClockSet() API
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
// API.
//
//*****************************************************************************
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlADCSpeedSet() API
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
// API.
//
//*****************************************************************************
#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second
#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second
#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlDeepSleepClockSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(unsigned long ulInts);
extern void SysCtlIntDisable(unsigned long ulInts);
extern void SysCtlIntClear(unsigned long ulInts);
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
extern void SysCtlLDOSet(unsigned long ulVoltage);
extern unsigned long SysCtlLDOGet(void);
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern unsigned long SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlDelay(unsigned long ulCount);
extern void SysCtlMOSCConfigSet(unsigned long ulConfig);
extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlDeepSleepClockSet(unsigned long ulConfig);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
extern unsigned long SysCtlADCSpeedGet(void);
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
extern void SysCtlClkVerificationClear(void);
extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
extern void SysCtlUSBPLLEnable(void);
extern void SysCtlUSBPLLDisable(void);
extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
unsigned long ulMClk);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSCTL_H__

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/*
FreeRTOS config file for the "DPP" demo on EK-TM4C123GXL board
Quantum Leaps, LLC, www.state-machine.com
*/
/*
FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/* Ensure stdint is only used by the compiler, and not the assembler. */
#ifdef __ICCARM__
#include <stdint.h>
extern uint32_t SystemCoreClock;
/* assertion failure handler prototype */
extern void assert_failed(char const *file, int line);
#endif
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ( ( TickType_t ) 50 )
#define configMAX_PRIORITIES ( 32 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 4 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 8 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 0
#define configQUEUE_REGISTRY_SIZE 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 0
#define configUSE_MALLOC_FAILED_HOOK 0
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 0
#define configGENERATE_RUN_TIME_STATS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 0
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 0
#define INCLUDE_vTaskDelay 0
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 3 /* 7 priority levels */
#endif
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 3
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY 0xFF
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
#define configASSERT( x ) if( ( x ) == 0 ) { assert_failed(__FILE__, __LINE__); }
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
#endif /* FREERTOS_CONFIG_H */

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The project file provided with this example assumes that
the environment variables QPC and FREERTOS are defined and
that they point to the location of the QP/C framework and
FreeRTOS, respectively.
For example, assuming that you have installed QP/C into the
directory C:\qp\qpc and FreeRTOS to C:\software\FreeRTOSV8.1.2
you should define the environment variable QPC to C:\qp\qpc
and the environment variable FREERTOS to C:\software\FreeRTOSV8.1.2.
Editing the Environment Variables on Windows
--------------------------------------------
Open the Windows Explorer and right-click on the Computer
icon. Then select Properties from the pop-up menu. This opens
a window with the basic information about your computer. In the
left panel of this window, click on "Advanced system settings".
This opens the dialog "System Properties". Click the
"Environment Variables..." button.
To add a new environment variable, click the "New..." button
in the System variables section and provide the variable name
(e.g., QPC) and value (e.g., C:\qp\qpc).
****
NOTE: After updating envrinment variables, you shold reboot your
computer so that all applications, such as IAR Embedded Workbench
can pick up the changes.
****

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//****************************************************************************
// Product: "Dining Philosophers Problem" example, FreeRTOS port
// Last Updated for Version: 5.3.1
// Date of the Last Update: 2014-09-29
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, LLC. state-machine.com.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Web: http://www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#include "qp_port.h"
#include "dpp.h"
#include "bsp.h"
extern "C" {
#include "tm4c_cmsis.h"
#include "sysctl.h"
#include "gpio.h"
#include "rom.h"
}
uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
//****************************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE // define the name of this file for assertions
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
//
enum KernelUnawareISRs { // see NOTE1
// ...
MAX_KERNEL_UNAWARE_CMSIS_PRI // keep always last
};
// "kernel-unaware" interrupts can't overlap "kernel-aware" interrupts
Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI
<= configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
enum KernelAwareISRs {
GPIOPORTA_PRIO = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY, // NOTE1
SYSTICK_PRIO,
// ...
MAX_KERNEL_AWARE_CMSIS_PRI // keep always last
};
// "kernel-aware" interrupts should not overlap the PendSV priority
Q_ASSERT_COMPILE(MAX_KERNEL_AWARE_CMSIS_PRI <= (0xFF >>(8-__NVIC_PRIO_BITS)));
// Local-scope objects -------------------------------------------------------
static uint32_t l_rnd; // random seed
#define LED_RED (1U << 1)
#define LED_GREEN (1U << 3)
#define LED_BLUE (1U << 2)
#define USR_SW1 (1U << 4)
#define USR_SW2 (1U << 0)
#ifdef Q_SPY
QP::QSTimeCtr QS_tickTime_;
QP::QSTimeCtr QS_tickPeriod_;
static uint8_t l_SysTick_Handler;
static uint8_t l_GPIOPortA_IRQHandler;
uint32_t const UART_BAUD_RATE = static_cast<uint32_t>(115200U);
uint32_t const UART_FR_TXFE = static_cast<uint32_t>(0x80U);
uint16_t const UART_TXFIFO_DEPTH = static_cast<uint16_t>(16U);
enum AppRecords { // application-specific trace records
PHILO_STAT = QP::QS_USER
};
#endif
//............................................................................
extern "C" void vApplicationTickHook(void) {
QF_CRIT_STAT_TYPE intStat;
BaseType_t lHigherPriorityTaskWoken = pdFALSE;
QF_ISR_ENTRY(intStat); // <=== inform QF about ISR entry
#ifdef Q_SPY
{
uint32_t dummy = SysTick->CTRL; // clear SysTick_CTRL_COUNTFLAG
QS_tickTime_ += QS_tickPeriod_; // account for the clock rollover
}
#endif
QP::QF::TICK_X(0U, &l_SysTick_Handler); // process time events at rate 0
static uint32_t btn_debounced = USR_SW1;
static uint8_t debounce_state = 0U;
uint32_t btn = GPIOF->DATA_Bits[USR_SW1]; // read the user sw1
switch (debounce_state) {
case 0:
if (btn != btn_debounced) {
debounce_state = 1U; // transition to the next state
}
break;
case 1:
if (btn != btn_debounced) {
debounce_state = 2U; // transition to the next state
}
else {
debounce_state = 0U; // transition back to state 0
}
break;
case 2:
if (btn != btn_debounced) {
debounce_state = 3U; // transition to the next state
}
else {
debounce_state = 0U; // transition back to state 0
}
break;
case 3:
if (btn != btn_debounced) {
btn_debounced = btn; // save the debounced button value
if (btn == 0U) { // is the button depressed?
static QP::QEvt const pauseEvt =
QEVT_INITIALIZER(DPP::PAUSE_SIG);
QP::QF::PUBLISH(&pauseEvt, &l_SysTick_Handler);
}
else {
static QP::QEvt const pauseEvt =
QEVT_INITIALIZER(DPP::PAUSE_SIG);
QP::QF::PUBLISH(&pauseEvt, &l_SysTick_Handler);
}
}
debounce_state = 0U; // transition back to state 0
break;
default:
Q_ERROR();
break;
}
QF_ISR_EXIT(intStat, lHigherPriorityTaskWoken); // <=== ISR exit
// yield only when needed...
if (lHigherPriorityTaskWoken != pdFALSE) {
vTaskMissedYield();
}
}
//............................................................................
extern "C" void vApplicationIdleHook(void) {
// toggle the User LED on and then off, see NOTE2
QF_INT_DISABLE();
GPIOF->DATA_Bits[LED_GREEN] = LED_GREEN; // turn the Green LED on
GPIOF->DATA_Bits[LED_GREEN] = 0; // turn the Green LED off
QF_INT_ENABLE();
#ifdef Q_SPY
if ((UART0->FR & DPP::UART_FR_TXFE) != 0U) { // TX done?
uint16_t fifo = DPP::UART_TXFIFO_DEPTH; // max bytes we can accept
QF_INT_DISABLE();
uint8_t const *block = QP::QS::getBlock(&fifo); // try to get next block
QF_INT_ENABLE();
while (fifo-- != 0) { // any bytes in the block?
UART0->DR = *block++; // put into the FIFO
}
}
#elif defined NDEBUG
// put the CPU and peripherals to the low-power mode
// you might need to customize the clock management for your application,
// see the datasheet for your particular Cortex-M3 MCU.
__WFI(); // Wait-For-Interrupt
#endif
}
//............................................................................
extern "C" void vApplicationStackOverflowHook(TaskHandle_t, char *) {
Q_ERROR();
}
//............................................................................
extern "C" void GPIOPortA_IRQHandler(void) {
QF_CRIT_STAT_TYPE intStat;
BaseType_t lHigherPriorityTaskWoken = pdFALSE;
QF_ISR_ENTRY(intStat); // <=== inform QF about ISR entry
DPP::AO_Table->POST(Q_NEW(QP::QEvt, DPP::MAX_PUB_SIG), // for testing
&l_GPIOPortA_IRQHandler);
QF_ISR_EXIT(intStat, lHigherPriorityTaskWoken); // <=== ISR exit
// the usual end of FreeRTOS ISR...
portEND_SWITCHING_ISR(lHigherPriorityTaskWoken);
}
//............................................................................
void BSP_init(void) {
// Enable the floating-point unit
SCB->CPACR |= (0xFU << 20);
// Enable lazy stacking for interrupt handlers. This allows FPU
// instructions to be used within interrupt handlers, but at the
// expense of extra stack and CPU usage.
//
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
// Set the clocking to run directly from the crystal
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC
| SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);
SystemCoreClock = ROM_SysCtlClockGet(); // get the actual clock
// enable clock to the peripherals used by the application
SYSCTL->RCGC2 |= (1U << 5); // enable clock to GPIOF
__NOP(); // wait after enabling clocks
__NOP();
__NOP();
// configure the LEDs and push buttons
GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE); // set direction: output
GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); // digital enable
GPIOF->DATA_Bits[LED_RED] = 0; // turn the LED off
GPIOF->DATA_Bits[LED_GREEN] = 0; // turn the LED off
GPIOF->DATA_Bits[LED_BLUE] = 0; // turn the LED off
// configure the User Switches
GPIOF->DIR &= ~(USR_SW1 | USR_SW2); // set direction: input
ROM_GPIOPadConfigSet(GPIO_PORTF_BASE, (USR_SW1 | USR_SW2),
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
BSP_randomSeed(1234U);
Q_ALLEGE(QS_INIT(static_cast<void *>(0)));
QS_OBJ_DICTIONARY(&l_SysTick_Handler);
QS_OBJ_DICTIONARY(&l_GPIOPortA_IRQHandler);
QS_USR_DICTIONARY(PHILO_STAT);
}
//............................................................................
void BSP_displayPhilStat(uint8_t const n, char_t const * const stat) {
GPIOF->DATA_Bits[LED_BLUE] = ((stat[0] == 'e') ? LED_BLUE : 0U);
QS_BEGIN(PHILO_STAT, AO_Philo[n]) // application-specific record begin
QS_U8(1U, n); // Philosopher number
QS_STR(stat); // Philosopher status
QS_END()
}
//............................................................................
void BSP_displayPaused(uint8_t const paused) {
GPIOF->DATA_Bits[LED_RED] = ((paused != 0U) ? LED_RED : 0U);
}
//............................................................................
uint32_t BSP_random(void) { // a very cheap pseudo-random-number generator
// code for testing the hardware FPU...
float volatile x = 3.1415926F;
x = x + 2.7182818F;
// "Super-Duper" Linear Congruential Generator (LCG)
// LCG(2^32, 3*7*11*13*23, 0, seed)
//
l_rnd = l_rnd * (3U*7U*11U*13U*23U);
return l_rnd >> 8;
}
//............................................................................
void BSP_randomSeed(uint32_t const seed) {
l_rnd = seed;
}
//............................................................................
void BSP_terminate(int16_t const result) {
(void)result;
}
} // namespace DPP
//............................................................................
extern "C" void Q_onAssert(char const Q_ROM * const file, int_t line) {
assert_failed(file, line);
}
//............................................................................
// error routine that is called if the CMSIS library encounters an error
extern "C" void assert_failed(char const *file, int line) {
(void)file; // avoid compiler warning
(void)line; // avoid compiler warning
QF_INT_DISABLE(); // make sure that all interrupts are disabled
ROM_SysCtlReset(); // reset the system
}
//****************************************************************************
namespace QP {
//............................................................................
void QF::onStartup(void) {
// set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate
(void)SysTick_Config(SystemCoreClock / DPP::BSP_TICKS_PER_SEC);
// assing all priority bits for preemption-prio. and none to sub-prio.
NVIC_SetPriorityGrouping(0U);
// set priorities of ALL ISRs used in the system, see NOTE00
//
// !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
//
NVIC_SetPriority(SysTick_IRQn, DPP::SYSTICK_PRIO);
NVIC_SetPriority(GPIOPortA_IRQn, DPP::GPIOPORTA_PRIO);
// enable IRQs...
NVIC_EnableIRQ(GPIOPortA_IRQn);
}
//............................................................................
void QF::onCleanup(void) {
}
//----------------------------------------------------------------------------
#ifdef Q_SPY
//............................................................................
bool QS::onStartup(void const *) {
static uint8_t qsBuf[6*256]; // buffer for Quantum Spy
uint32_t tmp;
initBuf(qsBuf, sizeof(qsBuf));
// enable the peripherals used by the UART0
SYSCTL->RCGC1 |= (1U << 0); // enable clock to UART0
SYSCTL->RCGC2 |= (1U << 0); // enable clock to GPIOA
__NOP(); // wait after enabling clocks
__NOP();
__NOP();
// configure UART0 pins for UART operation
tmp = (1 << 0) | (1 << 1);
GPIOA->DIR &= ~tmp;
GPIOA->AFSEL |= tmp;
GPIOA->DR2R |= tmp; // set 2mA drive, DR4R and DR8R are cleared
GPIOA->SLR &= ~tmp;
GPIOA->ODR &= ~tmp;
GPIOA->PUR &= ~tmp;
GPIOA->PDR &= ~tmp;
GPIOA->DEN |= tmp;
// configure the UART for the desired baud rate, 8-N-1 operation...
tmp = (((SystemCoreClock * 8U) / DPP::UART_BAUD_RATE) + 1U) / 2U;
UART0->IBRD = tmp / 64U;
UART0->FBRD = tmp % 64U;
UART0->LCRH = 0x60U; // configure 8-N-1 operation
UART0->LCRH |= 0x10U;
UART0->CTL |= (1U << 0) | (1U << 8) | (1U << 9);
DPP::QS_tickPeriod_ = SystemCoreClock / DPP::BSP_TICKS_PER_SEC;
DPP::QS_tickTime_ = DPP::QS_tickPeriod_; // to start the timestamp at zero
// setup the QS filters...
QS_FILTER_ON(QS_ALL_RECORDS);
// QS_FILTER_OFF(QS_QEP_STATE_EMPTY);
// QS_FILTER_OFF(QS_QEP_STATE_ENTRY);
// QS_FILTER_OFF(QS_QEP_STATE_EXIT);
// QS_FILTER_OFF(QS_QEP_STATE_INIT);
// QS_FILTER_OFF(QS_QEP_INIT_TRAN);
// QS_FILTER_OFF(QS_QEP_INTERN_TRAN);
// QS_FILTER_OFF(QS_QEP_TRAN);
// QS_FILTER_OFF(QS_QEP_IGNORED);
// QS_FILTER_OFF(QS_QF_ACTIVE_ADD);
// QS_FILTER_OFF(QS_QF_ACTIVE_REMOVE);
// QS_FILTER_OFF(QS_QF_ACTIVE_SUBSCRIBE);
// QS_FILTER_OFF(QS_QF_ACTIVE_UNSUBSCRIBE);
// QS_FILTER_OFF(QS_QF_ACTIVE_POST_FIFO);
// QS_FILTER_OFF(QS_QF_ACTIVE_POST_LIFO);
// QS_FILTER_OFF(QS_QF_ACTIVE_GET);
// QS_FILTER_OFF(QS_QF_ACTIVE_GET_LAST);
// QS_FILTER_OFF(QS_QF_EQUEUE_INIT);
// QS_FILTER_OFF(QS_QF_EQUEUE_POST_FIFO);
// QS_FILTER_OFF(QS_QF_EQUEUE_POST_LIFO);
// QS_FILTER_OFF(QS_QF_EQUEUE_GET);
// QS_FILTER_OFF(QS_QF_EQUEUE_GET_LAST);
// QS_FILTER_OFF(QS_QF_MPOOL_INIT);
// QS_FILTER_OFF(QS_QF_MPOOL_GET);
// QS_FILTER_OFF(QS_QF_MPOOL_PUT);
// QS_FILTER_OFF(QS_QF_PUBLISH);
// QS_FILTER_OFF(QS_QF_NEW);
// QS_FILTER_OFF(QS_QF_GC_ATTEMPT);
// QS_FILTER_OFF(QS_QF_GC);
// QS_FILTER_OFF(QS_QF_TICK);
// QS_FILTER_OFF(QS_QF_TIMEEVT_ARM);
// QS_FILTER_OFF(QS_QF_TIMEEVT_AUTO_DISARM);
// QS_FILTER_OFF(QS_QF_TIMEEVT_DISARM_ATTEMPT);
// QS_FILTER_OFF(QS_QF_TIMEEVT_DISARM);
// QS_FILTER_OFF(QS_QF_TIMEEVT_REARM);
// QS_FILTER_OFF(QS_QF_TIMEEVT_POST);
QS_FILTER_OFF(QS_QF_CRIT_ENTRY);
QS_FILTER_OFF(QS_QF_CRIT_EXIT);
QS_FILTER_OFF(QS_QF_ISR_ENTRY);
QS_FILTER_OFF(QS_QF_ISR_EXIT);
return true; // return success
}
//............................................................................
void QS::onCleanup(void) {
}
//............................................................................
QSTimeCtr QS::onGetTime(void) { // invoked with interrupts disabled
QSTimeCtr ret = DPP::QS_tickTime_ - static_cast<QSTimeCtr>(SysTick->VAL);
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) { // flag set?
ret += DPP::QS_tickPeriod_;
}
return ret;
}
//............................................................................
void QS::onFlush(void) {
uint16_t fifo = DPP::UART_TXFIFO_DEPTH; // Tx FIFO depth
uint8_t const *block;
while ((block = getBlock(&fifo)) != static_cast<uint8_t *>(0)) {
// busy-wait until TX FIFO empty
while ((UART0->FR & DPP::UART_FR_TXFE) == 0U) {
}
while (fifo-- != 0U) { // any bytes in the block?
UART0->DR = *block++; // put into the TX FIFO
}
fifo = DPP::UART_TXFIFO_DEPTH; // re-load the Tx FIFO depth
}
}
#endif // Q_SPY
//----------------------------------------------------------------------------
} // namespace QP
//****************************************************************************
// NOTE1:
// The QF_onIdle() callback is called with interrupts disabled, because the
// determination of the idle condition might change by any interrupt posting
// an event. QF::onIdle() must internally enable interrupts, ideally
// atomically with putting the CPU to the power-saving mode.
//
// NOTE2:
// The Green LED is used to visualize the idle loop activity. The brightness
// of the LED is proportional to the frequency of invcations of the idle loop.
// Please note that the LED is toggled with interrupts locked, so no interrupt
// execution time contributes to the brightness of the User LED.
//

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//****************************************************************************
// Product: DPP example, QP-FreeRTOS port
// Last Updated for Version: 5.3.1
// Date of the Last Update: 2014-09-29
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, LLC. state-machine.com.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Web: http://www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#ifndef bsp_h
#define bsp_h
namespace DPP {
uint32_t const BSP_TICKS_PER_SEC = static_cast<uint32_t>(configTICK_RATE_HZ);
void BSP_init(void);
void BSP_displayPaused(uint8_t const paused);
void BSP_displayPhilStat(uint8_t const n, char_t const *stat);
void BSP_terminate(int16_t const result);
void BSP_randomSeed(uint32_t const seed); // random seed
uint32_t BSP_random(void); // pseudo-random generator
} // namespace DPP
#endif // bsp_h

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\dpp.ewp</path>
</project>
<batchBuild/>
</workspace>

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//****************************************************************************
// Model: dpp.qm
// File: ./dpp.h
//
// This code has been generated by QM tool (see state-machine.com/qm).
// DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//****************************************************************************
//${.::dpp.h} ................................................................
#ifndef dpp_h
#define dpp_h
namespace DPP {
enum DPPSignals {
EAT_SIG = QP::Q_USER_SIG, // published by Table to let a philosopher eat
DONE_SIG, // published by Philosopher when done eating
PAUSE_SIG, // published by BSP to pause the application
TERMINATE_SIG, // published by BSP to terminate the application
MAX_PUB_SIG, // the last published signal
HUNGRY_SIG, // posted direclty to Table from hungry Philo
MAX_SIG // the last signal
};
} // namespace DPP
namespace DPP {
//${Events::TableEvt} ........................................................
class TableEvt : public QP::QEvt {
public:
uint8_t philoNum;
};
} // namespace DPP
// number of philosophers
#define N_PHILO ((uint8_t)5)
namespace DPP {
extern QP::QActive * const AO_Philo[N_PHILO];
} // namespace DPP
namespace DPP {
extern QP::QActive * const AO_Table;
} // namespace DPP
#endif // dpp_h

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 1024;
define symbol __ICFEDIT_size_heap__ = 0;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place at start of RAM_region {block CSTACK };
place in RAM_region { readwrite, block HEAP };

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<?xml version="1.0" encoding="UTF-8"?>
<model version="3.2.0">
<documentation>Dining Philosopher Problem example with MSM state machines</documentation>
<framework name="qpcpp"/>
<package name="Events" stereotype="0x01" namespace="DPP::">
<class name="TableEvt" superclass="qpcpp::QEvt">
<attribute name="philoNum" type="uint8_t" visibility="0x00" properties="0x00"/>
</class>
</package>
<package name="AOs" stereotype="0x02" namespace="DPP::">
<class name="Philo" superclass="qpcpp::QMActive">
<attribute name="m_timeEvt" type="QP::QTimeEvt" visibility="0x02" properties="0x00"/>
<operation name="Philo" type="" visibility="0x00" properties="0x00">
<code> : QMActive(Q_STATE_CAST(&amp;Philo::initial)),
m_timeEvt(this, TIMEOUT_SIG, 0U)</code>
</operation>
<statechart>
<initial target="../1">
<action>static bool registered = false; // starts off with 0, per C-standard
(void)e; // suppress the compiler warning about unused parameter
if (!registered) {
registered = true;
QS_OBJ_DICTIONARY(&amp;l_philo[0]);
QS_OBJ_DICTIONARY(&amp;l_philo[0].m_timeEvt);
QS_OBJ_DICTIONARY(&amp;l_philo[1]);
QS_OBJ_DICTIONARY(&amp;l_philo[1].m_timeEvt);
QS_OBJ_DICTIONARY(&amp;l_philo[2]);
QS_OBJ_DICTIONARY(&amp;l_philo[2].m_timeEvt);
QS_OBJ_DICTIONARY(&amp;l_philo[3]);
QS_OBJ_DICTIONARY(&amp;l_philo[3].m_timeEvt);
QS_OBJ_DICTIONARY(&amp;l_philo[4]);
QS_OBJ_DICTIONARY(&amp;l_philo[4].m_timeEvt);
QS_FUN_DICTIONARY(&amp;Philo::initial);
QS_FUN_DICTIONARY(&amp;Philo::thinking);
QS_FUN_DICTIONARY(&amp;Philo::hungry);
QS_FUN_DICTIONARY(&amp;Philo::eating);
}
QS_SIG_DICTIONARY(HUNGRY_SIG, me); // signal for each Philos
QS_SIG_DICTIONARY(TIMEOUT_SIG, me); // signal for each Philos
me-&gt;subscribe(EAT_SIG);</action>
<initial_glyph conn="2,3,5,1,20,5,-3">
<action box="0,-2,6,2"/>
</initial_glyph>
</initial>
<state name="thinking">
<entry>me-&gt;m_timeEvt.armX(think_time(), 0U);</entry>
<exit>(void)me-&gt;m_timeEvt.disarm();</exit>
<tran trig="TIMEOUT" target="../../2">
<tran_glyph conn="2,14,3,1,20,11,-3">
<action box="0,-2,6,2"/>
</tran_glyph>
</tran>
<tran trig="EAT, DONE">
<action>/* EAT or DONE must be for other Philos than this one */
Q_ASSERT(Q_EVT_CAST(TableEvt)-&gt;philoNum != PHILO_ID(me));</action>
<tran_glyph conn="2,18,3,-1,13">
<action box="0,-2,14,2"/>
</tran_glyph>
</tran>
<state_glyph node="2,5,17,16">
<entry box="1,2,5,2"/>
<exit box="1,4,5,2"/>
</state_glyph>
</state>
<state name="hungry">
<entry>TableEvt *pe = Q_NEW(TableEvt, HUNGRY_SIG);
pe-&gt;philoNum = PHILO_ID(me);
AO_Table-&gt;POST(pe, me);</entry>
<tran trig="EAT">
<choice target="../../../3">
<guard>Q_EVT_CAST(TableEvt)-&gt;philoNum == PHILO_ID(me)</guard>
<choice_glyph conn="15,30,5,1,7,13,-3">
<action box="1,0,19,4"/>
</choice_glyph>
</choice>
<tran_glyph conn="2,30,3,-1,13">
<action box="0,-2,14,2"/>
</tran_glyph>
</tran>
<tran trig="DONE">
<action>/* DONE must be for other Philos than this one */
Q_ASSERT(Q_EVT_CAST(TableEvt)-&gt;philoNum != PHILO_ID(me));</action>
<tran_glyph conn="2,36,3,-1,14">
<action box="0,-2,14,2"/>
</tran_glyph>
</tran>
<state_glyph node="2,23,17,16">
<entry box="1,2,5,2"/>
</state_glyph>
</state>
<state name="eating">
<entry>me-&gt;m_timeEvt.armX(eat_time(), 0U);</entry>
<exit>TableEvt *pe = Q_NEW(TableEvt, DONE_SIG);
pe-&gt;philoNum = PHILO_ID(me);
QP::QF::PUBLISH(pe, me);
(void)me-&gt;m_timeEvt.disarm();</exit>
<tran trig="TIMEOUT" target="../../1">
<tran_glyph conn="2,51,3,1,22,-41,-5">
<action box="0,-2,6,2"/>
</tran_glyph>
</tran>
<tran trig="EAT, DONE">
<action>/* EAT or DONE must be for other Philos than this one */
Q_ASSERT(Q_EVT_CAST(TableEvt)-&gt;philoNum != PHILO_ID(me));</action>
<tran_glyph conn="2,55,3,-1,13">
<action box="0,-2,14,2"/>
</tran_glyph>
</tran>
<state_glyph node="2,41,17,18">
<entry box="1,2,5,2"/>
<exit box="1,4,5,2"/>
</state_glyph>
</state>
<state_diagram size="37,61"/>
</statechart>
</class>
<class name="Table" superclass="qpcpp::QMActive">
<attribute name="m_fork[N_PHILO]" type="uint8_t" visibility="0x02" properties="0x00"/>
<attribute name="m_isHungry[N_PHILO]" type="bool" visibility="0x02" properties="0x00"/>
<operation name="Table" type="" visibility="0x00" properties="0x00">
<code> : QMActive(Q_STATE_CAST(&amp;Table::initial))
for (uint8_t n = 0U; n &lt; N_PHILO; ++n) {
m_fork[n] = FREE;
m_isHungry[n] = false;
}</code>
</operation>
<statechart>
<initial target="../1/2">
<action>(void)e; // suppress the compiler warning about unused parameter
QS_OBJ_DICTIONARY(&amp;l_table);
QS_FUN_DICTIONARY(&amp;QP::QHsm::top);
QS_FUN_DICTIONARY(&amp;Table::initial);
QS_FUN_DICTIONARY(&amp;Table::active);
QS_FUN_DICTIONARY(&amp;Table::serving);
QS_FUN_DICTIONARY(&amp;Table::paused);
QS_SIG_DICTIONARY(DONE_SIG, (void *)0); // global signals
QS_SIG_DICTIONARY(EAT_SIG, (void *)0);
QS_SIG_DICTIONARY(PAUSE_SIG, (void *)0);
QS_SIG_DICTIONARY(TERMINATE_SIG, (void *)0);
QS_SIG_DICTIONARY(HUNGRY_SIG, me); // signal just for Table
me-&gt;subscribe(DONE_SIG);
me-&gt;subscribe(PAUSE_SIG);
me-&gt;subscribe(TERMINATE_SIG);
for (uint8_t n = 0U; n &lt; N_PHILO; ++n) {
me-&gt;m_fork[n] = FREE;
me-&gt;m_isHungry[n] = false;
BSP_displayPhilStat(n, THINKING);
}</action>
<initial_glyph conn="3,3,5,1,44,18,-9">
<action box="0,-2,6,2"/>
</initial_glyph>
</initial>
<state name="active">
<tran trig="TERMINATE">
<action>BSP_terminate(0);</action>
<tran_glyph conn="2,11,3,-1,14">
<action box="0,-2,11,4"/>
</tran_glyph>
</tran>
<tran trig="EAT">
<action>Q_ERROR();</action>
<tran_glyph conn="2,15,3,-1,14">
<action box="0,-2,10,4"/>
</tran_glyph>
</tran>
<state name="serving">
<entry brief="give pending permitions to eat">for (uint8_t n = 0U; n &lt; N_PHILO; ++n) { // give permissions to eat...
if (me-&gt;m_isHungry[n]
&amp;&amp; (me-&gt;m_fork[LEFT(n)] == FREE)
&amp;&amp; (me-&gt;m_fork[n] == FREE))
{
me-&gt;m_fork[LEFT(n)] = USED;
me-&gt;m_fork[n] = USED;
TableEvt *te = Q_NEW(TableEvt, EAT_SIG);
te-&gt;philoNum = n;
QP::QF::PUBLISH(te, me);
me-&gt;m_isHungry[n] = false;
BSP_displayPhilStat(n, EATING);
}
}</entry>
<tran trig="HUNGRY">
<action>uint8_t n = Q_EVT_CAST(TableEvt)-&gt;philoNum;
// phil ID must be in range and he must be not hungry
Q_ASSERT((n &lt; N_PHILO) &amp;&amp; (!me-&gt;m_isHungry[n]));
BSP_displayPhilStat(n, HUNGRY);
uint8_t m = LEFT(n);</action>
<choice>
<guard brief="both free">(me-&gt;m_fork[m] == FREE) &amp;&amp; (me-&gt;m_fork[n] == FREE)</guard>
<action>me-&gt;m_fork[m] = USED;
me-&gt;m_fork[n] = USED;
TableEvt *pe = Q_NEW(TableEvt, EAT_SIG);
pe-&gt;philoNum = n;
QP::QF::PUBLISH(pe, me);
BSP_displayPhilStat(n, EATING);</action>
<choice_glyph conn="19,26,5,-1,10">
<action box="1,0,10,2"/>
</choice_glyph>
</choice>
<choice>
<guard>else</guard>
<action>me-&gt;m_isHungry[n] = true;</action>
<choice_glyph conn="19,26,4,-1,5,10">
<action box="1,5,6,2"/>
</choice_glyph>
</choice>
<tran_glyph conn="4,26,3,-1,15">
<action box="0,-2,8,2"/>
</tran_glyph>
</tran>
<tran trig="DONE">
<action>uint8_t n = Q_EVT_CAST(TableEvt)-&gt;philoNum;
// phil ID must be in range and he must be not hungry
Q_ASSERT((n &lt; N_PHILO) &amp;&amp; (!me-&gt;m_isHungry[n]));
BSP_displayPhilStat(n, THINKING);
uint8_t m = LEFT(n);
// both forks of Phil[n] must be used
Q_ASSERT((me-&gt;m_fork[n] == USED) &amp;&amp; (me-&gt;m_fork[m] == USED));
me-&gt;m_fork[m] = FREE;
me-&gt;m_fork[n] = FREE;
m = RIGHT(n); // check the right neighbor
if (me-&gt;m_isHungry[m] &amp;&amp; (me-&gt;m_fork[m] == FREE)) {
me-&gt;m_fork[n] = USED;
me-&gt;m_fork[m] = USED;
me-&gt;m_isHungry[m] = false;
TableEvt *pe = Q_NEW(TableEvt, EAT_SIG);
pe-&gt;philoNum = m;
QP::QF::PUBLISH(pe, me);
BSP_displayPhilStat(m, EATING);
}
m = LEFT(n); // check the left neighbor
n = LEFT(m); // left fork of the left neighbor
if (me-&gt;m_isHungry[m] &amp;&amp; (me-&gt;m_fork[n] == FREE)) {
me-&gt;m_fork[m] = USED;
me-&gt;m_fork[n] = USED;
me-&gt;m_isHungry[m] = false;
TableEvt *pe = Q_NEW(TableEvt, EAT_SIG);
pe-&gt;philoNum = m;
QP::QF::PUBLISH(pe, me);
BSP_displayPhilStat(m, EATING);
}</action>
<tran_glyph conn="4,34,3,-1,15">
<action box="0,-2,6,2"/>
</tran_glyph>
</tran>
<tran trig="EAT">
<action>Q_ERROR();</action>
<tran_glyph conn="4,37,3,-1,15">
<action box="0,-2,12,4"/>
</tran_glyph>
</tran>
<tran trig="PAUSE" target="../../3">
<tran_glyph conn="4,41,3,1,37,6,-3">
<action box="0,-2,7,2"/>
</tran_glyph>
</tran>
<state_glyph node="4,19,34,24">
<entry box="1,2,27,2"/>
</state_glyph>
</state>
<state name="paused">
<entry>BSP_displayPaused(1U);</entry>
<exit>BSP_displayPaused(0U);</exit>
<tran trig="PAUSE" target="../../2">
<tran_glyph conn="4,57,3,1,39,-29,-5">
<action box="0,-2,7,2"/>
</tran_glyph>
</tran>
<tran trig="HUNGRY">
<action>uint8_t n = Q_EVT_CAST(TableEvt)-&gt;philoNum;
// philo ID must be in range and he must be not hungry
Q_ASSERT((n &lt; N_PHILO) &amp;&amp; (!me-&gt;m_isHungry[n]));
me-&gt;m_isHungry[n] = true;
BSP_displayPhilStat(n, HUNGRY);</action>
<tran_glyph conn="4,60,3,-1,15">
<action box="0,-2,6,2"/>
</tran_glyph>
</tran>
<tran trig="DONE">
<action>uint8_t n = Q_EVT_CAST(TableEvt)-&gt;philoNum;
// phil ID must be in range and he must be not hungry
Q_ASSERT((n &lt; N_PHILO) &amp;&amp; (!me-&gt;m_isHungry[n]));
BSP_displayPhilStat(n, THINKING);
uint8_t m = LEFT(n);
/* both forks of Phil[n] must be used */
Q_ASSERT((me-&gt;m_fork[n] == USED) &amp;&amp; (me-&gt;m_fork[m] == USED));
me-&gt;m_fork[m] = FREE;
me-&gt;m_fork[n] = FREE;</action>
<tran_glyph conn="4,63,3,-1,15">
<action box="0,-2,6,2"/>
</tran_glyph>
</tran>
<state_glyph node="4,45,34,20">
<entry box="1,2,18,4"/>
<exit box="1,6,18,4"/>
</state_glyph>
</state>
<state_glyph node="2,5,43,62"/>
</state>
<state_diagram size="49,69"/>
</statechart>
</class>
<attribute name="AO_Philo[N_PHILO]" type="QP::QActive * const" visibility="0x00" properties="0x00"/>
<attribute name="AO_Table" type="QP::QActive * const" visibility="0x00" properties="0x00"/>
</package>
<directory name=".">
<file name="dpp.h">
<text>#ifndef dpp_h
#define dpp_h
namespace DPP {
enum DPPSignals {
EAT_SIG = QP::Q_USER_SIG, // published by Table to let a philosopher eat
DONE_SIG, // published by Philosopher when done eating
PAUSE_SIG, // published by BSP to pause the application
TERMINATE_SIG, // published by BSP to terminate the application
MAX_PUB_SIG, // the last published signal
HUNGRY_SIG, // posted direclty to Table from hungry Philo
MAX_SIG // the last signal
};
} // namespace DPP
$declare(Events::TableEvt)
// number of philosophers
#define N_PHILO ((uint8_t)5)
$declare(AOs::AO_Philo[N_PHILO])
$declare(AOs::AO_Table)
#endif // dpp_h</text>
</file>
<file name="philo.cpp">
<text>#include &quot;qp_port.h&quot;
#include &quot;dpp.h&quot;
#include &quot;bsp.h&quot;
Q_DEFINE_THIS_FILE
// Active object class -------------------------------------------------------
$declare(AOs::Philo)
namespace DPP {
// Local objects -------------------------------------------------------------
static Philo l_philo[N_PHILO]; // storage for all Philos
// helper function to provide a randomized think time for Philos
inline QP::QTimeEvtCtr think_time() {
return static_cast&lt;QP::QTimeEvtCtr&gt;((BSP_random() % BSP_TICKS_PER_SEC)
+ (BSP_TICKS_PER_SEC/2U));
}
// helper function to provide a randomized eat time for Philos
inline QP::QTimeEvtCtr eat_time() {
return static_cast&lt;QP::QTimeEvtCtr&gt;((BSP_random() % BSP_TICKS_PER_SEC)
+ BSP_TICKS_PER_SEC);
}
// helper function to provide the ID of Philo &quot;me&quot;
inline uint8_t PHILO_ID(Philo const * const me) {
return static_cast&lt;uint8_t&gt;(me - l_philo);
}
enum InternalSignals { // internal signals
TIMEOUT_SIG = MAX_SIG
};
// Global objects ------------------------------------------------------------
QP::QActive * const AO_Philo[N_PHILO] = { // &quot;opaque&quot; pointers to Philo AO
&amp;l_philo[0],
&amp;l_philo[1],
&amp;l_philo[2],
&amp;l_philo[3],
&amp;l_philo[4]
};
} // namespace DPP
// Philo definition ----------------------------------------------------------
$define(AOs::Philo)</text>
</file>
<file name="table.cpp">
<text>#include &quot;qp_port.h&quot;
#include &quot;dpp.h&quot;
#include &quot;bsp.h&quot;
Q_DEFINE_THIS_FILE
// Active object class -------------------------------------------------------
$declare(AOs::Table)
namespace DPP {
// helper function to provide the RIGHT neighbour of a Philo[n]
inline uint8_t RIGHT(uint8_t const n) {
return static_cast&lt;uint8_t&gt;((n + (N_PHILO - 1U)) % N_PHILO);
}
// helper function to provide the LEFT neighbour of a Philo[n]
inline uint8_t LEFT(uint8_t const n) {
return static_cast&lt;uint8_t&gt;((n + 1U) % N_PHILO);
}
static uint8_t const FREE = static_cast&lt;uint8_t&gt;(0);
static uint8_t const USED = static_cast&lt;uint8_t&gt;(1);
static char_t const * const THINKING = &amp;&quot;thinking&quot;[0];
static char_t const * const HUNGRY = &amp;&quot;hungry &quot;[0];
static char_t const * const EATING = &amp;&quot;eating &quot;[0];
// Local objects -------------------------------------------------------------
static Table l_table; // the single instance of the Table active object
// Global-scope objects ------------------------------------------------------
QP::QActive * const AO_Table = &amp;l_table; // &quot;opaque&quot; AO pointer
} // namespace DPP
//............................................................................
$define(AOs::Table)</text>
</file>
</directory>
</model>

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//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfnIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinConfigure(unsigned long ulPinConfig);
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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//****************************************************************************
// Product: DPP Example
// Last Updated for Version: 5.3.1
// Date of the Last Update: 2014-09-29
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, LLC. state-machine.com.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Web: http://www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#include "qp_port.h"
#include "dpp.h"
#include "bsp.h"
//............................................................................
int main() {
static QP::QEvt const *tableQueueSto[N_PHILO];
static QP::QEvt const *philoQueueSto[N_PHILO][N_PHILO];
static QP::QSubscrList subscrSto[DPP::MAX_PUB_SIG];
static QF_MPOOL_EL(DPP::TableEvt) smlPoolSto[2*N_PHILO];
QP::QF::init(); // initialize the framework and the underlying RT kernel
DPP::BSP_init(); // initialize the BSP
// object dictionaries...
QS_OBJ_DICTIONARY(smlPoolSto);
QS_OBJ_DICTIONARY(tableQueueSto);
QS_OBJ_DICTIONARY(philoQueueSto[0]);
QS_OBJ_DICTIONARY(philoQueueSto[1]);
QS_OBJ_DICTIONARY(philoQueueSto[2]);
QS_OBJ_DICTIONARY(philoQueueSto[3]);
QS_OBJ_DICTIONARY(philoQueueSto[4]);
QP::QF::psInit(subscrSto, Q_DIM(subscrSto)); // init publish-subscribe
// initialize event pools...
QP::QF::poolInit(smlPoolSto,
sizeof(smlPoolSto), sizeof(smlPoolSto[0]));
// start the active objects...
for (uint8_t n = 0U; n < N_PHILO; ++n) {
DPP::AO_Philo[n]->start((uint8_t)(n + 1U),
philoQueueSto[n], Q_DIM(philoQueueSto[n]),
(void *)0, 512U);
}
DPP::AO_Table->start((uint8_t)(N_PHILO + 1U),
tableQueueSto, Q_DIM(tableQueueSto),
(void *)0, 512U);
return QP::QF::run(); // run the QF application
}

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//****************************************************************************
// Model: dpp.qm
// File: ./philo.cpp
//
// This code has been generated by QM tool (see state-machine.com/qm).
// DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//****************************************************************************
//${.::philo.cpp} ............................................................
#include "qp_port.h"
#include "dpp.h"
#include "bsp.h"
Q_DEFINE_THIS_FILE
// Active object class -------------------------------------------------------
namespace DPP {
//${AOs::Philo} ..............................................................
class Philo : public QP::QMActive {
private:
QP::QTimeEvt m_timeEvt;
public:
Philo();
protected:
static QP::QState initial(Philo * const me, QP::QEvt const * const e);
static QP::QState thinking (Philo * const me, QP::QEvt const * const e);
static QP::QState thinking_e(Philo * const me);
static QP::QState thinking_x(Philo * const me);
static QP::QMState const thinking_s;
static QP::QState hungry (Philo * const me, QP::QEvt const * const e);
static QP::QState hungry_e(Philo * const me);
static QP::QMState const hungry_s;
static QP::QState eating (Philo * const me, QP::QEvt const * const e);
static QP::QState eating_e(Philo * const me);
static QP::QState eating_x(Philo * const me);
static QP::QMState const eating_s;
};
} // namespace DPP
namespace DPP {
// Local objects -------------------------------------------------------------
static Philo l_philo[N_PHILO]; // storage for all Philos
// helper function to provide a randomized think time for Philos
inline QP::QTimeEvtCtr think_time() {
return static_cast<QP::QTimeEvtCtr>((BSP_random() % BSP_TICKS_PER_SEC)
+ (BSP_TICKS_PER_SEC/2U));
}
// helper function to provide a randomized eat time for Philos
inline QP::QTimeEvtCtr eat_time() {
return static_cast<QP::QTimeEvtCtr>((BSP_random() % BSP_TICKS_PER_SEC)
+ BSP_TICKS_PER_SEC);
}
// helper function to provide the ID of Philo "me"
inline uint8_t PHILO_ID(Philo const * const me) {
return static_cast<uint8_t>(me - l_philo);
}
enum InternalSignals { // internal signals
TIMEOUT_SIG = MAX_SIG
};
// Global objects ------------------------------------------------------------
QP::QActive * const AO_Philo[N_PHILO] = { // "opaque" pointers to Philo AO
&l_philo[0],
&l_philo[1],
&l_philo[2],
&l_philo[3],
&l_philo[4]
};
} // namespace DPP
// Philo definition ----------------------------------------------------------
namespace DPP {
//${AOs::Philo} ..............................................................
//${AOs::Philo::Philo} .......................................................
Philo::Philo()
: QMActive(Q_STATE_CAST(&Philo::initial)),
m_timeEvt(this, TIMEOUT_SIG, 0U)
{}
//${AOs::Philo::SM} ..........................................................
QP::QState Philo::initial(Philo * const me, QP::QEvt const * const e) {
static struct {
QP::QMState const *target;
QP::QActionHandler act[2];
} const tatbl_ = { // transition-action table
&thinking_s,
{
Q_ACTION_CAST(&thinking_e), // entry
Q_ACTION_CAST(0) // zero terminator
}
};
// ${AOs::Philo::SM::initial}
static bool registered = false; // starts off with 0, per C-standard
(void)e; // suppress the compiler warning about unused parameter
if (!registered) {
registered = true;
QS_OBJ_DICTIONARY(&l_philo[0]);
QS_OBJ_DICTIONARY(&l_philo[0].m_timeEvt);
QS_OBJ_DICTIONARY(&l_philo[1]);
QS_OBJ_DICTIONARY(&l_philo[1].m_timeEvt);
QS_OBJ_DICTIONARY(&l_philo[2]);
QS_OBJ_DICTIONARY(&l_philo[2].m_timeEvt);
QS_OBJ_DICTIONARY(&l_philo[3]);
QS_OBJ_DICTIONARY(&l_philo[3].m_timeEvt);
QS_OBJ_DICTIONARY(&l_philo[4]);
QS_OBJ_DICTIONARY(&l_philo[4].m_timeEvt);
QS_FUN_DICTIONARY(&Philo::initial);
QS_FUN_DICTIONARY(&Philo::thinking);
QS_FUN_DICTIONARY(&Philo::hungry);
QS_FUN_DICTIONARY(&Philo::eating);
}
QS_SIG_DICTIONARY(HUNGRY_SIG, me); // signal for each Philos
QS_SIG_DICTIONARY(TIMEOUT_SIG, me); // signal for each Philos
me->subscribe(EAT_SIG);
return QM_TRAN_INIT(&tatbl_);
}
//${AOs::Philo::SM::thinking} ................................................
QP::QMState const Philo::thinking_s = {
static_cast<QP::QMState const *>(0), // superstate (top)
Q_STATE_CAST(&thinking),
Q_ACTION_CAST(&thinking_e),
Q_ACTION_CAST(&thinking_x),
Q_ACTION_CAST(0) // no intitial tran.
};
// ${AOs::Philo::SM::thinking}
QP::QState Philo::thinking_e(Philo * const me) {
me->m_timeEvt.armX(think_time(), 0U);
return QM_ENTRY(&thinking_s);
}
// ${AOs::Philo::SM::thinking}
QP::QState Philo::thinking_x(Philo * const me) {
(void)me->m_timeEvt.disarm();
return QM_EXIT(&thinking_s);
}
// ${AOs::Philo::SM::thinking}
QP::QState Philo::thinking(Philo * const me, QP::QEvt const * const e) {
QP::QState status_;
switch (e->sig) {
// ${AOs::Philo::SM::thinking::TIMEOUT}
case TIMEOUT_SIG: {
static struct {
QP::QMState const *target;
QP::QActionHandler act[3];
} const tatbl_ = { // transition-action table
&hungry_s,
{
Q_ACTION_CAST(&thinking_x), // exit
Q_ACTION_CAST(&hungry_e), // entry
Q_ACTION_CAST(0) // zero terminator
}
};
status_ = QM_TRAN(&tatbl_);
break;
}
// ${AOs::Philo::SM::thinking::EAT, DONE}
case EAT_SIG: /* intentionally fall through */
case DONE_SIG: {
/* EAT or DONE must be for other Philos than this one */
Q_ASSERT(Q_EVT_CAST(TableEvt)->philoNum != PHILO_ID(me));
status_ = QM_HANDLED();
break;
}
default: {
status_ = QM_SUPER();
break;
}
}
return status_;
}
//${AOs::Philo::SM::hungry} ..................................................
QP::QMState const Philo::hungry_s = {
static_cast<QP::QMState const *>(0), // superstate (top)
Q_STATE_CAST(&hungry),
Q_ACTION_CAST(&hungry_e),
Q_ACTION_CAST(0), // no exit action
Q_ACTION_CAST(0) // no intitial tran.
};
// ${AOs::Philo::SM::hungry}
QP::QState Philo::hungry_e(Philo * const me) {
TableEvt *pe = Q_NEW(TableEvt, HUNGRY_SIG);
pe->philoNum = PHILO_ID(me);
AO_Table->POST(pe, me);
return QM_ENTRY(&hungry_s);
}
// ${AOs::Philo::SM::hungry}
QP::QState Philo::hungry(Philo * const me, QP::QEvt const * const e) {
QP::QState status_;
switch (e->sig) {
// ${AOs::Philo::SM::hungry::EAT}
case EAT_SIG: {
// ${AOs::Philo::SM::hungry::EAT::[Q_EVT_CAST(Ta~]}
if (Q_EVT_CAST(TableEvt)->philoNum == PHILO_ID(me)) {
static struct {
QP::QMState const *target;
QP::QActionHandler act[2];
} const tatbl_ = { // transition-action table
&eating_s,
{
Q_ACTION_CAST(&eating_e), // entry
Q_ACTION_CAST(0) // zero terminator
}
};
status_ = QM_TRAN(&tatbl_);
}
else {
status_ = QM_UNHANDLED();
}
break;
}
// ${AOs::Philo::SM::hungry::DONE}
case DONE_SIG: {
/* DONE must be for other Philos than this one */
Q_ASSERT(Q_EVT_CAST(TableEvt)->philoNum != PHILO_ID(me));
status_ = QM_HANDLED();
break;
}
default: {
status_ = QM_SUPER();
break;
}
}
return status_;
}
//${AOs::Philo::SM::eating} ..................................................
QP::QMState const Philo::eating_s = {
static_cast<QP::QMState const *>(0), // superstate (top)
Q_STATE_CAST(&eating),
Q_ACTION_CAST(&eating_e),
Q_ACTION_CAST(&eating_x),
Q_ACTION_CAST(0) // no intitial tran.
};
// ${AOs::Philo::SM::eating}
QP::QState Philo::eating_e(Philo * const me) {
me->m_timeEvt.armX(eat_time(), 0U);
return QM_ENTRY(&eating_s);
}
// ${AOs::Philo::SM::eating}
QP::QState Philo::eating_x(Philo * const me) {
TableEvt *pe = Q_NEW(TableEvt, DONE_SIG);
pe->philoNum = PHILO_ID(me);
QP::QF::PUBLISH(pe, me);
(void)me->m_timeEvt.disarm();
return QM_EXIT(&eating_s);
}
// ${AOs::Philo::SM::eating}
QP::QState Philo::eating(Philo * const me, QP::QEvt const * const e) {
QP::QState status_;
switch (e->sig) {
// ${AOs::Philo::SM::eating::TIMEOUT}
case TIMEOUT_SIG: {
static struct {
QP::QMState const *target;
QP::QActionHandler act[3];
} const tatbl_ = { // transition-action table
&thinking_s,
{
Q_ACTION_CAST(&eating_x), // exit
Q_ACTION_CAST(&thinking_e), // entry
Q_ACTION_CAST(0) // zero terminator
}
};
status_ = QM_TRAN(&tatbl_);
break;
}
// ${AOs::Philo::SM::eating::EAT, DONE}
case EAT_SIG: /* intentionally fall through */
case DONE_SIG: {
/* EAT or DONE must be for other Philos than this one */
Q_ASSERT(Q_EVT_CAST(TableEvt)->philoNum != PHILO_ID(me));
status_ = QM_HANDLED();
break;
}
default: {
status_ = QM_SUPER();
break;
}
}
return status_;
}
} // namespace DPP

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examples/freertos/iar/dpp_ek-tm4c123gxl/rom.h Normal file
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examples/freertos/iar/dpp_ek-tm4c123gxl/startup_tm4c.c Normal file
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/*****************************************************************************
// This TM4C startup file has been adapted from startup_ewarm.c
// Quantum Leaps on 28-Jul-2014
// www.state-machine.com
*****************************************************************************/
//*****************************************************************************
//
// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench,
// version 5.
//
// Copyright (c) 2012-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2.0.1.11577 of the EK-TM4C123GXL Firmware Package.
//
//*****************************************************************************
#include "tm4c_cmsis.h"
/* Enable the IAR extensions for this source file */
#pragma language=extended
/* Function prototypes -----------------------------------------------------*/
void __iar_program_start(void); /* IAR startup code */
void Spurious_Handler(void); /* spurious exception/interrupt handler */
/* CSTACK section limits (created by the IAR linker) -----------------------*/
extern int CSTACK$$Base; /* symbol created by the IAR linker */
extern int CSTACK$$Limit; /* symbol created by the IAR linker */
/* exception and interrupt vector table ------------------------------------*/
typedef void (*handler)(void); /* pointer to handler function type */
/*..........................................................................*/
__root handler const __vector_table[] @ ".intvec" = {
(handler)&CSTACK$$Limit, /* The initial stack pointer */
&__iar_program_start, /* Reset Handler */
&NMI_Handler, /* NMI Handler */
&HardFault_Handler, /* Hard Fault Handler */
&MemManage_Handler, /* MPU Fault Handler */
&BusFault_Handler, /* Bus Fault Handler */
&UsageFault_Handler, /* Usage Fault Handler */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&SVC_Handler, /* SVCall Handler */
&DebugMon_Handler, /* Debug Monitor Handler */
&Spurious_Handler, /* Reserved */
&PendSV_Handler, /* PendSV Handler */
&SysTick_Handler, /* SysTick Handler */
/* external interrupts (IRQs) ... */
&GPIOPortA_IRQHandler, /* GPIO Port A */
&GPIOPortB_IRQHandler, /* GPIO Port B */
&GPIOPortC_IRQHandler, /* GPIO Port C */
&GPIOPortD_IRQHandler, /* GPIO Port D */
&GPIOPortE_IRQHandler, /* GPIO Port E */
&UART0_IRQHandler, /* UART0 Rx and Tx */
&UART1_IRQHandler, /* UART1 Rx and Tx */
&SSI0_IRQHandler, /* SSI0 Rx and Tx */
&I2C0_IRQHandler, /* I2C0 Master and Slave */
&PWMFault_IRQHandler, /* PWM Fault */
&PWMGen0_IRQHandler, /* PWM Generator 0 */
&PWMGen1_IRQHandler, /* PWM Generator 1 */
&PWMGen2_IRQHandler, /* PWM Generator 2 */
&QEI0_IRQHandler, /* Quadrature Encoder 0 */
&ADCSeq0_IRQHandler, /* ADC Sequence 0 */
&ADCSeq1_IRQHandler, /* ADC Sequence 1 */
&ADCSeq2_IRQHandler, /* ADC Sequence 2 */
&ADCSeq3_IRQHandler, /* ADC Sequence 3 */
&Watchdog_IRQHandler, /* Watchdog timer */
&Timer0A_IRQHandler, /* Timer 0 subtimer A */
&Timer0B_IRQHandler, /* Timer 0 subtimer B */
&Timer1A_IRQHandler, /* Timer 1 subtimer A */
&Timer1B_IRQHandler, /* Timer 1 subtimer B */
&Timer2A_IRQHandler, /* Timer 2 subtimer A */
&Timer2B_IRQHandler, /* Timer 2 subtimer B */
&Comp0_IRQHandler, /* Analog Comparator 0 */
&Comp1_IRQHandler, /* Analog Comparator 1 */
&Comp2_IRQHandler, /* Analog Comparator 2 */
&SysCtrl_IRQHandler, /* System Control (PLL,OSC,BO) */
&FlashCtrl_IRQHandler, /* FLASH Control */
&GPIOPortF_IRQHandler, /* GPIO Port F */
&GPIOPortG_IRQHandler, /* GPIO Port G */
&GPIOPortH_IRQHandler, /* GPIO Port H */
&UART2_IRQHandler, /* UART2 Rx and Tx */
&SSI1_IRQHandler , /* SSI1 Rx and Tx */
&Timer3A_IRQHandler, /* Timer 3 subtimer A */
&Timer3B_IRQHandler, /* Timer 3 subtimer B */
&I2C1_IRQHandler, /* I2C1 Master and Slave */
&QEI1_IRQHandler, /* Quadrature Encoder 1 */
&CAN0_IRQHandler, /* CAN0 */
&CAN1_IRQHandler, /* CAN1 */
&CAN2_IRQHandler, /* CAN2 */
&Spurious_Handler, /* Reserved */
&Hibernate_IRQHandler, /* Hibernate */
&USB0_IRQHandler, /* USB0 */
&PWMGen3_IRQHandler, /* PWM Generator 3 */
&uDMAST_IRQHandler, /* uDMA Software Transfer */
&uDMAError_IRQHandler, /* uDMA Error */
&ADC1Seq0_IRQHandler, /* ADC1 Sequence 0 */
&ADC1Seq1_IRQHandler, /* ADC1 Sequence 1 */
&ADC1Seq2_IRQHandler, /* ADC1 Sequence 2 */
&ADC1Seq3_IRQHandler, /* ADC1 Sequence 3 */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&GPIOPortJ_IRQHandler, /* GPIO Port J */
&GPIOPortK_IRQHandler, /* GPIO Port K */
&GPIOPortL_IRQHandler, /* GPIO Port L */
&SSI2_IRQHandler, /* SSI2 Rx and Tx */
&SSI3_IRQHandler, /* SSI3 Rx and Tx */
&UART3_IRQHandler, /* UART3 Rx and Tx */
&UART4_IRQHandler, /* UART4 Rx and Tx */
&UART5_IRQHandler, /* UART5 Rx and Tx */
&UART6_IRQHandler, /* UART6 Rx and Tx */
&UART7_IRQHandler, /* UART7 Rx and Tx */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&I2C2_IRQHandler, /* I2C2 Master and Slave */
&I2C3_IRQHandler, /* I2C3 Master and Slave */
&Timer4A_IRQHandler, /* Timer 4 subtimer A */
&Timer4B_IRQHandler, /* Timer 4 subtimer B */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&Timer5A_IRQHandler, /* Timer 5 subtimer A */
&Timer5B_IRQHandler, /* Timer 5 subtimer B */
&WideTimer0A_IRQHandler, /* Wide Timer 0 subtimer A */
&WideTimer0B_IRQHandler, /* Wide Timer 0 subtimer B */
&WideTimer1A_IRQHandler, /* Wide Timer 1 subtimer A */
&WideTimer1B_IRQHandler, /* Wide Timer 1 subtimer B */
&WideTimer2A_IRQHandler, /* Wide Timer 2 subtimer A */
&WideTimer2B_IRQHandler, /* Wide Timer 2 subtimer B */
&WideTimer3A_IRQHandler, /* Wide Timer 3 subtimer A */
&WideTimer3B_IRQHandler, /* Wide Timer 3 subtimer B */
&WideTimer4A_IRQHandler, /* Wide Timer 4 subtimer A */
&WideTimer4B_IRQHandler, /* Wide Timer 4 subtimer B */
&WideTimer5A_IRQHandler, /* Wide Timer 5 subtimer A */
&WideTimer5B_IRQHandler, /* Wide Timer 5 subtimer B */
&FPU_IRQHandler, /* FPU */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&I2C4_IRQHandler, /* I2C4 Master and Slave */
&I2C5_IRQHandler, /* I2C5 Master and Slave */
&GPIOPortM_IRQHandler, /* GPIO Port M */
&GPIOPortN_IRQHandler, /* GPIO Port N */
&QEI2_IRQHandler, /* Quadrature Encoder 2 */
&Spurious_Handler, /* Reserved */
&Spurious_Handler, /* Reserved */
&GPIOPortP0_IRQHandler, /* GPIO Port P (Summary or P0) */
&GPIOPortP1_IRQHandler, /* GPIO Port P1 */
&GPIOPortP2_IRQHandler, /* GPIO Port P2 */
&GPIOPortP3_IRQHandler, /* GPIO Port P3 */
&GPIOPortP4_IRQHandler, /* GPIO Port P4 */
&GPIOPortP5_IRQHandler, /* GPIO Port P5 */
&GPIOPortP6_IRQHandler, /* GPIO Port P6 */
&GPIOPortP7_IRQHandler, /* GPIO Port P7 */
&GPIOPortQ0_IRQHandler, /* GPIO Port Q (Summary or Q0) */
&GPIOPortQ1_IRQHandler, /* GPIO Port Q1 */
&GPIOPortQ2_IRQHandler, /* GPIO Port Q2 */
&GPIOPortQ3_IRQHandler, /* GPIO Port Q3 */
&GPIOPortQ4_IRQHandler, /* GPIO Port Q4 */
&GPIOPortQ5_IRQHandler, /* GPIO Port Q5 */
&GPIOPortQ6_IRQHandler, /* GPIO Port Q6 */
&GPIOPortQ7_IRQHandler, /* GPIO Port Q7 */
&GPIOPortR_IRQHandler, /* GPIO Port R */
&GPIOPortS_IRQHandler, /* GPIO Port S */
&PWM1Gen0_IRQHandler, /* PWM 1 Generator 0 */
&PWM1Gen1_IRQHandler, /* PWM 1 Generator 1 */
&PWM1Gen2_IRQHandler, /* PWM 1 Generator 2 */
&PWM1Gen3_IRQHandler, /* PWM 1 Generator 3 */
&PWM1Fault_IRQHandler /* PWM 1 Fault */
};
/* exception handlers ------------------------------------------------------*/
/*..........................................................................*/
__stackless void NMI_Handler(void) {
assert_failed("NMI", __LINE__); /* should never return! */
}
/*..........................................................................*/
__stackless void MemManage_Handler(void) {
assert_failed("MemManage", __LINE__); /* should never return! */
}
/*..........................................................................*/
__stackless void HardFault_Handler(void) {
unsigned old_sp = __get_SP();
if (old_sp < (unsigned)&CSTACK$$Base) { /* stack overflow? */
__set_SP((unsigned)&CSTACK$$Limit); /* initial stack pointer */
assert_failed("StackOverflow", old_sp); /* should never return! */
}
else {
assert_failed("HardFault", __LINE__); /* should never return! */
}
}
/*..........................................................................*/
__stackless void BusFault_Handler(void) {
assert_failed("BusFault", __LINE__); /* should never return! */
}
/*..........................................................................*/
__stackless void UsageFault_Handler(void) {
assert_failed("UsageFault", __LINE__); /* should never return! */
}
/*..........................................................................*/
__stackless void Spurious_Handler(void) {
assert_failed("Spurious", __LINE__); /* should never return! */
}
/*----------------------------------------------------------------------------
* Weak aliases for each Exception handler to the Spurious_Handler.
*/
#pragma weak SVC_Handler = Spurious_Handler
#pragma weak DebugMon_Handler = Spurious_Handler
#pragma weak PendSV_Handler = Spurious_Handler
#pragma weak SysTick_Handler = Spurious_Handler
#pragma weak GPIOPortA_IRQHandler = Spurious_Handler
#pragma weak GPIOPortB_IRQHandler = Spurious_Handler
#pragma weak GPIOPortC_IRQHandler = Spurious_Handler
#pragma weak GPIOPortD_IRQHandler = Spurious_Handler
#pragma weak GPIOPortE_IRQHandler = Spurious_Handler
#pragma weak UART0_IRQHandler = Spurious_Handler
#pragma weak UART1_IRQHandler = Spurious_Handler
#pragma weak SSI0_IRQHandler = Spurious_Handler
#pragma weak I2C0_IRQHandler = Spurious_Handler
#pragma weak PWMFault_IRQHandler = Spurious_Handler
#pragma weak PWMGen0_IRQHandler = Spurious_Handler
#pragma weak PWMGen1_IRQHandler = Spurious_Handler
#pragma weak PWMGen2_IRQHandler = Spurious_Handler
#pragma weak QEI0_IRQHandler = Spurious_Handler
#pragma weak ADCSeq0_IRQHandler = Spurious_Handler
#pragma weak ADCSeq1_IRQHandler = Spurious_Handler
#pragma weak ADCSeq2_IRQHandler = Spurious_Handler
#pragma weak ADCSeq3_IRQHandler = Spurious_Handler
#pragma weak Watchdog_IRQHandler = Spurious_Handler
#pragma weak Timer0A_IRQHandler = Spurious_Handler
#pragma weak Timer0B_IRQHandler = Spurious_Handler
#pragma weak Timer1A_IRQHandler = Spurious_Handler
#pragma weak Timer1B_IRQHandler = Spurious_Handler
#pragma weak Timer2A_IRQHandler = Spurious_Handler
#pragma weak Timer2B_IRQHandler = Spurious_Handler
#pragma weak Comp0_IRQHandler = Spurious_Handler
#pragma weak Comp1_IRQHandler = Spurious_Handler
#pragma weak Comp2_IRQHandler = Spurious_Handler
#pragma weak SysCtrl_IRQHandler = Spurious_Handler
#pragma weak FlashCtrl_IRQHandler = Spurious_Handler
#pragma weak GPIOPortF_IRQHandler = Spurious_Handler
#pragma weak GPIOPortG_IRQHandler = Spurious_Handler
#pragma weak GPIOPortH_IRQHandler = Spurious_Handler
#pragma weak UART2_IRQHandler = Spurious_Handler
#pragma weak SSI1_IRQHandler = Spurious_Handler
#pragma weak Timer3A_IRQHandler = Spurious_Handler
#pragma weak Timer3B_IRQHandler = Spurious_Handler
#pragma weak I2C1_IRQHandler = Spurious_Handler
#pragma weak QEI1_IRQHandler = Spurious_Handler
#pragma weak CAN0_IRQHandler = Spurious_Handler
#pragma weak CAN1_IRQHandler = Spurious_Handler
#pragma weak CAN2_IRQHandler = Spurious_Handler
#pragma weak Hibernate_IRQHandler = Spurious_Handler
#pragma weak USB0_IRQHandler = Spurious_Handler
#pragma weak PWMGen3_IRQHandler = Spurious_Handler
#pragma weak uDMAST_IRQHandler = Spurious_Handler
#pragma weak uDMAError_IRQHandler = Spurious_Handler
#pragma weak ADC1Seq0_IRQHandler = Spurious_Handler
#pragma weak ADC1Seq1_IRQHandler = Spurious_Handler
#pragma weak ADC1Seq2_IRQHandler = Spurious_Handler
#pragma weak ADC1Seq3_IRQHandler = Spurious_Handler
#pragma weak I2S0_IRQHandler = Spurious_Handler
#pragma weak EBI0_IRQHandler = Spurious_Handler
#pragma weak GPIOPortJ_IRQHandler = Spurious_Handler
#pragma weak GPIOPortK_IRQHandler = Spurious_Handler
#pragma weak GPIOPortL_IRQHandler = Spurious_Handler
#pragma weak SSI2_IRQHandler = Spurious_Handler
#pragma weak SSI3_IRQHandler = Spurious_Handler
#pragma weak UART3_IRQHandler = Spurious_Handler
#pragma weak UART4_IRQHandler = Spurious_Handler
#pragma weak UART5_IRQHandler = Spurious_Handler
#pragma weak UART6_IRQHandler = Spurious_Handler
#pragma weak UART7_IRQHandler = Spurious_Handler
#pragma weak I2C2_IRQHandler = Spurious_Handler
#pragma weak I2C3_IRQHandler = Spurious_Handler
#pragma weak Timer4A_IRQHandler = Spurious_Handler
#pragma weak Timer4B_IRQHandler = Spurious_Handler
#pragma weak Timer5A_IRQHandler = Spurious_Handler
#pragma weak Timer5B_IRQHandler = Spurious_Handler
#pragma weak WideTimer0A_IRQHandler = Spurious_Handler
#pragma weak WideTimer0B_IRQHandler = Spurious_Handler
#pragma weak WideTimer1A_IRQHandler = Spurious_Handler
#pragma weak WideTimer1B_IRQHandler = Spurious_Handler
#pragma weak WideTimer2A_IRQHandler = Spurious_Handler
#pragma weak WideTimer2B_IRQHandler = Spurious_Handler
#pragma weak WideTimer3A_IRQHandler = Spurious_Handler
#pragma weak WideTimer3B_IRQHandler = Spurious_Handler
#pragma weak WideTimer4A_IRQHandler = Spurious_Handler
#pragma weak WideTimer4B_IRQHandler = Spurious_Handler
#pragma weak WideTimer5A_IRQHandler = Spurious_Handler
#pragma weak WideTimer5B_IRQHandler = Spurious_Handler
#pragma weak FPU_IRQHandler = Spurious_Handler
#pragma weak PECI0_IRQHandler = Spurious_Handler
#pragma weak LPC0_IRQHandler = Spurious_Handler
#pragma weak I2C4_IRQHandler = Spurious_Handler
#pragma weak I2C5_IRQHandler = Spurious_Handler
#pragma weak GPIOPortM_IRQHandler = Spurious_Handler
#pragma weak GPIOPortN_IRQHandler = Spurious_Handler
#pragma weak QEI2_IRQHandler = Spurious_Handler
#pragma weak Fan0_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP0_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP1_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP2_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP3_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP4_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP5_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP6_IRQHandler = Spurious_Handler
#pragma weak GPIOPortP7_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ0_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ1_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ2_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ3_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ4_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ5_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ6_IRQHandler = Spurious_Handler
#pragma weak GPIOPortQ7_IRQHandler = Spurious_Handler
#pragma weak GPIOPortR_IRQHandler = Spurious_Handler
#pragma weak GPIOPortS_IRQHandler = Spurious_Handler
#pragma weak PWM1Gen0_IRQHandler = Spurious_Handler
#pragma weak PWM1Gen1_IRQHandler = Spurious_Handler
#pragma weak PWM1Gen2_IRQHandler = Spurious_Handler
#pragma weak PWM1Gen3_IRQHandler = Spurious_Handler
#pragma weak PWM1Fault_IRQHandler = Spurious_Handler

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examples/freertos/iar/dpp_ek-tm4c123gxl/sysctl.h Normal file
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//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
typedef unsigned char tBoolean;
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#ifndef DEPRECATED
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#endif
#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
#ifndef DEPRECATED
#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
#endif
#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#endif
#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
#ifndef DEPRECATED
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
#endif
#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
#endif
#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
#endif
#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
#define SYSCTL_PERIPH_ETH 0x20105000 // Ethernet
#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0
#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1
#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0
#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1
#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2
#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
#define SYSCTL_PERIPH2_EPI0 0xf0001000 // EPI0
#define SYSCTL_PERIPH2_ETH 0xf0002c00 // ETH
#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A
#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B
#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C
#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D
#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E
#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F
#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G
#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H
#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J
#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module
#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0
#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1
#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
#define SYSCTL_PERIPH2_I2S0 0xf0002400 // I2S0
#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0
#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0
#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0
#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0
#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1
#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0
#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1
#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0
#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1
#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2
#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3
#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0
#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1
#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2
#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA
#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0
#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0
#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1
#define SYSCTL_PERIPH2_HIBERNATE \
0xf0001400 // Hibernate
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPinPresent() API
// as the ulPin parameter.
//
//*****************************************************************************
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSet() API as
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
//
//*****************************************************************************
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
//
//*****************************************************************************
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPWMClockSet() API
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
// API.
//
//*****************************************************************************
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlADCSpeedSet() API
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
// API.
//
//*****************************************************************************
#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second
#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second
#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlDeepSleepClockSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(unsigned long ulInts);
extern void SysCtlIntDisable(unsigned long ulInts);
extern void SysCtlIntClear(unsigned long ulInts);
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
extern void SysCtlLDOSet(unsigned long ulVoltage);
extern unsigned long SysCtlLDOGet(void);
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern unsigned long SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlDelay(unsigned long ulCount);
extern void SysCtlMOSCConfigSet(unsigned long ulConfig);
extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlDeepSleepClockSet(unsigned long ulConfig);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
extern unsigned long SysCtlADCSpeedGet(void);
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
extern void SysCtlClkVerificationClear(void);
extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
extern void SysCtlUSBPLLEnable(void);
extern void SysCtlUSBPLLDisable(void);
extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
unsigned long ulMClk);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSCTL_H__

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@ -0,0 +1,359 @@
//****************************************************************************
// Model: dpp.qm
// File: ./table.cpp
//
// This code has been generated by QM tool (see state-machine.com/qm).
// DO NOT EDIT THIS FILE MANUALLY. All your changes will be lost.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//****************************************************************************
//${.::table.cpp} ............................................................
#include "qp_port.h"
#include "dpp.h"
#include "bsp.h"
Q_DEFINE_THIS_FILE
// Active object class -------------------------------------------------------
namespace DPP {
//${AOs::Table} ..............................................................
class Table : public QP::QMActive {
private:
uint8_t m_fork[N_PHILO];
bool m_isHungry[N_PHILO];
public:
Table();
protected:
static QP::QState initial(Table * const me, QP::QEvt const * const e);
static QP::QState active (Table * const me, QP::QEvt const * const e);
static QP::QMState const active_s;
static QP::QState serving (Table * const me, QP::QEvt const * const e);
static QP::QState serving_e(Table * const me);
static QP::QMState const serving_s;
static QP::QState paused (Table * const me, QP::QEvt const * const e);
static QP::QState paused_e(Table * const me);
static QP::QState paused_x(Table * const me);
static QP::QMState const paused_s;
};
} // namespace DPP
namespace DPP {
// helper function to provide the RIGHT neighbour of a Philo[n]
inline uint8_t RIGHT(uint8_t const n) {
return static_cast<uint8_t>((n + (N_PHILO - 1U)) % N_PHILO);
}
// helper function to provide the LEFT neighbour of a Philo[n]
inline uint8_t LEFT(uint8_t const n) {
return static_cast<uint8_t>((n + 1U) % N_PHILO);
}
static uint8_t const FREE = static_cast<uint8_t>(0);
static uint8_t const USED = static_cast<uint8_t>(1);
static char_t const * const THINKING = &"thinking"[0];
static char_t const * const HUNGRY = &"hungry "[0];
static char_t const * const EATING = &"eating "[0];
// Local objects -------------------------------------------------------------
static Table l_table; // the single instance of the Table active object
// Global-scope objects ------------------------------------------------------
QP::QActive * const AO_Table = &l_table; // "opaque" AO pointer
} // namespace DPP
//............................................................................
namespace DPP {
//${AOs::Table} ..............................................................
//${AOs::Table::Table} .......................................................
Table::Table()
: QMActive(Q_STATE_CAST(&Table::initial))
{
for (uint8_t n = 0U; n < N_PHILO; ++n) {
m_fork[n] = FREE;
m_isHungry[n] = false;
}
}
//${AOs::Table::SM} ..........................................................
QP::QState Table::initial(Table * const me, QP::QEvt const * const e) {
static struct {
QP::QMState const *target;
QP::QActionHandler act[2];
} const tatbl_ = { // transition-action table
&serving_s,
{
Q_ACTION_CAST(&serving_e), // entry
Q_ACTION_CAST(0) // zero terminator
}
};
// ${AOs::Table::SM::initial}
(void)e; // suppress the compiler warning about unused parameter
QS_OBJ_DICTIONARY(&l_table);
QS_FUN_DICTIONARY(&QP::QHsm::top);
QS_FUN_DICTIONARY(&Table::initial);
QS_FUN_DICTIONARY(&Table::active);
QS_FUN_DICTIONARY(&Table::serving);
QS_FUN_DICTIONARY(&Table::paused);
QS_SIG_DICTIONARY(DONE_SIG, (void *)0); // global signals
QS_SIG_DICTIONARY(EAT_SIG, (void *)0);
QS_SIG_DICTIONARY(PAUSE_SIG, (void *)0);
QS_SIG_DICTIONARY(TERMINATE_SIG, (void *)0);
QS_SIG_DICTIONARY(HUNGRY_SIG, me); // signal just for Table
me->subscribe(DONE_SIG);
me->subscribe(PAUSE_SIG);
me->subscribe(TERMINATE_SIG);
for (uint8_t n = 0U; n < N_PHILO; ++n) {
me->m_fork[n] = FREE;
me->m_isHungry[n] = false;
BSP_displayPhilStat(n, THINKING);
}
return QM_TRAN_INIT(&tatbl_);
}
//${AOs::Table::SM::active} ..................................................
QP::QMState const Table::active_s = {
static_cast<QP::QMState const *>(0), // superstate (top)
Q_STATE_CAST(&active),
Q_ACTION_CAST(0), // no entry action
Q_ACTION_CAST(0), // no exit action
Q_ACTION_CAST(0) // no intitial tran.
};
// ${AOs::Table::SM::active}
QP::QState Table::active(Table * const me, QP::QEvt const * const e) {
QP::QState status_;
switch (e->sig) {
// ${AOs::Table::SM::active::TERMINATE}
case TERMINATE_SIG: {
BSP_terminate(0);
status_ = QM_HANDLED();
break;
}
// ${AOs::Table::SM::active::EAT}
case EAT_SIG: {
Q_ERROR();
status_ = QM_HANDLED();
break;
}
default: {
status_ = QM_SUPER();
break;
}
}
(void)me; /* avoid compiler warning in case 'me' is not used */
return status_;
}
//${AOs::Table::SM::active::serving} .........................................
QP::QMState const Table::serving_s = {
&Table::active_s, // superstate
Q_STATE_CAST(&serving),
Q_ACTION_CAST(&serving_e),
Q_ACTION_CAST(0), // no exit action
Q_ACTION_CAST(0) // no intitial tran.
};
// ${AOs::Table::SM::active::serving}
QP::QState Table::serving_e(Table * const me) {
for (uint8_t n = 0U; n < N_PHILO; ++n) { // give permissions to eat...
if (me->m_isHungry[n]
&& (me->m_fork[LEFT(n)] == FREE)
&& (me->m_fork[n] == FREE))
{
me->m_fork[LEFT(n)] = USED;
me->m_fork[n] = USED;
TableEvt *te = Q_NEW(TableEvt, EAT_SIG);
te->philoNum = n;
QP::QF::PUBLISH(te, me);
me->m_isHungry[n] = false;
BSP_displayPhilStat(n, EATING);
}
}
return QM_ENTRY(&serving_s);
}
// ${AOs::Table::SM::active::serving}
QP::QState Table::serving(Table * const me, QP::QEvt const * const e) {
QP::QState status_;
switch (e->sig) {
// ${AOs::Table::SM::active::serving::HUNGRY}
case HUNGRY_SIG: {
uint8_t n = Q_EVT_CAST(TableEvt)->philoNum;
// phil ID must be in range and he must be not hungry
Q_ASSERT((n < N_PHILO) && (!me->m_isHungry[n]));
BSP_displayPhilStat(n, HUNGRY);
uint8_t m = LEFT(n);
// ${AOs::Table::SM::active::serving::HUNGRY::[bothfree]}
if ((me->m_fork[m] == FREE) && (me->m_fork[n] == FREE)) {
me->m_fork[m] = USED;
me->m_fork[n] = USED;
TableEvt *pe = Q_NEW(TableEvt, EAT_SIG);
pe->philoNum = n;
QP::QF::PUBLISH(pe, me);
BSP_displayPhilStat(n, EATING);
status_ = QM_HANDLED();
}
// ${AOs::Table::SM::active::serving::HUNGRY::[else]}
else {
me->m_isHungry[n] = true;
status_ = QM_HANDLED();
}
break;
}
// ${AOs::Table::SM::active::serving::DONE}
case DONE_SIG: {
uint8_t n = Q_EVT_CAST(TableEvt)->philoNum;
// phil ID must be in range and he must be not hungry
Q_ASSERT((n < N_PHILO) && (!me->m_isHungry[n]));
BSP_displayPhilStat(n, THINKING);
uint8_t m = LEFT(n);
// both forks of Phil[n] must be used
Q_ASSERT((me->m_fork[n] == USED) && (me->m_fork[m] == USED));
me->m_fork[m] = FREE;
me->m_fork[n] = FREE;
m = RIGHT(n); // check the right neighbor
if (me->m_isHungry[m] && (me->m_fork[m] == FREE)) {
me->m_fork[n] = USED;
me->m_fork[m] = USED;
me->m_isHungry[m] = false;
TableEvt *pe = Q_NEW(TableEvt, EAT_SIG);
pe->philoNum = m;
QP::QF::PUBLISH(pe, me);
BSP_displayPhilStat(m, EATING);
}
m = LEFT(n); // check the left neighbor
n = LEFT(m); // left fork of the left neighbor
if (me->m_isHungry[m] && (me->m_fork[n] == FREE)) {
me->m_fork[m] = USED;
me->m_fork[n] = USED;
me->m_isHungry[m] = false;
TableEvt *pe = Q_NEW(TableEvt, EAT_SIG);
pe->philoNum = m;
QP::QF::PUBLISH(pe, me);
BSP_displayPhilStat(m, EATING);
}
status_ = QM_HANDLED();
break;
}
// ${AOs::Table::SM::active::serving::EAT}
case EAT_SIG: {
Q_ERROR();
status_ = QM_HANDLED();
break;
}
// ${AOs::Table::SM::active::serving::PAUSE}
case PAUSE_SIG: {
static struct {
QP::QMState const *target;
QP::QActionHandler act[2];
} const tatbl_ = { // transition-action table
&paused_s,
{
Q_ACTION_CAST(&paused_e), // entry
Q_ACTION_CAST(0) // zero terminator
}
};
status_ = QM_TRAN(&tatbl_);
break;
}
default: {
status_ = QM_SUPER();
break;
}
}
return status_;
}
//${AOs::Table::SM::active::paused} ..........................................
QP::QMState const Table::paused_s = {
&Table::active_s, // superstate
Q_STATE_CAST(&paused),
Q_ACTION_CAST(&paused_e),
Q_ACTION_CAST(&paused_x),
Q_ACTION_CAST(0) // no intitial tran.
};
// ${AOs::Table::SM::active::paused}
QP::QState Table::paused_e(Table * const me) {
BSP_displayPaused(1U);
(void)me; // avoid compiler warning in case 'me' is not used
return QM_ENTRY(&paused_s);
}
// ${AOs::Table::SM::active::paused}
QP::QState Table::paused_x(Table * const me) {
BSP_displayPaused(0U);
(void)me; // avoid compiler warning in case 'me' is not used
return QM_EXIT(&paused_s);
}
// ${AOs::Table::SM::active::paused}
QP::QState Table::paused(Table * const me, QP::QEvt const * const e) {
QP::QState status_;
switch (e->sig) {
// ${AOs::Table::SM::active::paused::PAUSE}
case PAUSE_SIG: {
static struct {
QP::QMState const *target;
QP::QActionHandler act[3];
} const tatbl_ = { // transition-action table
&serving_s,
{
Q_ACTION_CAST(&paused_x), // exit
Q_ACTION_CAST(&serving_e), // entry
Q_ACTION_CAST(0) // zero terminator
}
};
status_ = QM_TRAN(&tatbl_);
break;
}
// ${AOs::Table::SM::active::paused::HUNGRY}
case HUNGRY_SIG: {
uint8_t n = Q_EVT_CAST(TableEvt)->philoNum;
// philo ID must be in range and he must be not hungry
Q_ASSERT((n < N_PHILO) && (!me->m_isHungry[n]));
me->m_isHungry[n] = true;
BSP_displayPhilStat(n, HUNGRY);
status_ = QM_HANDLED();
break;
}
// ${AOs::Table::SM::active::paused::DONE}
case DONE_SIG: {
uint8_t n = Q_EVT_CAST(TableEvt)->philoNum;
// phil ID must be in range and he must be not hungry
Q_ASSERT((n < N_PHILO) && (!me->m_isHungry[n]));
BSP_displayPhilStat(n, THINKING);
uint8_t m = LEFT(n);
/* both forks of Phil[n] must be used */
Q_ASSERT((me->m_fork[n] == USED) && (me->m_fork[m] == USED));
me->m_fork[m] = FREE;
me->m_fork[n] = FREE;
status_ = QM_HANDLED();
break;
}
default: {
status_ = QM_SUPER();
break;
}
}
return status_;
}
} // namespace DPP

1227
examples/freertos/iar/dpp_ek-tm4c123gxl/tm4c_cmsis.h Normal file
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File diff suppressed because it is too large Load Diff

20
ports/arm-cm/qk/arm_keil/qk_port.h
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: QK/C++, Cortex-M, QK port, Generic C++ compiler
// Last Updated for Version: 5.2.0
// Date of the Last Update: Dec 08, 2013
// Last Updated for Version: 5.3.1
// Date of the Last Update: 2014-09-24
//
// Q u a n t u m L e a P s
// ---------------------------
@ -28,13 +28,13 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Quantum Leaps Web sites: http://www.quantum-leaps.com
// http://www.state-machine.com
// e-mail: info@quantum-leaps.com
// Web: http://www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#ifndef qk_port_h
#define qk_port_h
// QK interrupt entry and exit
// QK interrupt entry and exit
#define QK_ISR_ENTRY() do { \
QF_INT_DISABLE(); \
++QK_intNest_; \
@ -46,12 +46,10 @@
QF_INT_DISABLE(); \
QF_QS_ISR_EXIT(QK_intNest_, QK_currPrio_); \
--QK_intNest_; \
if (QK_schedPrio_() != (uint8_t)0) { \
*Q_UINT2PTR_CAST(uint32_t, 0xE000ED04U) = (uint32_t)0x10000000U; \
} \
*Q_UINT2PTR_CAST(uint32_t, 0xE000ED04U) = (uint32_t)0x10000000U; \
QF_INT_ENABLE(); \
} while (0)
#include "qk.h" // QK platform-independent public interface
#include "qk.h" // QK platform-independent public interface
#endif // qk_port_h
#endif // qk_port_h

20
ports/arm-cm/qk/gnu/qk_port.h
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: QK/C++, Cortex-M, QK port, Generic C++ compiler
// Last Updated for Version: 5.2.0
// Date of the Last Update: Dec 08, 2013
// Last Updated for Version: 5.3.1
// Date of the Last Update: 2014-09-24
//
// Q u a n t u m L e a P s
// ---------------------------
@ -28,13 +28,13 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Quantum Leaps Web sites: http://www.quantum-leaps.com
// http://www.state-machine.com
// e-mail: info@quantum-leaps.com
// Web: http://www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#ifndef qk_port_h
#define qk_port_h
// QK interrupt entry and exit
// QK interrupt entry and exit
#define QK_ISR_ENTRY() do { \
QF_INT_DISABLE(); \
++QK_intNest_; \
@ -46,12 +46,10 @@
QF_INT_DISABLE(); \
QF_QS_ISR_EXIT(QK_intNest_, QK_currPrio_); \
--QK_intNest_; \
if (QK_schedPrio_() != (uint8_t)0) { \
*Q_UINT2PTR_CAST(uint32_t, 0xE000ED04U) = (uint32_t)0x10000000U; \
} \
*Q_UINT2PTR_CAST(uint32_t, 0xE000ED04U) = (uint32_t)0x10000000U; \
QF_INT_ENABLE(); \
} while (0)
#include "qk.h" // QK platform-independent public interface
#include "qk.h" // QK platform-independent public interface
#endif // qk_port_h
#endif // qk_port_h

20
ports/arm-cm/qk/iar/qk_port.h
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: QK/C++, Cortex-M, QK port, Generic C++ compiler
// Last Updated for Version: 5.2.0
// Date of the Last Update: Dec 08, 2013
// Last Updated for Version: 5.3.1
// Date of the Last Update: 2014-09-24
//
// Q u a n t u m L e a P s
// ---------------------------
@ -28,13 +28,13 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Quantum Leaps Web sites: http://www.quantum-leaps.com
// http://www.state-machine.com
// e-mail: info@quantum-leaps.com
// Web: http://www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#ifndef qk_port_h
#define qk_port_h
// QK interrupt entry and exit
// QK interrupt entry and exit
#define QK_ISR_ENTRY() do { \
QF_INT_DISABLE(); \
++QK_intNest_; \
@ -46,12 +46,10 @@
QF_INT_DISABLE(); \
QF_QS_ISR_EXIT(QK_intNest_, QK_currPrio_); \
--QK_intNest_; \
if (QK_schedPrio_() != (uint8_t)0) { \
*Q_UINT2PTR_CAST(uint32_t, 0xE000ED04U) = (uint32_t)0x10000000U; \
} \
*Q_UINT2PTR_CAST(uint32_t, 0xE000ED04U) = (uint32_t)0x10000000U; \
QF_INT_ENABLE(); \
} while (0)
#include "qk.h" // QK platform-independent public interface
#include "qk.h" // QK platform-independent public interface
#endif // qk_port_h
#endif // qk_port_h

20
ports/arm-cm/qk/ti_arm/qk_port.h
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: QK/C++, Cortex-M, QK port, Generic C++ compiler
// Last Updated for Version: 5.2.0
// Date of the Last Update: Dec 08, 2013
// Last Updated for Version: 5.3.1
// Date of the Last Update: 2014-09-24
//
// Q u a n t u m L e a P s
// ---------------------------
@ -28,13 +28,13 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Quantum Leaps Web sites: http://www.quantum-leaps.com
// http://www.state-machine.com
// e-mail: info@quantum-leaps.com
// Web: http://www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#ifndef qk_port_h
#define qk_port_h
// QK interrupt entry and exit
// QK interrupt entry and exit
#define QK_ISR_ENTRY() do { \
QF_INT_DISABLE(); \
++QK_intNest_; \
@ -46,12 +46,10 @@
QF_INT_DISABLE(); \
QF_QS_ISR_EXIT(QK_intNest_, QK_currPrio_); \
--QK_intNest_; \
if (QK_schedPrio_() != (uint8_t)0) { \
*Q_UINT2PTR_CAST(uint32_t, 0xE000ED04U) = (uint32_t)0x10000000U; \
} \
*Q_UINT2PTR_CAST(uint32_t, 0xE000ED04U) = (uint32_t)0x10000000U; \
QF_INT_ENABLE(); \
} while (0)
#include "qk.h" // QK platform-independent public interface
#include "qk.h" // QK platform-independent public interface
#endif // qk_port_h
#endif // qk_port_h

15
ports/freertos/README.txt Normal file
View File

@ -0,0 +1,15 @@
This directory contains a port of the QP/C++ framework to FreeRTOS.org.
The port has been designed to use the FreeRTOS hardware abstraction
layer, but this port does NOT eliminate all dependencies on the CPU
architecture.
Specifically, this port has been designed for the ARM Cortex-M
(ARM Cortex-M0/M3/M4/M4F) and might need some changes to work with
other CPU architectures.
However, this port should compile with all compilers for ARM Cortex-M.
Quantun Leaps
state-machine.com
info@state-machine.com

117
ports/freertos/conf/FreeRTOSConfig.h Normal file
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@ -0,0 +1,117 @@
/*
Dummy config file for the QP-FreeRTOS port
Quantum Leaps, LLC, www.state-machine.com
NOTE: the actual values of the FreeRTOS configuration macros do not
really matter. This dummy file is only used to pass the FreeRTOS sanity
checks in the header files, but not to actually build any FreeRTOS code.
*/
/*
FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 )
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 0
#define configMAX_PRIORITIES ( 32 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 0
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

176
ports/freertos/iar/make_cortex-m3.bat Normal file
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@ -0,0 +1,176 @@
@echo off
:: ===========================================================================
:: Product: QP/C++ buld script for ARM Cortex-M3, FreeRTOS port, IAR compiler
:: Last updated for version 5.3.1
:: Last updated on 2014-09-29
::
:: Q u a n t u m L e a P s
:: ---------------------------
:: innovating embedded systems
::
:: Copyright (C) Quantum Leaps, www.state-machine.com.
::
:: This program is open source software: you can redistribute it and/or
:: modify it under the terms of the GNU General Public License as published
:: by the Free Software Foundation, either version 3 of the License, or
:: (at your option) any later version.
::
:: Alternatively, this program may be distributed and modified under the
:: terms of Quantum Leaps commercial licenses, which expressly supersede
:: the GNU General Public License and are specifically designed for
:: licensees interested in retaining the proprietary status of their code.
::
:: This program is distributed in the hope that it will be useful,
:: but WITHOUT ANY WARRANTY; without even the implied warranty of
:: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
:: GNU General Public License for more details.
::
:: You should have received a copy of the GNU General Public License
:: along with this program. If not, see <http://www.gnu.org/licenses/>.
::
:: Contact information:
:: Web: www.state-machine.com
:: Email: info@state-machine.com
:: ===========================================================================
setlocal
:: define the IAR_ARM environment variable to point to the location
:: where you've installed the IAR toolset or adjust the following
:: set instruction
::if "%IAR_ARM%"=="" set IAR_ARM="C:\Program Files\IAR Systems\Embedded Workbench 7.10"
if "%IAR_ARM%"=="" set IAR_ARM="C:\tools\IAR\ARM_KS_7.10"
:: define the FREERTOS environment variable to point to the location
:: where you've installed the FreeRTOS
if "%FREERTOS%"=="" set FREERTOS="D:\software\FreeRTOSV8.1.2"
set PATH=%IAR_ARM%\arm\bin;%IAR_ARM%\common\bin;%PATH%
set CC=iccarm
set ASM=iasmarm
set LIB=iarchive
set QP_INCDIR=..\..\..\include
set QP_PRTDIR=..
set FREERTOS_INC=%FREERTOS%\FreeRTOS\Source\include
set FREERTOS_PORT=%FREERTOS%\FreeRTOS\Source\portable\IAR\ARM_CM3
set FREERTOS_CONF=..\conf
set ARM_CORE=cortex-m3
set ARM_FPU=none
if "%1"=="" (
echo default selected
set BINDIR=.\dbg
set CCOPT=-Ol
set CCFLAGS=-D DEBUG --debug --endian little --cpu=%ARM_CORE% --fpu %ARM_FPU% --eec++ -e --dlib_config %IAR_ARM%\ARM\INC\c\DLib_Config_Normal.h --diag_suppress Pa050 --no_static_destruction
set ASMFLAGS=-s+ -w+ -r --cpu %ARM_CORE% --fpu %ARM_FPU% -I%IAR_ARM%\ARM\INC\
)
if "%1"=="rel" (
echo rel selected
set BINDIR=.\rel
set CCOPT=-Ohs
set CCFLAGS=-D NDEBUG --endian little --cpu %ARM_CORE% --eec++ -e --fpu %ARM_FPU% --dlib_config %IAR_ARM%\ARM\INC\c\DLib_Config_Normal.h --diag_suppress Pa050 --no_static_destruction --no_size_constraints
set ASMFLAGS=-s+ -w+ -r --cpu %ARM_CORE% --fpu %ARM_FPU% -I%IAR_ARM%\ARM\INC\
)
if "%1"=="spy" (
echo spy selected
set BINDIR=.\spy
set CCOPT=-Ol
set CCOPT_QS=-Ohs
set CCFLAGS=-D Q_SPY -D DEBUG --debug --endian little --cpu %ARM_CORE% --fpu %ARM_FPU% --eec++ -e --dlib_config %IAR_ARM%\ARM\INC\c\DLib_Config_Normal.h --diag_suppress Pa050 --no_static_destruction
set ASMFLAGS=-s+ -w+ -r --cpu %ARM_CORE% --fpu %ARM_FPU% -I%IAR_ARM%\ARM\INC\
)
mkdir %BINDIR%
set LIBDIR=%BINDIR%
set LIBFLAGS=-r
erase %LIBDIR%\libqp_%ARM_CORE%.a
:: QEP ----------------------------------------------------------------------
set SRCDIR=..\..\..\qep\source
set CCINC=-I%QP_PRTDIR% -I%QP_INCDIR% -I%FREERTOS_INC% -I%FREERTOS_PORT% -I%FREERTOS_CONF% -I%SRCDIR%
@echo on
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qep.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmsm_ini.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmsm_dis.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmsm_in.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qfsm_ini.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qfsm_dis.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qhsm_ini.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qhsm_dis.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qhsm_top.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qhsm_in.cpp
%LIB% --create %LIBDIR%\libqp_%ARM_CORE%.a %BINDIR%\qep.o %BINDIR%\qmsm_ini.o %BINDIR%\qmsm_dis.o %BINDIR%\qmsm_in.o %BINDIR%\qfsm_ini.o %BINDIR%\qfsm_dis.o %BINDIR%\qhsm_ini.o %BINDIR%\qhsm_dis.o %BINDIR%\qhsm_top.o %BINDIR%\qhsm_in.o
@echo off
erase %BINDIR%\*.o
:: QF -----------------------------------------------------------------------
set SRCDIR=..\..\..\qf\source
set CCINC=-I%QP_PRTDIR% -I%QP_INCDIR% -I%FREERTOS_INC% -I%FREERTOS_PORT% -I%FREERTOS_CONF% -I%SRCDIR%
@echo on
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_defer.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_fifo.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_lifo.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_get_.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_sub.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_usub.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_usuba.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qeq_fifo.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qeq_get.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qeq_init.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qeq_lifo.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_act.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_gc.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_log2.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_new.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_pool.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_psini.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_pspub.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_pwr2.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_tick.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmp_get.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmp_init.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmp_put.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qte_ctor.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qte_ctr.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qte_arm.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qte_darm.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qte_rarm.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %QP_PRTDIR%\qf_port.cpp
%LIB% %LIBFLAGS% %LIBDIR%\libqp_%ARM_CORE%.a %BINDIR%\qa_defer.o %BINDIR%\qa_fifo.o %BINDIR%\qa_lifo.o %BINDIR%\qa_get_.o %BINDIR%\qa_sub.o %BINDIR%\qa_usub.o %BINDIR%\qa_usuba.o %BINDIR%\qeq_fifo.o %BINDIR%\qeq_get.o %BINDIR%\qeq_init.o %BINDIR%\qeq_lifo.o %BINDIR%\qf_act.o %BINDIR%\qf_gc.o %BINDIR%\qf_log2.o %BINDIR%\qf_new.o %BINDIR%\qf_pool.o %BINDIR%\qf_psini.o %BINDIR%\qf_pspub.o %BINDIR%\qf_pwr2.o %BINDIR%\qf_tick.o %BINDIR%\qmp_get.o %BINDIR%\qmp_init.o %BINDIR%\qmp_put.o %BINDIR%\qte_ctor.o %BINDIR%\qte_arm.o %BINDIR%\qte_darm.o %BINDIR%\qte_rarm.o %BINDIR%\qte_ctr.o %BINDIR%\qf_port.o
@echo off
erase %BINDIR%\*.o
:: QS -----------------------------------------------------------------------
if not "%1"=="spy" goto clean
set SRCDIR=..\..\..\qs\source
set CCINC=-I%QP_PRTDIR% -I%QP_INCDIR% -I%FREERTOS_INC% -I%FREERTOS_PORT% -I%FREERTOS_CONF% -I%SRCDIR%
@echo on
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_blk.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_byte.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_dict.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_f32.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_f64.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_mem.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_str.cpp
%LIB% %LIBFLAGS% %LIBDIR%\libqp_%ARM_CORE%.a %BINDIR%\qs.o %BINDIR%\qs_.o %BINDIR%\qs_blk.o %BINDIR%\qs_byte.o %BINDIR%\qs_dict.o %BINDIR%\qs_f32.o %BINDIR%\qs_f64.o %BINDIR%\qs_mem.o %BINDIR%\qs_str.o
@echo off
erase %BINDIR%\*.o
:: --------------------------------------------------------------------------
:clean
@echo off
erase %BINDIR%\tmp*.*
endlocal

176
ports/freertos/iar/make_cortex-m4f.bat Normal file
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@ -0,0 +1,176 @@
@echo off
:: ===========================================================================
:: Product: QP/C++ buld script for ARM Cortex-M4F, FreeRTOS port, IAR compiler
:: Last updated for version 5.3.1
:: Last updated on 2014-09-29
::
:: Q u a n t u m L e a P s
:: ---------------------------
:: innovating embedded systems
::
:: Copyright (C) Quantum Leaps, www.state-machine.com.
::
:: This program is open source software: you can redistribute it and/or
:: modify it under the terms of the GNU General Public License as published
:: by the Free Software Foundation, either version 3 of the License, or
:: (at your option) any later version.
::
:: Alternatively, this program may be distributed and modified under the
:: terms of Quantum Leaps commercial licenses, which expressly supersede
:: the GNU General Public License and are specifically designed for
:: licensees interested in retaining the proprietary status of their code.
::
:: This program is distributed in the hope that it will be useful,
:: but WITHOUT ANY WARRANTY; without even the implied warranty of
:: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
:: GNU General Public License for more details.
::
:: You should have received a copy of the GNU General Public License
:: along with this program. If not, see <http://www.gnu.org/licenses/>.
::
:: Contact information:
:: Web: www.state-machine.com
:: Email: info@state-machine.com
:: ===========================================================================
setlocal
:: define the IAR_ARM environment variable to point to the location
:: where you've installed the IAR toolset or adjust the following
:: set instruction
::if "%IAR_ARM%"=="" set IAR_ARM="C:\Program Files\IAR Systems\Embedded Workbench 7.10"
if "%IAR_ARM%"=="" set IAR_ARM="C:\tools\IAR\ARM_KS_7.10"
:: define the FREERTOS environment variable to point to the location
:: where you've installed the FreeRTOS
if "%FREERTOS%"=="" set FREERTOS="D:\software\FreeRTOSV8.1.2"
set PATH=%IAR_ARM%\arm\bin;%IAR_ARM%\common\bin;%PATH%
set CC=iccarm
set ASM=iasmarm
set LIB=iarchive
set QP_INCDIR=..\..\..\include
set QP_PRTDIR=..
set FREERTOS_INC=%FREERTOS%\FreeRTOS\Source\include
set FREERTOS_PORT=%FREERTOS%\FreeRTOS\Source\portable\IAR\ARM_CM4F
set FREERTOS_CONF=..\conf
set ARM_CORE=cortex-m4f
set ARM_FPU=VFPv4_sp
if "%1"=="" (
echo default selected
set BINDIR=.\dbg
set CCOPT=-Ol
set CCFLAGS=-D DEBUG --debug --endian little --cpu=%ARM_CORE% --fpu %ARM_FPU% --eec++ -e --dlib_config %IAR_ARM%\ARM\INC\c\DLib_Config_Normal.h --diag_suppress Pa050 --no_static_destruction
set ASMFLAGS=-s+ -w+ -r --cpu %ARM_CORE% --fpu %ARM_FPU% -I%IAR_ARM%\ARM\INC\
)
if "%1"=="rel" (
echo rel selected
set BINDIR=.\rel
set CCOPT=-Ohs
set CCFLAGS=-D NDEBUG --endian little --cpu %ARM_CORE% --eec++ -e --fpu %ARM_FPU% --dlib_config %IAR_ARM%\ARM\INC\c\DLib_Config_Normal.h --diag_suppress Pa050 --no_static_destruction --no_size_constraints
set ASMFLAGS=-s+ -w+ -r --cpu %ARM_CORE% --fpu %ARM_FPU% -I%IAR_ARM%\ARM\INC\
)
if "%1"=="spy" (
echo spy selected
set BINDIR=.\spy
set CCOPT=-Ol
set CCOPT_QS=-Ohs
set CCFLAGS=-D Q_SPY -D DEBUG --debug --endian little --cpu %ARM_CORE% --fpu %ARM_FPU% --eec++ -e --dlib_config %IAR_ARM%\ARM\INC\c\DLib_Config_Normal.h --diag_suppress Pa050 --no_static_destruction
set ASMFLAGS=-s+ -w+ -r --cpu %ARM_CORE% --fpu %ARM_FPU% -I%IAR_ARM%\ARM\INC\
)
mkdir %BINDIR%
set LIBDIR=%BINDIR%
set LIBFLAGS=-r
erase %LIBDIR%\libqp_%ARM_CORE%.a
:: QEP ----------------------------------------------------------------------
set SRCDIR=..\..\..\qep\source
set CCINC=-I%QP_PRTDIR% -I%QP_INCDIR% -I%FREERTOS_INC% -I%FREERTOS_PORT% -I%FREERTOS_CONF% -I%SRCDIR%
@echo on
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qep.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmsm_ini.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmsm_dis.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmsm_in.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qfsm_ini.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qfsm_dis.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qhsm_ini.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qhsm_dis.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qhsm_top.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qhsm_in.cpp
%LIB% --create %LIBDIR%\libqp_%ARM_CORE%.a %BINDIR%\qep.o %BINDIR%\qmsm_ini.o %BINDIR%\qmsm_dis.o %BINDIR%\qmsm_in.o %BINDIR%\qfsm_ini.o %BINDIR%\qfsm_dis.o %BINDIR%\qhsm_ini.o %BINDIR%\qhsm_dis.o %BINDIR%\qhsm_top.o %BINDIR%\qhsm_in.o
@echo off
erase %BINDIR%\*.o
:: QF -----------------------------------------------------------------------
set SRCDIR=..\..\..\qf\source
set CCINC=-I%QP_PRTDIR% -I%QP_INCDIR% -I%FREERTOS_INC% -I%FREERTOS_PORT% -I%FREERTOS_CONF% -I%SRCDIR%
@echo on
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_defer.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_fifo.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_lifo.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_get_.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_sub.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_usub.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qa_usuba.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qeq_fifo.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qeq_get.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qeq_init.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qeq_lifo.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_act.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_gc.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_log2.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_new.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_pool.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_psini.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_pspub.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_pwr2.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qf_tick.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmp_get.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmp_init.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qmp_put.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qte_ctor.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qte_ctr.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qte_arm.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qte_darm.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %SRCDIR%\qte_rarm.cpp
%CC% %CCFLAGS% %CCOPT% %CCINC% -o%BINDIR%\ %QP_PRTDIR%\qf_port.cpp
%LIB% %LIBFLAGS% %LIBDIR%\libqp_%ARM_CORE%.a %BINDIR%\qa_defer.o %BINDIR%\qa_fifo.o %BINDIR%\qa_lifo.o %BINDIR%\qa_get_.o %BINDIR%\qa_sub.o %BINDIR%\qa_usub.o %BINDIR%\qa_usuba.o %BINDIR%\qeq_fifo.o %BINDIR%\qeq_get.o %BINDIR%\qeq_init.o %BINDIR%\qeq_lifo.o %BINDIR%\qf_act.o %BINDIR%\qf_gc.o %BINDIR%\qf_log2.o %BINDIR%\qf_new.o %BINDIR%\qf_pool.o %BINDIR%\qf_psini.o %BINDIR%\qf_pspub.o %BINDIR%\qf_pwr2.o %BINDIR%\qf_tick.o %BINDIR%\qmp_get.o %BINDIR%\qmp_init.o %BINDIR%\qmp_put.o %BINDIR%\qte_ctor.o %BINDIR%\qte_arm.o %BINDIR%\qte_darm.o %BINDIR%\qte_rarm.o %BINDIR%\qte_ctr.o %BINDIR%\qf_port.o
@echo off
erase %BINDIR%\*.o
:: QS -----------------------------------------------------------------------
if not "%1"=="spy" goto clean
set SRCDIR=..\..\..\qs\source
set CCINC=-I%QP_PRTDIR% -I%QP_INCDIR% -I%FREERTOS_INC% -I%FREERTOS_PORT% -I%FREERTOS_CONF% -I%SRCDIR%
@echo on
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_blk.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_byte.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_dict.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_f32.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_f64.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_mem.cpp
%CC% %CCFLAGS% %CCOPT_QS% %CCINC% -o%BINDIR%\ %SRCDIR%\qs_str.cpp
%LIB% %LIBFLAGS% %LIBDIR%\libqp_%ARM_CORE%.a %BINDIR%\qs.o %BINDIR%\qs_.o %BINDIR%\qs_blk.o %BINDIR%\qs_byte.o %BINDIR%\qs_dict.o %BINDIR%\qs_f32.o %BINDIR%\qs_f64.o %BINDIR%\qs_mem.o %BINDIR%\qs_str.o
@echo off
erase %BINDIR%\*.o
:: --------------------------------------------------------------------------
:clean
@echo off
erase %BINDIR%\tmp*.*
endlocal

40
ports/freertos/qep_port.h Normal file
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@ -0,0 +1,40 @@
//****************************************************************************
// Product: QEP/C++ port (generic)
// Last updated for version 5.3.1
// Last updated on 2014-09-29
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, www.state-machine.com.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Web: www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#ifndef qep_port_h
#define qep_port_h
#include <stdint.h> // exact-width integers, WG14/N843 C99 Standard, 7.18.1.1
#include "qep.h" // QEP platform-independent public interface
#endif // qep_port_h

230
ports/freertos/qf_port.c Normal file
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@ -0,0 +1,230 @@
/*****************************************************************************
* Product: QF/C port to embOS
* Last updated for version 5.3.0
* Last updated on 2014-06-25
*
* Q u a n t u m L e a P s
* ---------------------------
* innovating embedded systems
*
* Copyright (C) Quantum Leaps, www.state-machine.com.
*
* This program is open source software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* Alternatively, this program may be distributed and modified under the
* terms of Quantum Leaps commercial licenses, which expressly supersede
* the GNU General Public License and are specifically designed for
* licensees interested in retaining the proprietary status of their code.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* Contact information:
* Web: www.state-machine.com
* Email: info@state-machine.com
*****************************************************************************/
#define QP_IMPL /* this is QP implementation */
#include "qf_port.h" /* QF port */
#include "qf_pkg.h"
#include "qassert.h"
#ifdef Q_SPY /* QS software tracing enabled? */
#include "qs_port.h" /* include QS port */
#else
#include "qs_dummy.h" /* disable the QS software tracing */
#endif /* Q_SPY */
Q_DEFINE_THIS_MODULE("qf_port")
/*..........................................................................*/
void QF_init(void) {
OS_InitKern(); /* initialize embOS */
OS_InitHW(); /* initialize the hardware used by embOS */
}
/*..........................................................................*/
int_t QF_run(void) {
QF_onStartup(); /* startup callback */
OS_Start(); /* start multitasking; NOTE: QS_start() does not return */
return (int_t)0; /* dummy return to make the compiler happy */
}
/*..........................................................................*/
void QF_stop(void) {
QF_onCleanup(); /* cleanup callback */
}
/*..........................................................................*/
static void thread_function(void *pVoid) { /* embOS signature */
QActive *act = (QActive *)pVoid;
#if defined (__ARM7EM__) && (__CORE__ == __ARM7EM__) && defined (__ARMVFP__)
/* does the task use the FPU? see NOTE1 */
if ((act->osObject & QF_TASK_USES_FPU) != (uint8_t)0) {
OS_ExtendTaskContext_VFP();
}
#endif
act->osObject = (uint8_t)1;/* enable thread-loop */
while (act->osObject) {
QEvt const *e = QActive_get_(act);
QMSM_DISPATCH(&act->super, e);
QF_gc(e); /* check if the event is garbage, and collect it if so */
}
QF_remove_(act); /* remove this object from QF */
OS_DeleteMB(&act->eQueue);
OS_TerminateTask(&act->thread);
}
/*..........................................................................*/
void QActive_start_(QActive * const me, uint_fast8_t prio,
QEvt const *qSto[], uint_fast16_t qLen,
void *stkSto, uint_fast16_t stkSize,
QEvt const *ie)
{
/* create the embOS message box for the AO */
OS_CreateMB(&me->eQueue,
(OS_U16)sizeof(QEvt *),
(OS_UINT)qLen,
(void *)&qSto[0]);
me->prio = prio; /* save the QF priority */
QF_add_(me); /* make QF aware of this active object */
QMSM_INIT(&me->super, ie); /* execute initial transition */
QS_FLUSH(); /* flush the trace buffer to the host */
OS_CreateTaskEx(&me->thread,
"AO",
(OS_PRIO)prio, /* embOS uses the same numbering as QP */
&thread_function,
(void OS_STACKPTR *)stkSto,
(OS_UINT)stkSize,
(OS_UINT)0, /* no AOs at the same prio */
(void *)me);
}
/*..........................................................................*/
void QActive_stop(QActive * const me) {
me->osObject = (uint8_t)0; /* stop the thread loop */
}
/*..........................................................................*/
#ifndef Q_SPY
bool QActive_post_(QActive * const me, QEvt const * const e,
uint_fast16_t const margin)
#else
bool QActive_post_(QActive * const me, QEvt const * const e,
uint_fast16_t const margin, void const * const sender)
#endif /* Q_SPY */
{
uint_fast16_t nFree;
bool status;
QF_CRIT_STAT_
QF_CRIT_ENTRY_();
nFree = (uint_fast16_t)(me->eQueue.maxMsg - me->eQueue.nofMsg);
if (nFree > margin) {
QS_BEGIN_NOCRIT_(QS_QF_ACTIVE_POST_FIFO, QS_priv_.aoObjFilter, me)
QS_TIME_(); /* timestamp */
QS_OBJ_(sender); /* the sender object */
QS_SIG_(e->sig); /* the signal of the event */
QS_OBJ_(me); /* this active object (recipient) */
QS_2U8_(e->poolId_, e->refCtr_); /* pool Id & ref Count */
QS_EQC_((QEQueueCtr)nFree); /* # free entries available */
QS_EQC_((QEQueueCtr)0); /* min # free entries (unknown) */
QS_END_NOCRIT_()
if (e->poolId_ != (uint8_t)0) { /* is it a pool event? */
QF_EVT_REF_CTR_INC_(e); /* increment the reference counter */
}
/* posting to the embOS mailbox must succeed, see NOTE2 */
Q_ALLEGE(OS_PutMailCond(&me->eQueue, (OS_CONST_PTR void *)&e)
== (char)0);
status = true; /* return success */
}
else {
/* can tolerate dropping evts? */
Q_ASSERT(margin != (uint_fast16_t)0);
QS_BEGIN_NOCRIT_(QS_QF_ACTIVE_POST_ATTEMPT, QS_priv_.aoObjFilter, me)
QS_TIME_(); /* timestamp */
QS_OBJ_(sender); /* the sender object */
QS_SIG_(e->sig); /* the signal of the event */
QS_OBJ_(me); /* this active object (recipient) */
QS_2U8_(e->poolId_, e->refCtr_); /* pool Id & ref Count */
QS_EQC_((QEQueueCtr)nFree); /* # free entries available */
QS_EQC_((QEQueueCtr)0); /* min # free entries (unknown) */
QS_END_NOCRIT_()
status = false; /* return failure */
}
QF_CRIT_EXIT_();
return status;
}
/*..........................................................................*/
void QActive_postLIFO_(QActive * const me, QEvt const * const e) {
QF_CRIT_STAT_
QF_CRIT_ENTRY_();
QS_BEGIN_NOCRIT_(QS_QF_ACTIVE_POST_LIFO, QS_priv_.aoObjFilter, me)
QS_TIME_(); /* timestamp */
QS_SIG_(e->sig); /* the signal of this event */
QS_OBJ_(me); /* this active object */
QS_2U8_(e->poolId_, e->refCtr_); /* pool Id & ref Count */
/* # free entries */
QS_EQC_((QEQueueCtr)(me->eQueue.maxMsg - me->eQueue.nofMsg));
QS_EQC_((QEQueueCtr)0); /* min # free entries (unknown) */
QS_END_NOCRIT_()
if (e->poolId_ != (uint8_t)0) { /* is it a pool event? */
QF_EVT_REF_CTR_INC_(e); /* increment the reference counter */
}
/* LIFO posting might block if the queue is full */
OS_PutMailFront(&me->eQueue, (OS_CONST_PTR void *)&e);
QF_CRIT_EXIT_();
}
/*..........................................................................*/
QEvt const *QActive_get_(QActive * const me) {
QEvt const *e;
QS_CRIT_STAT_
OS_GetMail(&me->eQueue, (void *)&e);
QS_BEGIN_(QS_QF_ACTIVE_GET, QS_priv_.aoObjFilter, me)
QS_TIME_(); /* timestamp */
QS_SIG_(e->sig); /* the signal of this event */
QS_OBJ_(me); /* this active object */
QS_2U8_(e->poolId_, e->refCtr_); /* pool Id & ref Count */
/* # free entries */
QS_EQC_((QEQueueCtr)(me->eQueue.maxMsg - me->eQueue.nofMsg));
QS_END_()
return e;
}
/*****************************************************************************
* NOTE1:
* In case of hardware-supported floating point unit (FPU), a task must
* preserve the FPU registers accross the context switch. However, this
* additional overhead is necessary only for tasks that actually use the
* FPU. In this QP-embOS port, an active object task that uses the FPU is
* designated by initially setting the bit QF_TASK_USES_FPU in the
* QActive.osObject attribute. Later on the QActive.osObject attribute is
* reused as the event-loop flag to gracefully terminate the AOs event
* loop, in case QActive_stop() is called.
*
* NOTE2:
* The event posting to embOS mailbox occurs inside a critical section,
* but this is OK, because the QF/embOS critical sections are designed
* to nest.
*/

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//****************************************************************************
// Product: QF/C++ generic port to FreeRTOS.org
// Last updated for version 5.3.1
// Last updated on 2014-09-29
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, www.state-machine.com.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Web: www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#define QP_IMPL // this is QP implementation
#include "qf_port.h" // QF port
#include "qf_pkg.h"
#include "qassert.h"
#ifdef Q_SPY // QS software tracing enabled?
#include "qs_port.h" // include QS port
#else
#include "qs_dummy.h" // disable the QS software tracing
#endif // Q_SPY
// global varibles used by this FreeRTOS port (outside the QP namespace)
FreeRTOSExtras FreeRTOS_extras;
namespace QP {
Q_DEFINE_THIS_MODULE("qf_port")
//............................................................................
void QF::init(void) {
FreeRTOS_extras.isrNest = static_cast<BaseType_t>(0);
}
//............................................................................
int_t QF::run(void) {
onStartup(); // startup callback
vTaskStartScheduler(); // start the FreeRTOS.org scheduler
Q_ERROR(); // the FreeRTOS scheduler should never return
return static_cast<int_t>(0); // return success (just in case)
}
//............................................................................
void QF::stop(void) {
onCleanup(); // cleanup callback
}
//............................................................................
extern "C" void task_function(void *pvParameters) { // FreeRTOS task signature
QF::thread_(static_cast<QActive *>(pvParameters));
}
//............................................................................
void QActive::start(uint_fast8_t const prio,
QEvt const *qSto[], uint_fast16_t const qLen,
void * const stkSto, uint_fast16_t const stkSize,
QEvt const * const ie)
{
Q_REQUIRE(
(qSto != static_cast<QEvt const **>(0)) /* queue storage provided */
&& (qLen > static_cast<uint_fast16_t>(0)) /* queue size provided */
&& (stkSto == static_cast<void *>(0)) /* no stack storage */
&& (stkSize > static_cast<uint_fast16_t>(0))); // stack size provided
m_eQueue.init(qSto, qLen); // initialize QEQueue of this AO
m_prio = prio; // set the QF priority of this AO
QF::add_(this); // make QF aware of this AO
this->init(ie); // execute initial transition (virtual call)
// create the FreeRTOS task for the AO...
portBASE_TYPE err = xTaskCreate(
&task_function, // the task function
static_cast<const char *>("AO"), // the name of the task
static_cast<uint16_t>(stkSize/sizeof(portSTACK_TYPE)), // stack size
static_cast<void *>(this), // the 'pvParameters' parameter
static_cast<UBaseType_t>(prio + tskIDLE_PRIORITY),// FreeRTOS priority
&m_thread); // task handle
Q_ENSURE(err == pdPASS); // FreeRTOS task must be created
m_osObject = m_thread; // OS-Object for FreeRTOS is the task handle
}
//............................................................................
void QF::thread_(QActive *act) {
// event-loop of an active object thread
while (act->m_thread != static_cast<TaskHandle_t>(0)) {
QEvt const *e = act->get_(); // wait for event
act->dispatch(e); // dispatch to the active object's state machine
gc(e); // check if the event is garbage, and collect it if so
}
QF::remove_(act); // remove this object from the framework
vTaskDelete(static_cast<TaskHandle_t>(0)); // delete this FreeRTOS task
}
//............................................................................
void QActive::stop(void) {
m_thread = static_cast<TaskHandle_t>(0); // stop the AO thread loop
}
} // namespace QP

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//****************************************************************************
// Product: QF/C++ port to FreeRTOS.org (version 8)
// Last updated for version 5.3.1
// Last updated on 2014-09-29
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, www.state-machine.com.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Web: www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#ifndef qf_port_h
#define qf_port_h
// FreeRTOS message mailbox and thread types
#define QF_EQUEUE_TYPE QEQueue
#define QF_THREAD_TYPE TaskHandle_t
#define QF_OS_OBJECT_TYPE TaskHandle_t
// The maximum number of active objects in the application, see NOTE1
#define QF_MAX_ACTIVE 32
/* QF critical section for FreeRTOS/ARM-Cortex-M, see NOTE2 */
#define QF_CRIT_STAT_TYPE uint32_t
#define QF_CRIT_ENTRY(stat_) ((stat_) = portSET_INTERRUPT_MASK_FROM_ISR())
#define QF_CRIT_EXIT(stat_) portCLEAR_INTERRUPT_MASK_FROM_ISR(stat_)
#define QF_INT_DISABLE() portDISABLE_INTERRUPTS()
#define QF_INT_ENABLE() portENABLE_INTERRUPTS()
#include "FreeRTOS.h" // FreeRTOS master include file
#include "task.h" // FreeRTOS task management
#include "qep_port.h" // QEP port
#include "qequeue.h" // this QP port uses the native QF event queue
#include "qmpool.h" // this QP port uses the native QF memory pool
#include "qpset.h" // native QF set for publish/subscribe
#include "qf.h" // QF platform-independent public interface
// FreeRTOS "extras" for handling ISRs for FreeRTOS/ARM-Cortex-M
struct FreeRTOSExtras {
BaseType_t volatile isrNest;
BaseType_t volatile ctxtReq;
} ;
extern FreeRTOSExtras FreeRTOS_extras;
#define QF_ISR_ENTRY(stat_) do { \
(stat_) = portSET_INTERRUPT_MASK_FROM_ISR(); \
if ((FreeRTOS_extras.isrNest++) == (BaseType_t)0) { \
FreeRTOS_extras.ctxtReq = pdFALSE; \
} \
portCLEAR_INTERRUPT_MASK_FROM_ISR(stat_); \
} while (0)
#define QF_ISR_EXIT(stat_, ctxtReq_) do { \
(stat_) = portSET_INTERRUPT_MASK_FROM_ISR(); \
if (FreeRTOS_extras.ctxtReq != pdFALSE) { \
(ctxtReq_) = pdTRUE; \
} \
--FreeRTOS_extras.isrNest; \
portCLEAR_INTERRUPT_MASK_FROM_ISR(stat_); \
} while (0)
// FreeRTOS hooks prototypes (not provided by FreeRTOS)
#if (configUSE_IDLE_HOOK > 0)
extern "C" void vApplicationIdleHook(void);
#endif
#if (configUSE_TICK_HOOK > 0)
extern "C" void vApplicationTickHook(void);
#endif
#if (configCHECK_FOR_STACK_OVERFLOW > 0)
extern "C" void vApplicationStackOverflowHook(TaskHandle_t xTask,
char *pcTaskName);
#endif
//****************************************************************************
// interface used only inside QF, but not in applications
//
#ifdef QP_IMPL
// FreeRTOS blocking for event queue implementation
#define QACTIVE_EQUEUE_WAIT_(me_) \
while ((me_)->m_eQueue.m_frontEvt == static_cast<QEvt *>(0)) { \
QF_CRIT_EXIT_(); \
vTaskSuspend(static_cast<TaskHandle_t>(0)); \
QF_CRIT_ENTRY_(); \
}
#define QACTIVE_EQUEUE_SIGNAL_(me_) do { \
if (FreeRTOS_extras.isrNest == static_cast<BaseType_t>(0)) { \
QF_CRIT_EXIT_(); \
vTaskResume((me_)->m_osObject); \
QF_CRIT_ENTRY_(); \
} \
else { \
BaseType_t ctxtReq; \
QF_CRIT_EXIT_(); \
ctxtReq = xTaskResumeFromISR((me_)->m_osObject); \
QF_CRIT_ENTRY_(); \
if (ctxtReq != pdFALSE) { \
FreeRTOS_extras.ctxtReq = pdTRUE; \
} \
} \
} while (false)
#define QACTIVE_EQUEUE_ONEMPTY_(me_) ((void)0)
// native QF event pool operations
#define QF_EPOOL_TYPE_ QMPool
#define QF_EPOOL_INIT_(p_, poolSto_, poolSize_, evtSize_) \
(p_).init((poolSto_), (poolSize_), (evtSize_))
#define QF_EPOOL_EVENT_SIZE_(p_) \
static_cast<uint_fast16_t>((p_).getBlockSize())
#define QF_EPOOL_GET_(p_, e_, m_) \
((e_) = static_cast<QEvt *>((p_).get((m_))))
#define QF_EPOOL_PUT_(p_, e_) ((p_).put(e_))
#endif // ifdef QP_IMPL
//****************************************************************************
// NOTE1:
// The maximum number of active objects in QP can be increased to 63,
// inclusive, but it can be reduced to save some memory. Also, the number of
// active objects cannot exceed the number of FreeRTOS task priorities,
// because each QP active object requires a unique priority level.
//
// NOTE2:
// The FreeRTOS critical section defined here is correct only for ARM Cortex-M
// which define the portSET_INTERRUPT_MASK_FROM_ISR() /
// portCLEAR_INTERRUPT_MASK_FROM_ISR() pair of macros, and where the interrupt
// disabling policy from the ISRs is actually the same as from the tasks.
// This critical section might NOT work for other CPUs (!)
//
// NOTE3:
// The "FreeRTOS.h" header file includes the "FreeRTOSConfig.h" header file
// which creates an artificial dependency on the FreeRTOS configuration. This
// port uses a dummy "FreeRTOSConfig.h" from the "config" sub-directory, so that
// applications can still use their own (and potentially different) FreeRTOS
// configuration at compile time.
//
#endif // qf_port_h

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//****************************************************************************
// Product: QS/C++ port to embOS for 32-bit targets
// Last updated for version 5.3.0
// Last updated on 2014-06-27
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, www.state-machine.com.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Contact information:
// Web: www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#ifndef qs_port_h
#define qs_port_h
#define QS_TIME_SIZE 4
#define QS_OBJ_PTR_SIZE 4
#define QS_FUN_PTR_SIZE 4
//****************************************************************************
// NOTE: QS might be used with or without other QP components, in which case
// the separate definitions of the macros Q_ROM, Q_ROM_VAR,
// QF_CRIT_STAT_TYPE, QF_CRIT_ENTRY, and QF_CRIT_EXIT are needed. In this
// port QS is configured to be used with the QF framework component, by
// simply including "qf_port.h" *before* "qs.h".
//
#include "qf_port.h" // use QS with QF
#include "qs.h" // QS platform-independent public interface
#endif // qs_port_h